1b24cc2a1SSakari Ailus /* SPDX-License-Identifier: GPL-2.0-only */
2b24cc2a1SSakari Ailus /*
3b24cc2a1SSakari Ailus  * drivers/media/i2c/smiapp/smiapp-reg-defs.h
4b24cc2a1SSakari Ailus  *
5b24cc2a1SSakari Ailus  * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
6b24cc2a1SSakari Ailus  *
7b24cc2a1SSakari Ailus  * Copyright (C) 2020 Intel Corporation
8b24cc2a1SSakari Ailus  * Copyright (C) 2011--2012 Nokia Corporation
9b24cc2a1SSakari Ailus  * Contact: Sakari Ailus <sakari.ailus@iki.fi>
10b24cc2a1SSakari Ailus  */
11b24cc2a1SSakari Ailus 
12b24cc2a1SSakari Ailus #ifndef __SMIAPP_REG_DEFS_H__
13b24cc2a1SSakari Ailus #define __SMIAPP_REG_DEFS_H__
14b24cc2a1SSakari Ailus 
15b24cc2a1SSakari Ailus /* Register addresses */
16b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MODEL_ID					(0x0000 | CCS_FL_16BIT)
17b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR			0x0002
18b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MANUFACTURER_ID				0x0003
19b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SMIA_VERSION				0x0004
20b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FRAME_COUNT				0x0005
21b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_PIXEL_ORDER				0x0006
22b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DATA_PEDESTAL				(0x0008 | CCS_FL_16BIT)
23b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_PIXEL_DEPTH				0x000c
24b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR			0x0010
25b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SMIAPP_VERSION				0x0011
26b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_DATE_YEAR				0x0012
27b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_DATE_MONTH				0x0013
28b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_DATE_DAY				0x0014
29b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_DATE_PHASE				0x0015
30b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SENSOR_MODEL_ID				(0x0016 | CCS_FL_16BIT)
31b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER			0x0018
32b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID			0x0019
33b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION			0x001a
34b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_SERIAL_NUMBER				(0x001c | CCS_FL_32BIT)
35b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE			0x0040
36b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE		0x0041
37b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n)		((0x0042 + ((n) << 1)) | CCS_FL_16BIT) /* 0 <= n <= 14 */
38b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n)		((0x0060 + ((n) << 2)) | CCS_FL_32BIT) /* 0 <= n <= 7 */
39b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY			(0x0080 | CCS_FL_16BIT)
40b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN			(0x0084 | CCS_FL_16BIT)
41b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX			(0x0086 | CCS_FL_16BIT)
42b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP			(0x0088 | CCS_FL_16BIT)
43b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE			(0x008a | CCS_FL_16BIT)
44b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_M0				(0x008c | CCS_FL_16BIT)
45b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_C0				(0x008e | CCS_FL_16BIT)
46b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_M1				(0x0090 | CCS_FL_16BIT)
47b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_C1				(0x0092 | CCS_FL_16BIT)
48b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE			0x00c0
49b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE			0x00c1
50b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n)		((0x00c2 + ((n) << 1)) | CCS_FL_16BIT)
51b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODE_SELECT				0x0100
52b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_IMAGE_ORIENTATION				0x0101
53b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SOFTWARE_RESET				0x0103
54b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD			0x0104
55b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES			0x0105
56b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FAST_STANDBY_CTRL				0x0106
57b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL			0x0107
58b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL			0x0108
59b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL			0x0109
60b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER			0x0110
61b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI_SIGNALLING_MODE			0x0111
62b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_CSI_DATA_FORMAT				(0x0112 | CCS_FL_16BIT)
63b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI_LANE_MODE				0x0114
64b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_10_TO_8_DT				0x0115
65b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_10_TO_7_DT				0x0116
66b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_10_TO_6_DT				0x0117
67b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_12_TO_8_DT				0x0118
68b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_12_TO_7_DT				0x0119
69b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_12_TO_6_DT				0x011a
70b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_14_TO_10_DT				0x011b
71b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_14_TO_8_DT				0x011c
72b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_16_TO_10_DT				0x011d
73b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI2_16_TO_8_DT				0x011e
74b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GAIN_MODE					0x0120
75b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VANA_VOLTAGE				(0x0130 | CCS_FL_16BIT)
76b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VDIG_VOLTAGE				(0x0132 | CCS_FL_16BIT)
77b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VIO_VOLTAGE				(0x0134 | CCS_FL_16BIT)
78b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ			(0x0136 | CCS_FL_16BIT)
79b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL			0x0138
80b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TEMP_SENSOR_MODE				0x0139
81b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT			0x013a
82b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FINE_INTEGRATION_TIME			(0x0200 | CCS_FL_16BIT)
83b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME			(0x0202 | CCS_FL_16BIT)
84b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL		(0x0204 | CCS_FL_16BIT)
85b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR		(0x0206 | CCS_FL_16BIT)
86b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED			(0x0208 | CCS_FL_16BIT)
87b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE			(0x020a | CCS_FL_16BIT)
88b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB		(0x020c | CCS_FL_16BIT)
89b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR			(0x020e | CCS_FL_16BIT)
90b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_RED				(0x0210 | CCS_FL_16BIT)
91b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE			(0x0212 | CCS_FL_16BIT)
92b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB			(0x0214 | CCS_FL_16BIT)
93b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VT_PIX_CLK_DIV				(0x0300 | CCS_FL_16BIT)
94b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VT_SYS_CLK_DIV				(0x0302 | CCS_FL_16BIT)
95b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_PRE_PLL_CLK_DIV				(0x0304 | CCS_FL_16BIT)
96b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_PLL_MULTIPLIER				(0x0306 | CCS_FL_16BIT)
97b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_OP_PIX_CLK_DIV				(0x0308 | CCS_FL_16BIT)
98b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_OP_SYS_CLK_DIV				(0x030a | CCS_FL_16BIT)
99b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FRAME_LENGTH_LINES			(0x0340 | CCS_FL_16BIT)
100b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_LINE_LENGTH_PCK				(0x0342 | CCS_FL_16BIT)
101b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_ADDR_START				(0x0344 | CCS_FL_16BIT)
102b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_ADDR_START				(0x0346 | CCS_FL_16BIT)
103b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_ADDR_END				(0x0348 | CCS_FL_16BIT)
104b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_ADDR_END				(0x034a | CCS_FL_16BIT)
105b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_OUTPUT_SIZE				(0x034c | CCS_FL_16BIT)
106b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_OUTPUT_SIZE				(0x034e | CCS_FL_16BIT)
107b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_EVEN_INC				(0x0380 | CCS_FL_16BIT)
108b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_ODD_INC				(0x0382 | CCS_FL_16BIT)
109b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_EVEN_INC				(0x0384 | CCS_FL_16BIT)
110b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_ODD_INC				(0x0386 | CCS_FL_16BIT)
111b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALING_MODE				(0x0400 | CCS_FL_16BIT)
112b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SPATIAL_SAMPLING				(0x0402 | CCS_FL_16BIT)
113b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALE_M					(0x0404 | CCS_FL_16BIT)
114b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALE_N					(0x0406 | CCS_FL_16BIT)
115b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET			(0x0408 | CCS_FL_16BIT)
116b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET			(0x040a | CCS_FL_16BIT)
117b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH			(0x040c | CCS_FL_16BIT)
118b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT		(0x040e | CCS_FL_16BIT)
119b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_COMPRESSION_MODE				(0x0500 | CCS_FL_16BIT)
120b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TEST_PATTERN_MODE			(0x0600 | CCS_FL_16BIT)
121b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TEST_DATA_RED				(0x0602 | CCS_FL_16BIT)
122b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TEST_DATA_GREENR				(0x0604 | CCS_FL_16BIT)
123b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TEST_DATA_BLUE				(0x0606 | CCS_FL_16BIT)
124b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TEST_DATA_GREENB				(0x0608 | CCS_FL_16BIT)
125b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH			(0x060a | CCS_FL_16BIT)
126b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION		(0x060c | CCS_FL_16BIT)
127b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH			(0x060e | CCS_FL_16BIT)
128b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION			(0x0610 | CCS_FL_16BIT)
129b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS			(0x0700 | CCS_FL_16BIT)
130b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TCLK_POST					0x0800
131b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_THS_PREPARE				0x0801
132b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_THS_ZERO_MIN				0x0802
133b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_THS_TRAIL					0x0803
134b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TCLK_TRAIL_MIN				0x0804
135b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TCLK_PREPARE				0x0805
136b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TCLK_ZERO					0x0806
137b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TLPX					0x0807
138b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DPHY_CTRL					0x0808
139b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS		(0x0820 | CCS_FL_32BIT)
140b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_MODE				0x0900
141b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_TYPE				0x0901
142b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_WEIGHTING				0x0902
143b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL			0x0a00
144b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS			0x0a01
145b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT		0x0a02
146b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0			0x0a04
147b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1			0x0a05
148b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2			0x0a06
149b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3			0x0a07
150b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4			0x0a08
151b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5			0x0a09
152b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12		0x0a10
153b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13		0x0a11
154b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14		0x0a12
155b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15		0x0a13
156b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16		0x0a14
157b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17		0x0a15
158b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18		0x0a16
159b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19		0x0a17
160b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20		0x0a18
161b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21		0x0a19
162b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22		0x0a1a
163b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23		0x0a1b
164b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24		0x0a1c
165b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25		0x0a1d
166b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26		0x0a1e
167b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27		0x0a1f
168b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28		0x0a20
169b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29		0x0a21
170b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30		0x0a22
171b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31		0x0a23
172b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32		0x0a24
173b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33		0x0a25
174b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34		0x0a26
175b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35		0x0a27
176b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36		0x0a28
177b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37		0x0a29
178b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38		0x0a2a
179b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39		0x0a2b
180b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40		0x0a2c
181b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41		0x0a2d
182b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42		0x0a2e
183b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43		0x0a2f
184b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44		0x0a30
185b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45		0x0a31
186b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46		0x0a32
187b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47		0x0a33
188b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48		0x0a34
189b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49		0x0a35
190b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50		0x0a36
191b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51		0x0a37
192b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52		0x0a38
193b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53		0x0a39
194b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54		0x0a3a
195b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55		0x0a3b
196b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56		0x0a3c
197b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57		0x0a3d
198b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58		0x0a3e
199b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59		0x0a3f
200b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60		0x0a40
201b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61		0x0a41
202b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62		0x0a42
203b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63		0x0a43
204b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL			0x0a44
205b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS			0x0a45
206b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT		0x0a46
207b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0			0x0a48
208b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1			0x0a49
209b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2			0x0a4a
210b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3			0x0a4b
211b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4			0x0a4c
212b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5			0x0a4d
213b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6			0x0a4e
214b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7			0x0a4f
215b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8			0x0a50
216b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9			0x0a51
217b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10		0x0a52
218b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11		0x0a53
219b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12		0x0a54
220b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13		0x0a55
221b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14		0x0a56
222b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15		0x0a57
223b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16		0x0a58
224b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17		0x0a59
225b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18		0x0a5a
226b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19		0x0a5b
227b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20		0x0a5c
228b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21		0x0a5d
229b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22		0x0a5e
230b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23		0x0a5f
231b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24		0x0a60
232b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25		0x0a61
233b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26		0x0a62
234b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27		0x0a63
235b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28		0x0a64
236b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29		0x0a65
237b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30		0x0a66
238b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31		0x0a67
239b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32		0x0a68
240b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33		0x0a69
241b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34		0x0a6a
242b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35		0x0a6b
243b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36		0x0a6c
244b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37		0x0a6d
245b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38		0x0a6e
246b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39		0x0a6f
247b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40		0x0a70
248b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41		0x0a71
249b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42		0x0a72
250b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43		0x0a73
251b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44		0x0a74
252b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45		0x0a75
253b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46		0x0a76
254b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47		0x0a77
255b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48		0x0a78
256b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49		0x0a79
257b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50		0x0a7a
258b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51		0x0a7b
259b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52		0x0a7c
260b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53		0x0a7d
261b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54		0x0a7e
262b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55		0x0a7f
263b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56		0x0a80
264b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57		0x0a81
265b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58		0x0a82
266b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59		0x0a83
267b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60		0x0a84
268b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61		0x0a85
269b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62		0x0a86
270b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63		0x0a87
271b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE			0x0b00
272b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL		0x0b01
273b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE		0x0b02
274b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT		0x0b03
275b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE		0x0b04
276b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE		0x0b05
277b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE		0x0b06
278b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT		0x0b07
279b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE		0x0b08
280b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT		0x0b09
281b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE		0x0b0a
282b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT		0x0b0b
283b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE		0x0b0c
284b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT		0x0b0d
285b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE		0x0b0e
286b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST		0x0b0f
287b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST		0x0b10
288b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE	0x0b11
289b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST	0x0b12
290b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE	0x0b13
291b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST	0x0b14
292b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE	0x0b15
293b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST	0x0b16
294b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_EDOF_MODE					0x0b80
295b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SHARPNESS					0x0b83
296b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DENOISING					0x0b84
297b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_SPECIFIC				0x0b85
298b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DEPTH_OF_FIELD				(0x0b86 | CCS_FL_16BIT)
299b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FOCUS_DISTANCE				(0x0b88 | CCS_FL_16BIT)
300b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL			0x0b8a
301b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_COLOUR_TEMPERATURE			(0x0b8c | CCS_FL_16BIT)
302b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR			(0x0b8e | CCS_FL_16BIT)
303b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED			(0x0b90 | CCS_FL_16BIT)
304b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE			(0x0b92 | CCS_FL_16BIT)
305b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB			(0x0b94 | CCS_FL_16BIT)
306b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE			0x0bc0
307b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING			(0x0bc2 | CCS_FL_16BIT)
308b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_CUSTOM_ZONE_X_START			(0x0bc4 | CCS_FL_16BIT)
309b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START			(0x0bc6 | CCS_FL_16BIT)
310b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH			(0x0bc8 | CCS_FL_16BIT)
311b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT			(0x0bca | CCS_FL_16BIT)
312b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1			0x0c00
313b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2			0x0c01
314b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1		0x0c02
315b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2		0x0c03
316b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TRDY_CTRL				(0x0c04 | CCS_FL_16BIT)
317b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TRDOUT_CTRL				(0x0c06 | CCS_FL_16BIT)
318b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL		(0x0c08 | CCS_FL_16BIT)
319b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL		(0x0c0a | CCS_FL_16BIT)
320b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL			(0x0c0c | CCS_FL_16BIT)
321b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL		(0x0c0e | CCS_FL_16BIT)
322b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL			(0x0c10 | CCS_FL_16BIT)
323b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT			0x0c12
324b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FLASH_STROBE_START_POINT			(0x0c14 | CCS_FL_16BIT)
325b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL		(0x0c16 | CCS_FL_16BIT)
326b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL		(0x0c18 | CCS_FL_16BIT)
327b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FLASH_MODE_RS				0x0c1a
328b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FLASH_TRIGGER_RS				0x0c1b
329b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FLASH_STATUS				0x0c1c
330b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SA_STROBE_MODE				0x0c1d
331b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SA_STROBE_START_POINT			(0x0c1e | CCS_FL_16BIT)
332b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL			(0x0c20 | CCS_FL_16BIT)
333b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL			(0x0c22 | CCS_FL_16BIT)
334b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SA_STROBE_TRIGGER				0x0c24
335b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS			0x0c25
336b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL	(0x0c26 | CCS_FL_16BIT)
337b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL		(0x0c28 | CCS_FL_16BIT)
338b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL		0x0c2a
339b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL			0x0c2b
340b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL		(0x0c2c | CCS_FL_16BIT)
341b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL		(0x0c2e | CCS_FL_16BIT)
342b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_LOW_LEVEL_CTRL				0x0c80
343b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT			(0x0c82 | CCS_FL_16BIT)
344b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAIN_TRIGGER_T3				(0x0c84 | CCS_FL_16BIT)
345b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT			0x0c86
346b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_PHASE1_TRIGGER_T3			(0x0c88 | CCS_FL_16BIT)
347b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT			0x0c8a
348b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_PHASE2_TRIGGER_T3			(0x0c8c | CCS_FL_16BIT)
349b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT			0x0c8e
350b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MECH_SHUTTER_CTRL				0x0d00
351b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_OPERATION_MODE				0x0d01
352b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ACT_STATE1				0x0d02
353b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ACT_STATE2				0x0d03
354b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FOCUS_CHANGE				(0x0d80 | CCS_FL_16BIT)
355b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL			(0x0d82 | CCS_FL_16BIT)
356b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1		(0x0d84 | CCS_FL_16BIT)
357b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2		(0x0d86 | CCS_FL_16BIT)
358b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_STROBE_COUNT_PHASE1			0x0d88
359b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_STROBE_COUNT_PHASE2			0x0d89
360b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_POSITION					0x0d8a
361b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL			0x0e00
362b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BRACKETING_LUT_MODE			0x0e01
363b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL		0x0e02
364b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_LUT_PARAMETERS_START			0x0e10
365b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_LUT_PARAMETERS_END			0x0eff
366b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY		(0x1000 | CCS_FL_16BIT)
367b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN		(0x1004 | CCS_FL_16BIT)
368b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN	(0x1006 | CCS_FL_16BIT)
369b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN		(0x1008 | CCS_FL_16BIT)
370b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN		(0x100a | CCS_FL_16BIT)
371b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY			(0x1080 | CCS_FL_16BIT)
372b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_MIN				(0x1084 | CCS_FL_16BIT)
373b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_MAX				(0x1086 | CCS_FL_16BIT)
374b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE			(0x1088 | CCS_FL_16BIT)
375b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ			(0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
376b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ			(0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
377b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV			(0x1108 | CCS_FL_16BIT)
378b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV			(0x110a | CCS_FL_16BIT)
379b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ			(0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
380b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ			(0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
381b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER			(0x1114 | CCS_FL_16BIT)
382b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER			(0x1116 | CCS_FL_16BIT)
383b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ			(0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
384b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ			(0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
385b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV			(0x1120 | CCS_FL_16BIT)
386b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV			(0x1122 | CCS_FL_16BIT)
387b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ			(0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
388b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ			(0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
389b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ			(0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
390b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ			(0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
391b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV			(0x1134 | CCS_FL_16BIT)
392b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV			(0x1136 | CCS_FL_16BIT)
393b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES			(0x1140 | CCS_FL_16BIT)
394b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES			(0x1142 | CCS_FL_16BIT)
395b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK			(0x1144 | CCS_FL_16BIT)
396b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK			(0x1146 | CCS_FL_16BIT)
397b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK			(0x1148 | CCS_FL_16BIT)
398b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES			(0x114a | CCS_FL_16BIT)
399b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE		0x114c
400b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV			(0x1160 | CCS_FL_16BIT)
401b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV			(0x1162 | CCS_FL_16BIT)
402b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ			(0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
403b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ			(0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
404b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV			(0x116c | CCS_FL_16BIT)
405b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV			(0x116e | CCS_FL_16BIT)
406b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ			(0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
407b24cc2a1SSakari Ailus #define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ			(0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
408b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_ADDR_MIN				(0x1180 | CCS_FL_16BIT)
409b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_ADDR_MIN				(0x1182 | CCS_FL_16BIT)
410b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_X_ADDR_MAX				(0x1184 | CCS_FL_16BIT)
411b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_Y_ADDR_MAX				(0x1186 | CCS_FL_16BIT)
412b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE			(0x1188 | CCS_FL_16BIT)
413b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE			(0x118a | CCS_FL_16BIT)
414b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE			(0x118c | CCS_FL_16BIT)
415b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE			(0x118e | CCS_FL_16BIT)
416b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_EVEN_INC				(0x11c0 | CCS_FL_16BIT)
417b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_EVEN_INC				(0x11c2 | CCS_FL_16BIT)
418b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_ODD_INC				(0x11c4 | CCS_FL_16BIT)
419b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_ODD_INC				(0x11c6 | CCS_FL_16BIT)
420b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALING_CAPABILITY			(0x1200 | CCS_FL_16BIT)
421b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALER_M_MIN				(0x1204 | CCS_FL_16BIT)
422b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALER_M_MAX				(0x1206 | CCS_FL_16BIT)
423b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALER_N_MIN				(0x1208 | CCS_FL_16BIT)
424b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SCALER_N_MAX				(0x120a | CCS_FL_16BIT)
425b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY		(0x120c | CCS_FL_16BIT)
426b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY			0x120e
427b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_COMPRESSION_CAPABILITY			(0x1300 | CCS_FL_16BIT)
428b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED			(0x1400 | CCS_FL_16BIT)
429b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED		(0x1402 | CCS_FL_16BIT)
430b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED			(0x1404 | CCS_FL_16BIT)
431b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN		(0x1406 | CCS_FL_16BIT)
432b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN		(0x1408 | CCS_FL_16BIT)
433b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN		(0x140a | CCS_FL_16BIT)
434b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE			(0x140c | CCS_FL_16BIT)
435b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE		(0x140e | CCS_FL_16BIT)
436b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE		(0x1410 | CCS_FL_16BIT)
437b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FIFO_SIZE_PIXELS				(0x1500 | CCS_FL_16BIT)
438b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY			0x1502
439b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY			0x1600
440b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY			0x1601
441b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY		0x1602
442b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY			0x1603
443b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY		0x1604
444b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS	(0x1608 | CCS_FL_32BIT)
445b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS	(0x160c | CCS_FL_32BIT)
446b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS	(0x1610 | CCS_FL_32BIT)
447b24cc2a1SSakari Ailus #define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS	(0x1614 | CCS_FL_32BIT)
448b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY			0x1618
449b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN		(0x1700 | CCS_FL_16BIT)
450b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN		(0x1702 | CCS_FL_16BIT)
451b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN			(0x1704 | CCS_FL_16BIT)
452b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN			(0x1706 | CCS_FL_16BIT)
453b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN		(0x1708 | CCS_FL_16BIT)
454b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN		(0x170a | CCS_FL_16BIT)
455b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN	(0x170c | CCS_FL_16BIT)
456b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_CAPABILITY			0x1710
457b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY		0x1711
458b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_SUBTYPES				0x1712
459b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BINNING_TYPE_n(n)				(0x1713 + (n)) /* 1 <= n <= 237 */
460b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY		0x1800
461b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY		0x1900
462b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY		0x1901
463b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY			0x1902
464b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY	0x1903
465b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY		(0x1904 | CCS_FL_16BIT)
466b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2		(0x1906 | CCS_FL_16BIT)
467b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_EDOF_CAPABILITY				0x1980
468b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ESTIMATION_FRAMES				0x1981
469b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ			0x1982
470b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ			0x1983
471b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ		0x1984
472b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ		0x1985
473b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ		0x1986
474b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY		0x1987
475b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM			0x1988
476b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY		0x19c0
477b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY		0x19c1
478b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD			(0x19c2 | CCS_FL_16BIT)
479b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_EST_FOCUS_DISTANCE			(0x19c4 | CCS_FL_16BIT)
480b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN			(0x1a00 | CCS_FL_16BIT)
481b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY			0x1a02
482b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR		(0x1b02 | CCS_FL_16BIT)
483b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_ACTUATOR_CAPABILITY			0x1b04
484b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_ACTUATOR_TYPE				(0x1b40 | CCS_FL_16BIT)
485b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_AF_DEVICE_ADDRESS				0x1b42
486b24cc2a1SSakari Ailus #define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS			(0x1b44 | CCS_FL_16BIT)
487b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1		0x1c00
488b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2		0x1c01
489b24cc2a1SSakari Ailus #define SMIAPP_REG_U8_BRACKETING_LUT_SIZE			0x1c02
490b24cc2a1SSakari Ailus 
491b24cc2a1SSakari Ailus /* Register bit definitions */
492b24cc2a1SSakari Ailus #define SMIAPP_IMAGE_ORIENTATION_HFLIP			BIT(0)
493b24cc2a1SSakari Ailus #define SMIAPP_IMAGE_ORIENTATION_VFLIP			BIT(1)
494b24cc2a1SSakari Ailus 
495b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN		BIT(0)
496b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN		BIT(1)
497b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR	BIT(2)
498b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY	BIT(0)
499b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY	BIT(1)
500b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA		BIT(2)
501b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE		BIT(3)
502b24cc2a1SSakari Ailus 
503b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED	BIT(0)
504b24cc2a1SSakari Ailus #define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL		BIT(2)
505b24cc2a1SSakari Ailus 
506b24cc2a1SSakari Ailus #define SMIAPP_SOFTWARE_RESET				BIT(0)
507b24cc2a1SSakari Ailus 
508b24cc2a1SSakari Ailus #define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE	BIT(0)
509b24cc2a1SSakari Ailus #define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE	BIT(1)
510b24cc2a1SSakari Ailus 
511b24cc2a1SSakari Ailus #define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK	0
512b24cc2a1SSakari Ailus #define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE	1
513b24cc2a1SSakari Ailus #define SMIAPP_CSI_SIGNALLING_MODE_CSI2			2
514b24cc2a1SSakari Ailus 
515b24cc2a1SSakari Ailus #define SMIAPP_DPHY_CTRL_AUTOMATIC			0
516b24cc2a1SSakari Ailus /* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
517b24cc2a1SSakari Ailus #define SMIAPP_DPHY_CTRL_UI				1
518b24cc2a1SSakari Ailus #define SMIAPP_DPHY_CTRL_REGISTER			2
519b24cc2a1SSakari Ailus 
520b24cc2a1SSakari Ailus #define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR	1
521b24cc2a1SSakari Ailus #define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR	2
522b24cc2a1SSakari Ailus 
523b24cc2a1SSakari Ailus #define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY		0
524b24cc2a1SSakari Ailus #define SMIAPP_MODE_SELECT_STREAMING			1
525b24cc2a1SSakari Ailus 
526b24cc2a1SSakari Ailus #define SMIAPP_SCALING_MODE_NONE			0
527b24cc2a1SSakari Ailus #define SMIAPP_SCALING_MODE_HORIZONTAL			1
528b24cc2a1SSakari Ailus #define SMIAPP_SCALING_MODE_BOTH			2
529b24cc2a1SSakari Ailus 
530b24cc2a1SSakari Ailus #define SMIAPP_SCALING_CAPABILITY_NONE			0
531b24cc2a1SSakari Ailus #define SMIAPP_SCALING_CAPABILITY_HORIZONTAL		1
532b24cc2a1SSakari Ailus #define SMIAPP_SCALING_CAPABILITY_BOTH			2 /* horizontal/both */
533b24cc2a1SSakari Ailus 
534b24cc2a1SSakari Ailus /* digital crop right before scaler */
535b24cc2a1SSakari Ailus #define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE		0
536b24cc2a1SSakari Ailus #define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP	1
537b24cc2a1SSakari Ailus 
538*82187857SSakari Ailus #define SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL	1
539*82187857SSakari Ailus 
540b24cc2a1SSakari Ailus #define SMIAPP_BINNING_CAPABILITY_NO			0
541b24cc2a1SSakari Ailus #define SMIAPP_BINNING_CAPABILITY_YES			1
542b24cc2a1SSakari Ailus 
543b24cc2a1SSakari Ailus /* Maximum number of binning subtypes */
544b24cc2a1SSakari Ailus #define SMIAPP_BINNING_SUBTYPES				253
545b24cc2a1SSakari Ailus 
546b24cc2a1SSakari Ailus #define SMIAPP_PIXEL_ORDER_GRBG				0
547b24cc2a1SSakari Ailus #define SMIAPP_PIXEL_ORDER_RGGB				1
548b24cc2a1SSakari Ailus #define SMIAPP_PIXEL_ORDER_BGGR				2
549b24cc2a1SSakari Ailus #define SMIAPP_PIXEL_ORDER_GBRG				3
550b24cc2a1SSakari Ailus 
551b24cc2a1SSakari Ailus #define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL		1
552b24cc2a1SSakari Ailus #define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED		2
553b24cc2a1SSakari Ailus #define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N		8
554b24cc2a1SSakari Ailus #define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N	16
555b24cc2a1SSakari Ailus 
556b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE		0x01
557b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE		0x02
558b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK	0x0f
559b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK	0xf0
560b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT	4
561b24cc2a1SSakari Ailus 
562b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK	0xf000
563b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT	12
564b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK		0x0fff
565b24cc2a1SSakari Ailus 
566b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK	0xf0000000
567b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT	28
568b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK		0x0000ffff
569b24cc2a1SSakari Ailus 
570b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED	1
571b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY	2
572b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK	3
573b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK		4
574b24cc2a1SSakari Ailus #define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE	5
575b24cc2a1SSakari Ailus 
576b24cc2a1SSakari Ailus #define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES	0
577b24cc2a1SSakari Ailus #define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE		1
578b24cc2a1SSakari Ailus 
579b24cc2a1SSakari Ailus /* Scaling N factor */
580b24cc2a1SSakari Ailus #define SMIAPP_SCALE_N					16
581b24cc2a1SSakari Ailus 
582b24cc2a1SSakari Ailus #endif /* __SMIAPP_REG_DEFS_H__ */
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