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/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/openbmc/u-boot/include/configs/
H A Dimx6dl-mamoj.h29 # define CONFIG_ENV_OFFSET 0x100000
35 "scriptaddr=0x14000000\0" \
36 "fdt_addr_r=0x13000000\0" \
37 "kernel_addr_r=0x10008000\0" \
38 "fdt_high=0xffffffff\0" \
39 "dfu_alt_info_spl=spl raw 0x2 0x400\0" \
40 "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
62 #define CONFIG_MXC_USB_FLAGS 0
69 #define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
73 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
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H A Dembestmx6boards.h39 #define CONFIG_MXC_USB_FLAGS 0
42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
54 #define CONFIG_SYS_MEMTEST_START 0x10000000
55 #define CONFIG_SYS_MEMTEST_END 0x10010000
56 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
104 #define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
108 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */
109 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */
110 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */
117 "bootm_size=0x10000000\0" \
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H A Dnitrogen6x.h35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
43 #define CONFIG_DWC_AHSATA_PORT_ID 0
58 #define CONFIG_MXC_USB_FLAGS 0
74 #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
80 #define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
86 #define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
105 #define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
121 "console=ttymxc1\0" \
122 "fdt_high=0xffffffff\0" \
123 "initrd_high=0xffffffff\0" \
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H A Dmx6cuboxi.h25 #define CONFIG_DWC_AHSATA_PORT_ID 0
34 #define CONFIG_FEC_MXC_PHYADDR 0
51 #define CONFIG_MXC_USB_FLAGS 0
69 #define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
73 "som_rev=undefined\0" \
74 "has_emmc=undefined\0" \
75 "fdtfile=undefined\0" \
76 "fdt_addr_r=0x18000000\0" \
77 "fdt_addr=0x18000000\0" \
78 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
[all …]
H A Dwandboard.h27 #define CONFIG_DWC_AHSATA_PORT_ID 0
32 #define CONFIG_SYS_MEMTEST_START 0x10000000
47 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
51 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
56 #define CONFIG_MXC_USB_FLAGS 0
80 "console=ttymxc0\0" \
81 "splashpos=m,m\0" \
82 "fdtfile=undefined\0" \
83 "fdt_high=0xffffffff\0" \
84 "initrd_high=0xffffffff\0" \
[all …]
H A Dudoo.h28 #define CONFIG_DWC_AHSATA_PORT_ID 0
41 #define CONFIG_SYS_MEMTEST_START 0x10000000
45 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
48 "console=ttymxc1,115200\0" \
49 "fdt_high=0xffffffff\0" \
50 "initrd_high=0xffffffff\0" \
51 "fdtfile=undefined\0" \
52 "fdt_addr=0x18000000\0" \
53 "fdt_addr_r=0x18000000\0" \
54 "ip_dyn=yes\0" \
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H A Dmeson64.h12 #define GICD_BASE 0xffc01000
13 #define GICC_BASE 0xffc02000
15 #define GICD_BASE 0xc4301000
16 #define GICC_BASE 0xc4302000
41 #define CONFIG_ENV_SIZE 0x2000
46 #define CONFIG_SYS_SDRAM_BASE 0
47 #define CONFIG_SYS_INIT_SP_ADDR 0x20000000
58 "fi\0"
64 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
72 func(MMC, mmc, 0) \
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H A Dkp_imx6q_tpc.h31 #define CONFIG_FEC_MXC_PHYADDR 0
49 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
51 #define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
65 #define CONFIG_MXC_USB_FLAGS 0
75 #define CONFIG_LOADADDR 0x12000000
80 "console=ttymxc0,115200\0" \
81 "fdt_addr=0x18000000\0" \
82 "fdt_high=0xffffffff\0" \
83 "initrd_high=0xffffffff\0" \
84 "kernel_addr_r=0x10008000\0" \
[all …]
H A Ddh_imx6.h17 * 0x00_0000-0x00_ffff ... U-Boot SPL
18 * 0x01_0000-0x0f_ffff ... U-Boot
19 * 0x10_0000-0x10_ffff ... U-Boot env #1
20 * 0x11_0000-0x11_ffff ... U-Boot env #2
21 * 0x12_0000-0x1f_ffff ... UNUSED
26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
48 #define CONFIG_FEC_MXC_PHYADDR 0
66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define CONFIG_DWC_AHSATA_PORT_ID 0
91 #define CONFIG_MXC_USB_FLAGS 0
[all …]
H A Dimx6_logic.h24 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
31 #define CONFIG_FEC_MXC_PHYADDR 0
34 "script=boot.scr\0" \
35 "image=zImage\0" \
36 "bootm_size=0x10000000\0" \
37 "fdt_addr_r=0x13000000\0" \
38 "ramdisk_addr_r=0x14000000\0" \
39 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
40 "ramdisk_file=rootfs.cpio.uboot\0" \
41 "boot_fdt=try\0" \
[all …]
H A Dcm_fx6.h27 #define CONFIG_SYS_MEMTEST_START 0x10000000
28 #define CONFIG_SYS_MEMTEST_END 0x10010000
55 "fdt_high=0xffffffff\0" \
56 "initrd_high=0xffffffff\0" \
57 "fdt_addr_r=0x18000000\0" \
58 "ramdisk_addr_r=0x13000000\0" \
59 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
60 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
61 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
62 "fdtfile=undefined\0" \
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H A Dmccmon6.h16 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
18 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
19 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
21 #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
28 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
29 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
30 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
43 #define CONFIG_SYS_MEMTEST_START 0x10000000
55 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define CONFIG_MXC_USB_FLAGS 0
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/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mfgcfg.txt23 reg = <0 0x13000000 0 0x1000>;
H A Dmediatek,g3dsys.txt27 reg = <0 0x13000000 0 0x200>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt6795-clock.yaml51 reg = <0 0x13000000 0 0x1000>;
57 reg = <0 0x16000000 0 0x1000>;
63 reg = <0 0x18000000 0 0x1000>;
/openbmc/u-boot/board/bticino/mamoj/
H A DREADME44 0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf
48 hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000
53 hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000
69 => mmc partconf 2 1 0 0
73 => ums 0 mmc 2
80 => dfu 0 mmc 2
89 => dfu 0 mmc 2
111 => mmc write $kernel_addr_r 0x1000 0x4000
118 => mmc write 0x13000000 0x800 0x800
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
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/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
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/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1.dtsi38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi22 reg = <0 0x13000000 0 0x200>;
29 reg = <0 0x13040000 0 0x30000>;
55 reg = <0 0x14000000 0 0x1000>;
62 reg = <0 0x14010000 0 0x1000>;
64 mediatek,larb-id = <0>;
74 reg = <0 0x16010000 0 0x1000>;
86 reg = <0 0x15001000 0 0x1000>;
99 reg = <0 0x15000000 0 0x1000>;
106 reg = <0 0x10205000 0 0x1000>;
117 reg = <0 0x15004000 0 0x1000>;
[all …]
/openbmc/linux/fs/freevxfs/
H A Dvxfs.h20 #define VXFS_SUPER_MAGIC 0xa501FCF5
176 * File modes. File types above 0xf000 are vxfs internal only, they should
181 VXFS_ISUID = 0x00000800, /* setuid */
182 VXFS_ISGID = 0x00000400, /* setgid */
183 VXFS_ISVTX = 0x00000200, /* sticky bit */
184 VXFS_IREAD = 0x00000100, /* read */
185 VXFS_IWRITE = 0x00000080, /* write */
186 VXFS_IEXEC = 0x00000040, /* exec */
188 VXFS_IFIFO = 0x00001000, /* Named pipe */
189 VXFS_IFCHR = 0x00002000, /* Character device */
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_power.c18 #define AGC_MSG_STATE (AGC_MSG_BASE + 0)
24 #define AGC_INIT_MSG_VALUE 0xBABEFACE
42 { 0xB9A1, 0x00010303 },
43 { 0xB9A2, 0x13000000 },
44 { 0xB9A3, 0x00460020 },
45 { 0xB9A4, 0x10000000 },
46 { 0xB9A5, 0x040A1707 },
47 { 0xB9A6, 0x00010000 },
48 { 0xB9A7, 0x0E000904 },
49 { 0xB9A8, 0x10000000 },
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra210.dtsi17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29 bus-range = <0x00 0xff>;
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]

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