1*d7445676SArnd Bergmann /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*d7445676SArnd Bergmann /* 3*d7445676SArnd Bergmann * This file contains the hardware definitions of the Integrator. 4*d7445676SArnd Bergmann * 5*d7445676SArnd Bergmann * Copyright (C) 1998-1999 ARM Limited. 6*d7445676SArnd Bergmann */ 7*d7445676SArnd Bergmann #ifndef INTEGRATOR_HARDWARE_H 8*d7445676SArnd Bergmann #define INTEGRATOR_HARDWARE_H 9*d7445676SArnd Bergmann 10*d7445676SArnd Bergmann /* 11*d7445676SArnd Bergmann * Where in virtual memory the IO devices (timers, system controllers 12*d7445676SArnd Bergmann * and so on) 13*d7445676SArnd Bergmann */ 14*d7445676SArnd Bergmann #define IO_BASE 0xF0000000 // VA of IO 15*d7445676SArnd Bergmann #define IO_SIZE 0x0B000000 // How much? 16*d7445676SArnd Bergmann #define IO_START INTEGRATOR_HDR_BASE // PA of IO 17*d7445676SArnd Bergmann 18*d7445676SArnd Bergmann /* macro to get at IO space when running virtually */ 19*d7445676SArnd Bergmann #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) 20*d7445676SArnd Bergmann #define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) 21*d7445676SArnd Bergmann 22*d7445676SArnd Bergmann /* 23*d7445676SArnd Bergmann * Integrator memory map 24*d7445676SArnd Bergmann */ 25*d7445676SArnd Bergmann #define INTEGRATOR_BOOT_ROM_LO 0x00000000 26*d7445676SArnd Bergmann #define INTEGRATOR_BOOT_ROM_HI 0x20000000 27*d7445676SArnd Bergmann #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ 28*d7445676SArnd Bergmann #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K 29*d7445676SArnd Bergmann 30*d7445676SArnd Bergmann /* 31*d7445676SArnd Bergmann * New Core Modules have different amounts of SSRAM, the amount of SSRAM 32*d7445676SArnd Bergmann * fitted can be found in HDR_STAT. 33*d7445676SArnd Bergmann * 34*d7445676SArnd Bergmann * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to 35*d7445676SArnd Bergmann * the minimum amount of SSRAM fitted on any core module. 36*d7445676SArnd Bergmann * 37*d7445676SArnd Bergmann * New Core Modules also alias the SSRAM. 38*d7445676SArnd Bergmann * 39*d7445676SArnd Bergmann */ 40*d7445676SArnd Bergmann #define INTEGRATOR_SSRAM_BASE 0x00000000 41*d7445676SArnd Bergmann #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 42*d7445676SArnd Bergmann #define INTEGRATOR_SSRAM_SIZE SZ_256K 43*d7445676SArnd Bergmann 44*d7445676SArnd Bergmann #define INTEGRATOR_FLASH_BASE 0x24000000 45*d7445676SArnd Bergmann #define INTEGRATOR_FLASH_SIZE SZ_32M 46*d7445676SArnd Bergmann 47*d7445676SArnd Bergmann #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 48*d7445676SArnd Bergmann #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K 49*d7445676SArnd Bergmann 50*d7445676SArnd Bergmann /* 51*d7445676SArnd Bergmann * SDRAM is a SIMM therefore the size is not known. 52*d7445676SArnd Bergmann */ 53*d7445676SArnd Bergmann #define INTEGRATOR_SDRAM_BASE 0x00040000 54*d7445676SArnd Bergmann 55*d7445676SArnd Bergmann #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 56*d7445676SArnd Bergmann #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 57*d7445676SArnd Bergmann #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 58*d7445676SArnd Bergmann #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 59*d7445676SArnd Bergmann #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 60*d7445676SArnd Bergmann 61*d7445676SArnd Bergmann /* 62*d7445676SArnd Bergmann * Logic expansion modules 63*d7445676SArnd Bergmann * 64*d7445676SArnd Bergmann */ 65*d7445676SArnd Bergmann #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 66*d7445676SArnd Bergmann #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 67*d7445676SArnd Bergmann #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 68*d7445676SArnd Bergmann #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 69*d7445676SArnd Bergmann #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 70*d7445676SArnd Bergmann 71*d7445676SArnd Bergmann /* 72*d7445676SArnd Bergmann * Integrator header card registers 73*d7445676SArnd Bergmann */ 74*d7445676SArnd Bergmann #define INTEGRATOR_HDR_ID_OFFSET 0x00 75*d7445676SArnd Bergmann #define INTEGRATOR_HDR_PROC_OFFSET 0x04 76*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_OFFSET 0x08 77*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C 78*d7445676SArnd Bergmann #define INTEGRATOR_HDR_STAT_OFFSET 0x10 79*d7445676SArnd Bergmann #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 80*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 81*d7445676SArnd Bergmann #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ 82*d7445676SArnd Bergmann #define INTEGRATOR_HDR_IC_OFFSET 0x40 83*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 84*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 85*d7445676SArnd Bergmann 86*d7445676SArnd Bergmann #define INTEGRATOR_HDR_BASE 0x10000000 87*d7445676SArnd Bergmann #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) 88*d7445676SArnd Bergmann #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) 89*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) 90*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) 91*d7445676SArnd Bergmann #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) 92*d7445676SArnd Bergmann #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) 93*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) 94*d7445676SArnd Bergmann #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) 95*d7445676SArnd Bergmann #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) 96*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) 97*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) 98*d7445676SArnd Bergmann 99*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_LED 0x01 100*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 101*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_REMAP 0x04 102*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_RESET 0x08 103*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 104*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 105*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 106*d7445676SArnd Bergmann #define INTEGRATOR_HDR_CTRL_SYNC 0x80 107*d7445676SArnd Bergmann 108*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 109*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 110*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C 111*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 112*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 113*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B 114*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 115*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 116*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A 117*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F 118*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 119*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 120*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E 121*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 122*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 123*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D 124*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 125*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 126*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C 127*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 128*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 129*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B 130*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 131*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 132*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A 133*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F 134*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 135*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 136*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E 137*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 138*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 139*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF 140*d7445676SArnd Bergmann 141*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 142*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 143*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 144*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 145*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 146*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 147*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 148*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 149*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 150*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 151*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 152*d7445676SArnd Bergmann 153*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 154*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 155*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 156*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 157*d7445676SArnd Bergmann #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 158*d7445676SArnd Bergmann 159*d7445676SArnd Bergmann #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) 160*d7445676SArnd Bergmann 161*d7445676SArnd Bergmann /* 162*d7445676SArnd Bergmann * Integrator system registers 163*d7445676SArnd Bergmann */ 164*d7445676SArnd Bergmann 165*d7445676SArnd Bergmann /* 166*d7445676SArnd Bergmann * System Controller 167*d7445676SArnd Bergmann */ 168*d7445676SArnd Bergmann #define INTEGRATOR_SC_ID_OFFSET 0x00 169*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_OFFSET 0x04 170*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRLS_OFFSET 0x08 171*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C 172*d7445676SArnd Bergmann #define INTEGRATOR_SC_DEC_OFFSET 0x10 173*d7445676SArnd Bergmann #define INTEGRATOR_SC_ARB_OFFSET 0x14 174*d7445676SArnd Bergmann #define INTEGRATOR_SC_LOCK_OFFSET 0x1C 175*d7445676SArnd Bergmann 176*d7445676SArnd Bergmann #define INTEGRATOR_SC_BASE 0x11000000 177*d7445676SArnd Bergmann #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) 178*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) 179*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) 180*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) 181*d7445676SArnd Bergmann #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) 182*d7445676SArnd Bergmann #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) 183*d7445676SArnd Bergmann #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) 184*d7445676SArnd Bergmann #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) 185*d7445676SArnd Bergmann 186*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 187*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 188*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 189*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C 190*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C 191*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF 192*d7445676SArnd Bergmann 193*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 194*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 195*d7445676SArnd Bergmann #define INTEGRATOR_SC_OSC_PCI_MASK 0x100 196*d7445676SArnd Bergmann 197*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) 198*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) 199*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) 200*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) 201*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) 202*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) 203*d7445676SArnd Bergmann #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) 204*d7445676SArnd Bergmann 205*d7445676SArnd Bergmann /* 206*d7445676SArnd Bergmann * External Bus Interface 207*d7445676SArnd Bergmann */ 208*d7445676SArnd Bergmann #define INTEGRATOR_EBI_BASE 0x12000000 209*d7445676SArnd Bergmann 210*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR0_OFFSET 0x00 211*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR1_OFFSET 0x04 212*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR2_OFFSET 0x08 213*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C 214*d7445676SArnd Bergmann #define INTEGRATOR_EBI_LOCK_OFFSET 0x20 215*d7445676SArnd Bergmann 216*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) 217*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 218*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) 219*d7445676SArnd Bergmann #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) 220*d7445676SArnd Bergmann #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 221*d7445676SArnd Bergmann 222*d7445676SArnd Bergmann #define INTEGRATOR_EBI_8_BIT 0x00 223*d7445676SArnd Bergmann #define INTEGRATOR_EBI_16_BIT 0x01 224*d7445676SArnd Bergmann #define INTEGRATOR_EBI_32_BIT 0x02 225*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WRITE_ENABLE 0x04 226*d7445676SArnd Bergmann #define INTEGRATOR_EBI_SYNC 0x08 227*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_2 0x00 228*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_3 0x10 229*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_4 0x20 230*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_5 0x30 231*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_6 0x40 232*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_7 0x50 233*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_8 0x60 234*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_9 0x70 235*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_10 0x80 236*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_11 0x90 237*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_12 0xA0 238*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_13 0xB0 239*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_14 0xC0 240*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_15 0xD0 241*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_16 0xE0 242*d7445676SArnd Bergmann #define INTEGRATOR_EBI_WS_17 0xF0 243*d7445676SArnd Bergmann 244*d7445676SArnd Bergmann 245*d7445676SArnd Bergmann #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ 246*d7445676SArnd Bergmann #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ 247*d7445676SArnd Bergmann #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ 248*d7445676SArnd Bergmann #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ 249*d7445676SArnd Bergmann #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ 250*d7445676SArnd Bergmann #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ 251*d7445676SArnd Bergmann #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ 252*d7445676SArnd Bergmann 253*d7445676SArnd Bergmann /* 254*d7445676SArnd Bergmann * LED's & Switches 255*d7445676SArnd Bergmann */ 256*d7445676SArnd Bergmann #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 257*d7445676SArnd Bergmann #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 258*d7445676SArnd Bergmann #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 259*d7445676SArnd Bergmann 260*d7445676SArnd Bergmann #define INTEGRATOR_DBG_BASE 0x1A000000 261*d7445676SArnd Bergmann #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) 262*d7445676SArnd Bergmann #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) 263*d7445676SArnd Bergmann #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) 264*d7445676SArnd Bergmann 265*d7445676SArnd Bergmann #define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ 266*d7445676SArnd Bergmann 267*d7445676SArnd Bergmann #define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ 268*d7445676SArnd Bergmann #define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ 269*d7445676SArnd Bergmann #define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ 270*d7445676SArnd Bergmann #define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ 271*d7445676SArnd Bergmann #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ 272*d7445676SArnd Bergmann #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ 273*d7445676SArnd Bergmann 274*d7445676SArnd Bergmann /* PS2 Keyboard interface */ 275*d7445676SArnd Bergmann #define KMI0_BASE INTEGRATOR_KBD_BASE 276*d7445676SArnd Bergmann 277*d7445676SArnd Bergmann /* PS2 Mouse interface */ 278*d7445676SArnd Bergmann #define KMI1_BASE INTEGRATOR_MOUSE_BASE 279*d7445676SArnd Bergmann 280*d7445676SArnd Bergmann /* 281*d7445676SArnd Bergmann * Integrator Interrupt Controllers 282*d7445676SArnd Bergmann * 283*d7445676SArnd Bergmann * 284*d7445676SArnd Bergmann * Offsets from interrupt controller base 285*d7445676SArnd Bergmann * 286*d7445676SArnd Bergmann * System Controller interrupt controller base is 287*d7445676SArnd Bergmann * 288*d7445676SArnd Bergmann * INTEGRATOR_IC_BASE + (header_number << 6) 289*d7445676SArnd Bergmann * 290*d7445676SArnd Bergmann * Core Module interrupt controller base is 291*d7445676SArnd Bergmann * 292*d7445676SArnd Bergmann * INTEGRATOR_HDR_IC 293*d7445676SArnd Bergmann */ 294*d7445676SArnd Bergmann #define IRQ_STATUS 0 295*d7445676SArnd Bergmann #define IRQ_RAW_STATUS 0x04 296*d7445676SArnd Bergmann #define IRQ_ENABLE 0x08 297*d7445676SArnd Bergmann #define IRQ_ENABLE_SET 0x08 298*d7445676SArnd Bergmann #define IRQ_ENABLE_CLEAR 0x0C 299*d7445676SArnd Bergmann 300*d7445676SArnd Bergmann #define INT_SOFT_SET 0x10 301*d7445676SArnd Bergmann #define INT_SOFT_CLEAR 0x14 302*d7445676SArnd Bergmann 303*d7445676SArnd Bergmann #define FIQ_STATUS 0x20 304*d7445676SArnd Bergmann #define FIQ_RAW_STATUS 0x24 305*d7445676SArnd Bergmann #define FIQ_ENABLE 0x28 306*d7445676SArnd Bergmann #define FIQ_ENABLE_SET 0x28 307*d7445676SArnd Bergmann #define FIQ_ENABLE_CLEAR 0x2C 308*d7445676SArnd Bergmann 309*d7445676SArnd Bergmann 310*d7445676SArnd Bergmann /* 311*d7445676SArnd Bergmann * LED's 312*d7445676SArnd Bergmann */ 313*d7445676SArnd Bergmann #define GREEN_LED 0x01 314*d7445676SArnd Bergmann #define YELLOW_LED 0x02 315*d7445676SArnd Bergmann #define RED_LED 0x04 316*d7445676SArnd Bergmann #define GREEN_LED_2 0x08 317*d7445676SArnd Bergmann #define ALL_LEDS 0x0F 318*d7445676SArnd Bergmann 319*d7445676SArnd Bergmann #define LED_BANK INTEGRATOR_DBG_LEDS 320*d7445676SArnd Bergmann 321*d7445676SArnd Bergmann /* 322*d7445676SArnd Bergmann * Timer definitions 323*d7445676SArnd Bergmann * 324*d7445676SArnd Bergmann * Only use timer 1 & 2 325*d7445676SArnd Bergmann * (both run at 24MHz and will need the clock divider set to 16). 326*d7445676SArnd Bergmann * 327*d7445676SArnd Bergmann * Timer 0 runs at bus frequency 328*d7445676SArnd Bergmann */ 329*d7445676SArnd Bergmann #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE 330*d7445676SArnd Bergmann #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) 331*d7445676SArnd Bergmann #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) 332*d7445676SArnd Bergmann 333*d7445676SArnd Bergmann #define INTEGRATOR_CSR_BASE 0x10000000 334*d7445676SArnd Bergmann #define INTEGRATOR_CSR_SIZE 0x10000000 335*d7445676SArnd Bergmann 336*d7445676SArnd Bergmann #endif /* INTEGRATOR_HARDWARE_H */ 337