18 #define AGC_MSG_STATE (AGC_MSG_BASE + 0)
24 #define AGC_INIT_MSG_VALUE 0xBABEFACE
42 	{ 0xB9A1, 0x00010303 },
43 	{ 0xB9A2, 0x13000000 },
44 	{ 0xB9A3, 0x00460020 },
45 	{ 0xB9A4, 0x10000000 },
46 	{ 0xB9A5, 0x040A1707 },
47 	{ 0xB9A6, 0x00010000 },
48 	{ 0xB9A7, 0x0E000904 },
49 	{ 0xB9A8, 0x10000000 },
50 	{ 0xB9A9, 0x01165000 },
51 	{ 0xB9AA, 0x000E0002 },
52 	{ 0xB9AB, 0x03884141 },
53 	{ 0xB9AC, 0x10000840 },
54 	{ 0xB9AD, 0x572A5000 },
55 	{ 0xB9AE, 0x00000003 },
56 	{ 0xB9AF, 0x00000000 },
57 	{ 0xB9B0, 0x10000000 },
58 	{ 0xB828, 0x6C204010 },
59 	{ 0xB829, 0x6C204011 },
60 	{ 0xB82A, 0x6C204012 },
61 	{ 0xB82B, 0x6C204013 },
62 	{ 0xB82C, 0x6C204014 },
63 	{ 0xB90F, 0x00000004 },
64 	{ 0xB910, 0x00000002 },
65 	{ 0xB911, 0x00000002 },
66 	{ 0xB912, 0x00000002 },
67 	{ 0xB913, 0x00000002 },
68 	{ 0xB92F, 0x00000004 },
69 	{ 0xB930, 0x00000005 },
70 	{ 0xB931, 0x00000005 },
71 	{ 0xB932, 0x00000005 },
72 	{ 0xB933, 0x00000005 },
73 	{ 0xB96F, 0x00000001 },
74 	{ 0xB970, 0x00000003 },
75 	{ 0xB94F, 0x00000004 },
76 	{ 0xB950, 0x0000000B },
77 	{ 0xB951, 0x0000000B },
78 	{ 0xB952, 0x0000000B },
79 	{ 0xB953, 0x0000000B },
80 	{ 0xB907, 0x00000019 },
81 	{ 0xB927, 0x00000019 },
82 	{ 0xB947, 0x00000019 },
83 	{ 0xB967, 0x00000019 },
84 	{ 0xB987, 0x00000019 },
85 	{ 0xB906, 0x00220001 },
86 	{ 0xB926, 0x00220001 },
87 	{ 0xB946, 0x00220001 },
88 	{ 0xB966, 0x00220001 },
89 	{ 0xB986, 0x00300000 },
90 	{ 0xAC40, 0x0340FF41 },
91 	{ 0xAC41, 0x03BEFED0 },
92 	{ 0xAC42, 0x00331FED },
93 	{ 0xAC43, 0x021FFDD3 },
94 	{ 0xAC44, 0x5555AAAA },
95 	{ 0xAC45, 0x5555AAAA },
96 	{ 0xB9BA, 0x00000008 },
109 	u32 ret = 0;  in _get_mvolts()
129 	for (i = 0; i < ARRAY_SIZE(a5xx_sequence_regs); i++)  in a530_lm_setup()
134 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007);  in a530_lm_setup()
135 	gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01);  in a530_lm_setup()
136 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01);  in a530_lm_setup()
138 	/* Until we get clock scaling 0 is always the active power level */  in a530_lm_setup()
139 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);  in a530_lm_setup()
144 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);  in a530_lm_setup()
146 	gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);  in a530_lm_setup()
147 	gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1);  in a530_lm_setup()
150 	gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);  in a530_lm_setup()
151 	gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1);  in a530_lm_setup()
157 	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);  in a530_lm_setup()
173 #define LEVEL_CONFIG ~(0x303)
187 	/* Until we get clock scaling 0 is always the active power level */  in a540_lm_setup()
188 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);  in a540_lm_setup()
191 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);  in a540_lm_setup()
193 	gpu_write(gpu, AGC_MSG_STATE, 0x80000001);  in a540_lm_setup()
196 	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);  in a540_lm_setup()
213 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F);  in a5xx_pc_init()
214 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0);  in a5xx_pc_init()
215 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080);  in a5xx_pc_init()
216 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040);  in a5xx_pc_init()
224 	struct msm_ringbuffer *ring = gpu->rb[0];  in a5xx_gpmu_init()
227 		return 0;  in a5xx_gpmu_init()
231 	OUT_RING(ring, 0);  in a5xx_gpmu_init()
252 		gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);  in a5xx_gpmu_init()
255 	gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);  in a5xx_gpmu_init()
261 	if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF,  in a5xx_gpmu_init()
262 		0xBABEFACE))  in a5xx_gpmu_init()
274 	return 0;  in a5xx_gpmu_init()
286 	gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);  in a5xx_lm_enable()
287 	gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);  in a5xx_lm_enable()
288 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);  in a5xx_lm_enable()
289 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000);  in a5xx_lm_enable()
290 	gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000);  in a5xx_lm_enable()
292 	gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011);  in a5xx_lm_enable()
302 		return 0;  in a5xx_power_init()
321 	return 0;  in a5xx_power_init()
329 	uint32_t dwords = 0, offset = 0, bosize;  in a5xx_gpmu_ucode_init()
348 		(data[0] < 2) || (data[0] >=  in a5xx_gpmu_ucode_init()
357 	cmds_size = data[0] - data[2] - 2;  in a5xx_gpmu_ucode_init()
373 	while (cmds_size > 0) {  in a5xx_gpmu_ucode_init()
381 		for (i = 0; i < _size; i++)  in a5xx_gpmu_ucode_init()