147b65a4aSSean WangMediaTek g3dsys controller
247b65a4aSSean Wang============================
347b65a4aSSean Wang
447b65a4aSSean WangThe MediaTek g3dsys controller provides various clocks and reset controller to
547b65a4aSSean Wangthe GPU.
647b65a4aSSean Wang
747b65a4aSSean WangRequired Properties:
847b65a4aSSean Wang
947b65a4aSSean Wang- compatible: Should be:
1047b65a4aSSean Wang	- "mediatek,mt2701-g3dsys", "syscon":
1147b65a4aSSean Wang		for MT2701 SoC
1247b65a4aSSean Wang	- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
1347b65a4aSSean Wang		for MT7623 SoC
1447b65a4aSSean Wang- #clock-cells: Must be 1
1547b65a4aSSean Wang- #reset-cells: Must be 1
1647b65a4aSSean Wang
1747b65a4aSSean WangThe g3dsys controller uses the common clk binding from
1847b65a4aSSean WangDocumentation/devicetree/bindings/clock/clock-bindings.txt
1947b65a4aSSean WangThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
2047b65a4aSSean Wang
2147b65a4aSSean WangExample:
2247b65a4aSSean Wang
2347b65a4aSSean Wangg3dsys: clock-controller@13000000 {
2447b65a4aSSean Wang	compatible = "mediatek,mt7623-g3dsys",
2547b65a4aSSean Wang		     "mediatek,mt2701-g3dsys",
2647b65a4aSSean Wang		     "syscon";
2747b65a4aSSean Wang	reg = <0 0x13000000 0 0x200>;
2847b65a4aSSean Wang	#clock-cells = <1>;
2947b65a4aSSean Wang	#reset-cells = <1>;
3047b65a4aSSean Wang};
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