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/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/openbmc/u-boot/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
46 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
47 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
48 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
49 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
54 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
55 UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
56 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
[all …]
/openbmc/linux/drivers/media/usb/stk1160/
H A Dstk1160-reg.h14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-draco.dts45 reg = <0x4b000000 1000000>;
53 pinctrl-0 = <&gpio_mux_pins>;
57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */
58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */
59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */
60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */
61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */
67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/
68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-ln-shrd-v6.h9 #define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10 #define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11 #define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
[all …]
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_raddu_w_qb.c9 rs = 0x12345678; in main()
10 result = 0x114; in main()
13 ("raddu.w.qb %0, %1\n\t" in main()
19 return 0; in main()
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dfuse.h12 u32 reserved0[64]; /* 0x00 - 0xFC: */
13 u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
14 u32 reserved1[3]; /* 0x104 - 0x10c: */
15 u32 sku_info; /* 0x110 */
16 u32 reserved2[13]; /* 0x114 - 0x144: */
17 u32 fa; /* 0x148: FUSE_FA */
18 u32 reserved3[21]; /* 0x14C - 0x19C: */
19 u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pdc.h10 u32 rpr; /* 0x100 Receive Pointer Register */
11 u32 rcr; /* 0x104 Receive Counter Register */
12 u32 tpr; /* 0x108 Transmit Pointer Register */
13 u32 tcr; /* 0x10C Transmit Counter Register */
14 u32 pnpr; /* 0x110 Receive Next Pointer Register */
15 u32 pncr; /* 0x114 Receive Next Counter Register */
16 u32 tnpr; /* 0x118 Transmit Next Pointer Register */
17 u32 tncr; /* 0x11C Transmit Next Counter Register */
18 u32 ptcr; /* 0x120 Transfer Control Register */
19 u32 ptsr; /* 0x124 Transfer Status Register */
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnxp,lpc3220-clk.txt18 ranges = <0x0 0x040004000 0x00001000>;
22 clk: clock-controller@0 {
24 reg = <0x00 0x114>;
/openbmc/linux/drivers/mmc/host/
H A Dsdhci_f_sdh30.h11 #define F_SDH30_AHB_CONFIG 0x100
18 #define F_SDH30_AHB_INCR_4 BIT(0)
20 #define F_SDH30_TUNING_SETTING 0x108
23 #define F_SDH30_IO_CONTROL2 0x114
27 #define F_SDH30_ESD_CONTROL 0x124
32 #define F_SDH30_TEST 0x158
/openbmc/u-boot/arch/arm/mach-versal/include/mach/
H A Dhardware.h6 #define VERSAL_CRL_APB_BASEADDR 0xFF5E0000
17 u32 iou_switch_ctrl; /* 0x114 */
19 u32 timestamp_ref_ctrl; /* 0x14c */
23 u32 rst_timestamp; /* 0x348 */
28 #define VERSAL_IOU_SCNTR_SECURE 0xFF140000
33 u32 counter_control_register; /* 0x0 */
35 u32 base_frequency_id_register; /* 0x20 */
40 #define VERSAL_TCM_BASE_ADDR 0xFFE00000
41 #define VERSAL_TCM_SIZE 0x40000
43 #define VERSAL_RPU_BASEADDR 0xFF9A0000
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-minix-neo.c14 { 0x118, KEY_POWER },
16 { 0x146, KEY_UP },
17 { 0x116, KEY_DOWN },
18 { 0x147, KEY_LEFT },
19 { 0x115, KEY_RIGHT },
20 { 0x155, KEY_ENTER },
22 { 0x110, KEY_VOLUMEDOWN },
23 { 0x140, KEY_BACK },
24 { 0x114, KEY_VOLUMEUP },
26 { 0x10d, KEY_HOME },
[all …]
/openbmc/linux/include/linux/
H A Datmel_pdc.h15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Dutil_csr.h10 #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
11 #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
12 #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
14 #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
16 #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
17 #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
18 #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
19 #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
21 #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
22 #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dwm8505fb_regs.h15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dstk1135.h8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun6i.h17 u32 cr; /* 0x00 */
18 u32 ccr; /* 0x04 controller configuration register */
19 u32 dbgcr; /* 0x08 */
20 u32 dbgcr1; /* 0x0c */
21 u32 rmcr[8]; /* 0x10 */
22 u32 mmcr[16]; /* 0x30 */
23 u32 mbagcr[6]; /* 0x70 */
24 u32 maer; /* 0x88 */
25 u8 res0[0x14]; /* 0x8c */
26 u32 mdfscr; /* 0x100 */
[all …]
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr9a06g032-clocks.c28 #define R9A06G032_SYSCTRL_USB 0x00
30 #define R9A06G032_SYSCTRL_DMAMUX 0xA0
36 * @bit: which bit (0 to 31) in the register
45 * This allows encoding an offset up to 0x1FFC (8188) bytes.
88 K_GATE = 0, /* gate which enable/disable */
103 * Root clock uses ID of ~0 (PARENT_ID);
112 * @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7
128 uint32_t source:8; /* source index + 1 (0 == none) */
217 #define R9A06G032_CLKOUT 0
262 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/bcm/
H A Dbrcm,bcm2835-pm.yaml77 reg = <0x7e100000 0x114>,
78 <0x7e00a000 0x24>;

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