1ec48b6c9SMichal Simek /* SPDX-License-Identifier: GPL-2.0+ */ 2ec48b6c9SMichal Simek /* 3ec48b6c9SMichal Simek * Copyright 2016 - 2018 Xilinx, Inc. 4ec48b6c9SMichal Simek */ 5ec48b6c9SMichal Simek 6ec48b6c9SMichal Simek #define VERSAL_CRL_APB_BASEADDR 0xFF5E0000 7ec48b6c9SMichal Simek 8ec48b6c9SMichal Simek #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) 9ec48b6c9SMichal Simek 10ec48b6c9SMichal Simek #define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) 11ec48b6c9SMichal Simek #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 12ec48b6c9SMichal Simek 13ec48b6c9SMichal Simek struct crlapb_regs { 14*4244f2b7SSiva Durga Prasad Paladugu u32 reserved0[67]; 15*4244f2b7SSiva Durga Prasad Paladugu u32 cpu_r5_ctrl; 16*4244f2b7SSiva Durga Prasad Paladugu u32 reserved; 17ec48b6c9SMichal Simek u32 iou_switch_ctrl; /* 0x114 */ 18ec48b6c9SMichal Simek u32 reserved1[13]; 19ec48b6c9SMichal Simek u32 timestamp_ref_ctrl; /* 0x14c */ 20*4244f2b7SSiva Durga Prasad Paladugu u32 reserved3[108]; 21*4244f2b7SSiva Durga Prasad Paladugu u32 rst_cpu_r5; 22*4244f2b7SSiva Durga Prasad Paladugu u32 reserved2[17]; 23ec48b6c9SMichal Simek u32 rst_timestamp; /* 0x348 */ 24ec48b6c9SMichal Simek }; 25ec48b6c9SMichal Simek 26ec48b6c9SMichal Simek #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR) 27ec48b6c9SMichal Simek 28ec48b6c9SMichal Simek #define VERSAL_IOU_SCNTR_SECURE 0xFF140000 29ec48b6c9SMichal Simek 30ec48b6c9SMichal Simek #define IOU_SCNTRS_CONTROL_EN 1 31ec48b6c9SMichal Simek 32ec48b6c9SMichal Simek struct iou_scntrs_regs { 33ec48b6c9SMichal Simek u32 counter_control_register; /* 0x0 */ 34ec48b6c9SMichal Simek u32 reserved0[7]; 35ec48b6c9SMichal Simek u32 base_frequency_id_register; /* 0x20 */ 36ec48b6c9SMichal Simek }; 37ec48b6c9SMichal Simek 38ec48b6c9SMichal Simek #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE) 39*4244f2b7SSiva Durga Prasad Paladugu 40*4244f2b7SSiva Durga Prasad Paladugu #define VERSAL_TCM_BASE_ADDR 0xFFE00000 41*4244f2b7SSiva Durga Prasad Paladugu #define VERSAL_TCM_SIZE 0x40000 42*4244f2b7SSiva Durga Prasad Paladugu 43*4244f2b7SSiva Durga Prasad Paladugu #define VERSAL_RPU_BASEADDR 0xFF9A0000 44*4244f2b7SSiva Durga Prasad Paladugu 45*4244f2b7SSiva Durga Prasad Paladugu struct rpu_regs { 46*4244f2b7SSiva Durga Prasad Paladugu u32 rpu_glbl_ctrl; 47*4244f2b7SSiva Durga Prasad Paladugu u32 reserved0[63]; 48*4244f2b7SSiva Durga Prasad Paladugu u32 rpu0_cfg; /* 0x100 */ 49*4244f2b7SSiva Durga Prasad Paladugu u32 reserved1[63]; 50*4244f2b7SSiva Durga Prasad Paladugu u32 rpu1_cfg; /* 0x200 */ 51*4244f2b7SSiva Durga Prasad Paladugu }; 52*4244f2b7SSiva Durga Prasad Paladugu 53*4244f2b7SSiva Durga Prasad Paladugu #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR) 54