1fd9871f7SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 24ab0620bSOndrej Zary /* 34ab0620bSOndrej Zary * STK1135 registers 44ab0620bSOndrej Zary * 54ab0620bSOndrej Zary * Copyright (c) 2013 Ondrej Zary 64ab0620bSOndrej Zary */ 74ab0620bSOndrej Zary 84ab0620bSOndrej Zary #define STK1135_REG_GCTRL 0x000 /* GPIO control */ 94ab0620bSOndrej Zary #define STK1135_REG_ICTRL 0x004 /* Interrupt control */ 104ab0620bSOndrej Zary #define STK1135_REG_IDATA 0x008 /* Interrupt data */ 114ab0620bSOndrej Zary #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */ 124ab0620bSOndrej Zary #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */ 134ab0620bSOndrej Zary 144ab0620bSOndrej Zary #define STK1135_REG_SENSO 0x018 /* Sensor select options */ 154ab0620bSOndrej Zary #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */ 164ab0620bSOndrej Zary 174ab0620bSOndrej Zary #define STK1135_REG_SCTRL 0x100 /* Sensor control register */ 184ab0620bSOndrej Zary #define STK1135_REG_DCTRL 0x104 /* Decimation control register */ 194ab0620bSOndrej Zary #define STK1135_REG_CISPO 0x110 /* Capture image starting position */ 204ab0620bSOndrej Zary #define STK1135_REG_CIEPO 0x114 /* Capture image ending position */ 214ab0620bSOndrej Zary #define STK1135_REG_TCTRL 0x120 /* Test data control */ 224ab0620bSOndrej Zary 234ab0620bSOndrej Zary #define STK1135_REG_SICTL 0x200 /* Serial interface control register */ 244ab0620bSOndrej Zary #define STK1135_REG_SBUSW 0x204 /* Serial bus write */ 254ab0620bSOndrej Zary #define STK1135_REG_SBUSR 0x208 /* Serial bus read */ 264ab0620bSOndrej Zary #define STK1135_REG_SCSI 0x20c /* Software control serial interface */ 274ab0620bSOndrej Zary #define STK1135_REG_GSBWP 0x210 /* General serial bus write port */ 284ab0620bSOndrej Zary #define STK1135_REG_GSBRP 0x214 /* General serial bus read port */ 294ab0620bSOndrej Zary #define STK1135_REG_ASIC 0x2fc /* Alternate serial interface control */ 304ab0620bSOndrej Zary 314ab0620bSOndrej Zary #define STK1135_REG_TMGEN 0x300 /* Timing generator */ 324ab0620bSOndrej Zary #define STK1135_REG_TCP1 0x350 /* Timing control parameter 1 */ 334ab0620bSOndrej Zary 344ab0620bSOndrej Zary struct stk1135_pkt_header { 354ab0620bSOndrej Zary u8 flags; 364ab0620bSOndrej Zary u8 seq; 374ab0620bSOndrej Zary __le16 gpio; 384ab0620bSOndrej Zary } __packed; 394ab0620bSOndrej Zary 404ab0620bSOndrej Zary #define STK1135_HDR_FRAME_START (1 << 7) 414ab0620bSOndrej Zary #define STK1135_HDR_ODD (1 << 6) 424ab0620bSOndrej Zary #define STK1135_HDR_I2C_VBLANK (1 << 5) 434ab0620bSOndrej Zary 444ab0620bSOndrej Zary #define STK1135_HDR_SEQ_MASK 0x3f 45