1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cf4c3448SCalvin Johnson /* 3cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 4cf4c3448SCalvin Johnson * Copyright 2017 NXP 5cf4c3448SCalvin Johnson */ 6cf4c3448SCalvin Johnson 7cf4c3448SCalvin Johnson #ifndef _UTIL_CSR_H_ 8cf4c3448SCalvin Johnson #define _UTIL_CSR_H_ 9cf4c3448SCalvin Johnson 10cf4c3448SCalvin Johnson #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) 11cf4c3448SCalvin Johnson #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) 12cf4c3448SCalvin Johnson #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) 13cf4c3448SCalvin Johnson 14cf4c3448SCalvin Johnson #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) 15cf4c3448SCalvin Johnson 16cf4c3448SCalvin Johnson #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) 17cf4c3448SCalvin Johnson #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) 18cf4c3448SCalvin Johnson #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) 19cf4c3448SCalvin Johnson #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) 20cf4c3448SCalvin Johnson 21cf4c3448SCalvin Johnson #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) 22cf4c3448SCalvin Johnson #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) 23cf4c3448SCalvin Johnson #define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) 24cf4c3448SCalvin Johnson 25cf4c3448SCalvin Johnson #define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) 26cf4c3448SCalvin Johnson #define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) 27cf4c3448SCalvin Johnson 28cf4c3448SCalvin Johnson #define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) 29cf4c3448SCalvin Johnson #define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) 30cf4c3448SCalvin Johnson #define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) 31cf4c3448SCalvin Johnson #define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) 32cf4c3448SCalvin Johnson #define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) 33cf4c3448SCalvin Johnson #define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) 34cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) 35cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) 36cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) 37cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) 38cf4c3448SCalvin Johnson 39cf4c3448SCalvin Johnson #define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) 40cf4c3448SCalvin Johnson #define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) 41cf4c3448SCalvin Johnson #define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) 42cf4c3448SCalvin Johnson 43cf4c3448SCalvin Johnson #define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) 44cf4c3448SCalvin Johnson #define UTIL_AXI_CTRL (UTIL_CSR_BASE_ADDR + 0x240) 45cf4c3448SCalvin Johnson 46cf4c3448SCalvin Johnson #endif /* _UTIL_CSR_H_ */ 47