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Searched +full:0 +full:x10080000 (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlsi,axm5516-clks.txt18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi18 cpu@0 {
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Dlpc4357.dtsi18 cpu@0 {
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
163 ranges = <0 0x5c000000 0x40000>;
166 reg = <0x100 0x50>;
170 reg = <0x1000 0x1000>;
175 reg = <0x20000 0x20000>;
190 reg = <0x02020000 0x54000>;
193 ranges = <0 0x02020000 0x54000>;
195 smp-sram@0 {
197 reg = <0x0 0x1000>;
202 reg = <0x53000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3188.dtsi17 #size-cells = <0>;
20 cpu0: cpu@0 {
24 reg = <0x0>;
43 reg = <0x1>;
49 reg = <0x2>;
55 reg = <0x3>;
61 reg = <0x10080000 0x8000>;
64 ranges = <0 0x10080000 0x8000>;
66 smp-sram@0 {
68 reg = <0x0 0x50>;
[all …]
H A Drv1108.dtsi28 #size-cells = <0>;
33 reg = <0xf00>;
53 #clock-cells = <0>;
64 reg = <0x102a0000 0x4000>;
65 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
75 reg = <0x10080000 0x2000>;
78 ranges = <0 0x10080000 0x2000>;
83 reg = <0x10210000 0x100>;
91 pinctrl-0 = <&uart2m0_xfer>;
97 reg = <0x10220000 0x100>;
[all …]
H A Drk322x.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
48 reg = <0xf01>;
55 reg = <0xf02>;
62 reg = <0xf03>;
75 reg = <0x110f0000 0x4000>;
76 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 #clock-cells = <0>;
112 reg = <0x10080000 0x9000>;
115 ranges = <0 0x10080000 0x9000>;
[all …]
H A Drk3036.dtsi29 reg = <0x60000000 0x40000000>;
41 #size-cells = <0>;
47 reg = <0xf00>;
60 reg = <0xf01>;
73 reg = <0x20078000 0x4000>;
75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
87 #clock-cells = <0>;
102 reg = <0x20000000 0x1000>;
112 reg = <0x20060000 0x100>;
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6318.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
61 reg = <0x10000008 0x4>;
74 reg = <0x10000010 0x4>;
80 reg = <0x10000068 0xc>;
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dm53xx.c31 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
32 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
33 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
34 DEFINE_CLK(0, "edma", 17, MCF_CLK);
35 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
36 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
37 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
39 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
40 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
42 reg = <0x1>;
53 reg = <0x10080000 0x10000>;
56 ranges = <0 0x10080000 0x10000>;
58 smp-sram@0 {
60 reg = <0x0 0x50>;
66 reg = <0x1010c000 0x19c>;
81 #size-cells = <0>;
[all …]
H A Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
35 reg = <0x1>;
43 reg = <0x2>;
51 reg = <0x3>;
57 cpu0_opp_table: opp-table-0 {
104 reg = <0x10080000 0x8000>;
107 ranges = <0 0x10080000 0x8000>;
109 smp-sram@0 {
[all …]
H A Drk3036.dtsi34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
[all …]
H A Drv1108.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
43 cpu_opp_table: opp-table-0 {
85 #clock-cells = <0>;
90 reg = <0x10080000 0x2000>;
93 ranges = <0 0x10080000 0x2000>;
98 reg = <0x10210000 0x100>;
107 pinctrl-0 = <&uart2m0_xfer>;
113 reg = <0x10220000 0x100>;
122 pinctrl-0 = <&uart1_xfer>;
[all …]
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
15 reg = <0 0x10000000 0 0x400>;
18 loongson,pic-base-vec = <0>;
24 reg = <0 0x100d0100 0 0x78>;
31 reg = <0 0x10080000 0 0x100>;
41 reg = <0 0x10080100 0 0x100>;
51 reg = <0 0x10080200 0 0x100>;
[all …]
/openbmc/qemu/target/ppc/
H A Dcpu-models.h42 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
45 CPU_POWERPC_405D2 = 0x20010000,
46 CPU_POWERPC_405D4 = 0x41810000,
48 /* XXX: missing 0x200108a0 */
49 CPU_POWERPC_405CRa = 0x40110041,
50 CPU_POWERPC_405CRb = 0x401100C5,
51 CPU_POWERPC_405CRc = 0x40110145,
52 CPU_POWERPC_405EP = 0x51210950,
53 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
54 CPU_POWERPC_405GPa = 0x40110000,
[all …]
/openbmc/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/qemu/hw/mips/
H A Dloongson3_virt.c54 #define PM_CNTL_MODE 0x10
65 #define UART_IRQ 0
70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
71 [VIRT_PM] = { 0x10080000, 0x100 },
72 [VIRT_FW_CFG] = { 0x10080100, 0x100 },
73 [VIRT_RTC] = { 0x10081000, 0x1000 },
74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
77 [VIRT_UART] = { 0x1fe001e0, 0x8 },
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
185 cpu_opp: opp-table-0 {
245 #clock-cells = <0>;
250 #clock-cells = <0>;
256 #clock-cells = <0>;
262 #clock-cells = <0>;
268 #clock-cells = <0>;
274 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h31 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
38 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
47 #define MSR_LE (1<<0) /* Little Endian */
62 #define FPSCR_FX 0x80000000 /* FPU exception summary */
63 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
64 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
65 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
66 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
68 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg.h49 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
54 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
61 #define MSR_LE_LG 0 /* Little Endian */
75 #define MSR_SF 0
76 #define MSR_HV 0
77 #define MSR_S 0
85 #define MSR_SPE 0
99 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
104 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
116 #define MSR_TS_N 0 /* Non-transactional */
[all …]