Lines Matching +full:0 +full:x10080000
29 reg = <0x60000000 0x40000000>;
41 #size-cells = <0>;
47 reg = <0xf00>;
60 reg = <0xf01>;
73 reg = <0x20078000 0x4000>;
75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
87 #clock-cells = <0>;
102 reg = <0x20000000 0x1000>;
112 reg = <0x20060000 0x100>;
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
125 reg = <0x20064000 0x100>;
133 pinctrl-0 = <&uart1_xfer>;
138 reg = <0x20068000 0x100>;
146 pinctrl-0 = <&uart2_xfer>;
151 reg = <0x20050000 0x10>;
154 pinctrl-0 = <&pwm0_pin>;
162 reg = <0x20050010 0x10>;
165 pinctrl-0 = <&pwm1_pin>;
173 reg = <0x20050020 0x10>;
176 pinctrl-0 = <&pwm2_pin>;
184 reg = <0x20050030 0x10>;
187 pinctrl-0 = <&pwm3_pin>;
195 reg = <0x10080000 0x2000>;
202 #address-cells = <0>;
204 reg = <0x10139000 0x1000>,
205 <0x1013a000 0x1000>,
206 <0x1013c000 0x2000>,
207 <0x1013e000 0x2000>;
208 interrupts = <GIC_PPI 9 0xf04>;
213 reg = <0x20008000 0x1000>;
219 reg = <0x10180000 0x40000>;
234 reg = <0x101c0000 0x40000>;
251 fifo-depth = <0x100>;
253 reg = <0x1021c000 0x4000>;
264 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
269 reg = <0x10214000 0x4000>;
274 fifo-depth = <0x100>;
288 reg = <0x2007c000 0x100>;
301 reg = <0x20080000 0x100>;
314 reg = <0x20084000 0x100>;
366 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
367 <0 17 RK_FUNC_1 &pcfg_pull_none>;
371 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
375 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
397 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
403 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
409 rockchip,pins = <0 1 2 &pcfg_pull_none>;
415 rockchip,pins = <0 27 1 &pcfg_pull_none>;
421 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
422 <0 3 RK_FUNC_1 &pcfg_pull_none>;
429 reg = <0x20056000 0x1000>;
432 #size-cells = <0>;
436 pinctrl-0 = <&i2c1_xfer>;