31 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
32 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
33 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
34 DEFINE_CLK(0, "edma", 17, MCF_CLK);
35 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
36 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
37 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
39 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
40 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
41 DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
42 DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
43 DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
44 DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
45 DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
46 DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
48 DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
49 DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
50 DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
51 DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
52 DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
53 DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
54 DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
55 DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
56 DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
57 DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
58 DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
59 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
60 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
61 DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
62 DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
63 DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
65 DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
66 DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
67 DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
71 	CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
72 	CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
74 	CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
76 	CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
77 	CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
78 	CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
79 	CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
82 	CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
86 	CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
90 	CLKDEV_INIT("mcfpwm.0", NULL, &__clk_0_36),
91 	CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
92 	CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_38),
93 	CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
94 	CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
95 	CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
96 	CLKDEV_INIT("mcflcd.0", NULL, &__clk_0_43),
97 	CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
98 	CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
99 	CLKDEV_INIT("sdram.0", NULL, &__clk_0_46),
100 	CLKDEV_INIT("ssi.0", NULL, &__clk_0_47),
101 	CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
102 	CLKDEV_INIT("mdha.0", NULL, &__clk_1_32),
103 	CLKDEV_INIT("skha.0", NULL, &__clk_1_33),
104 	CLKDEV_INIT("rng.0", NULL, &__clk_1_34),
109 	&__clk_0_18,	/* intc.0 */
111 	&__clk_0_21,	/* iack.0 */
112 	&__clk_0_24,	/* mcfuart.0 */
115 	&__clk_0_28,	/* mcftmr.0 */
117 	&__clk_0_32,	/* mcfpit.0 */
119 	&__clk_0_37,	/* mcfeport.0 */
120 	&__clk_0_40,	/* sys.0 */
121 	&__clk_0_41,	/* gpio.0 */
122 	&__clk_0_46,	/* sdram.0 */
123 	&__clk_0_48,	/* pll.0 */
127 	&__clk_0_8,	/* mcfcan.0 */
128 	&__clk_0_12,	/* fec.0 */
130 	&__clk_0_22,	/* imx1-i2c.0 */
131 	&__clk_0_23,	/* mcfqspi.0 */
136 	&__clk_0_36,	/* mcfpwm.0 */
137 	&__clk_0_38,	/* mcfwdt.0 */
138 	&__clk_0_42,	/* mcfrtc.0 */
139 	&__clk_0_43,	/* mcflcd.0 */
140 	&__clk_0_44,	/* mcfusb-otg.0 */
141 	&__clk_0_45,	/* mcfusb-host.0 */
142 	&__clk_0_47,	/* ssi.0 */
143 	&__clk_1_32,	/* mdha.0 */
144 	&__clk_1_33,	/* skha.0 */
145 	&__clk_1_34,	/* rng.0 */
154 	for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)  in m53xx_clk_init()
157 	for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)  in m53xx_clk_init()
169 	writew(0x01f0, MCFGPIO_PAR_QSPI);  in m53xx_qspi_init()
181 	r |= 0x0f;  in m53xx_i2c_init()
191 	writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);  in m53xx_uarts_init()
217 	memcpy(commandp, (char *) 0x4000, 4);  in config_BSP()
218 	if(strncmp(commandp, "kcl ", 4) == 0){  in config_BSP()
219 		memcpy(commandp, (char *) 0x4004, size);  in config_BSP()
220 		commandp[size-1] = 0;  in config_BSP()
222 		memset(commandp, 0, size);  in config_BSP()
261 #define MIN_LPD		(1 << 0)    /* Divider (not encoded) */
278 #define EXT_SRAM_ADDRESS	(0xC0000000)
279 #define FLASH_ADDRESS		(0x00000000)
280 #define SDRAM_ADDRESS		(0x40000000)
282 #define NAND_FLASH_ADDRESS	(0xD0000000)
296 	clock_pll(0, 0);  in sysinit()
308 	writew(0, MCF_WTM_WCR);  in wtm_init()
311 #define MCF_SCM_BCR_GBW		(0x00000100)
312 #define MCF_SCM_BCR_GBR		(0x00000200)
317 	writel(0x77777777, MCF_SCM_MPR);  in scm_init()
321 	writel(0, MCF_SCM_PACRA);  in scm_init()
322 	writel(0, MCF_SCM_PACRB);  in scm_init()
323 	writel(0, MCF_SCM_PACRC);  in scm_init()
324 	writel(0, MCF_SCM_PACRD);  in scm_init()
325 	writel(0, MCF_SCM_PACRE);  in scm_init()
326 	writel(0, MCF_SCM_PACRF);  in scm_init()
335 	writeb(0x3E, MCFGPIO_PAR_CS);  in fbcs_init()
338 	writel(0x10080000, MCF_FBCS1_CSAR);  in fbcs_init()
340 	writel(0x002A3780, MCF_FBCS1_CSCR);  in fbcs_init()
344 	writew(0xffff, 0x10080000);  in fbcs_init()
414 		MCF_SDRAMC_SDMR_AD(0x0) |  in sdramc_init()
422 		MCF_SDRAMC_SDMR_AD(0x163) |  in sdramc_init()
441 		MCF_SDRAMC_SDMR_AD(0x063) |  in sdramc_init()
450 	writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),  in sdramc_init()
465 	writeb(0x00, MCFGPIO_PAR_TIMER);  in gpio_init()
466 	writeb(0x08, MCFGPIO_PDDR_TIMER);  in gpio_init()
467 	writeb(0x00, MCFGPIO_PCLRR_TIMER);  in gpio_init()
477 	if (fsys == 0) {  in clock_pll()
539 	for (i = 0; i < 0x200; i++)  in clock_pll()
557 	temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);  in clock_limp()
589 		divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);  in get_sys_clock()