Lines Matching +full:0 +full:x10080000

28 		#size-cells = <0>;
33 			reg = <0xf00>;
53 		#clock-cells = <0>;
64 			reg = <0x102a0000 0x4000>;
65 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
75 		reg = <0x10080000 0x2000>;
78 		ranges = <0 0x10080000 0x2000>;
83 		reg = <0x10210000 0x100>;
91 		pinctrl-0 = <&uart2m0_xfer>;
97 		reg = <0x10220000 0x100>;
105 		pinctrl-0 = <&uart1_xfer>;
111 		reg = <0x10230000 0x100>;
119 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
125 		reg = <0x10300000 0x1000>;
131 			reg = <0x100 0x0c>;
134 			#clock-cells = <0>;
142 				#phy-cells = <0>;
149 				#phy-cells = <0>;
157 		reg = <0x1038c000 0x100>;
168 		reg = <0x20060000 0x1000>;
173 		reg = <0x202a0000 0x1000>;
178 		reg = <0x20200000 0x1000>;
190 		fifo-depth = <0x100>;
192 		reg = <0x30110000 0x4000>;
202 		fifo-depth = <0x100>;
204 		reg = <0x30120000 0x4000>;
214 		fifo-depth = <0x100>;
216 		reg = <0x30130000 0x4000>;
222 		reg = <0x30140000 0x20000>;
229 		reg = <0x30160000 0x20000>;
237 		reg = <0x30180000 0x40000>;
253 		reg = <0x301c0000 0x200>;
255 		#size-cells = <0>;
259 		pinctrl-0 = <&sfc_pins>;
266 		reg = <0x30200000 0x10000>;
279 		pinctrl-0 = <&rmii_pins>;
289 		#address-cells = <0>;
291 		reg = <0x32011000 0x1000>,
292 		      <0x32012000 0x1000>,
293 		      <0x32014000 0x2000>,
294 		      <0x32016000 0x2000>;
308 			reg = <0x20030000 0x100>;
321 			reg = <0x10310000 0x100>;
334 			reg = <0x10320000 0x100>;
347 			reg = <0x10330000 0x100>;
429 				rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
430 						<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
434 				rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
435 						<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
453 				rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
454 						<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
508 				rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;