1*724ba675SRob Herring/* 2*724ba675SRob Herring * NXP LPC4350 and LPC4330 SoC 3*724ba675SRob Herring * 4*724ba675SRob Herring * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com> 5*724ba675SRob Herring * 6*724ba675SRob Herring * This code is released using a dual license strategy: BSD/GPL 7*724ba675SRob Herring * You can choose the licence that better fits your requirements. 8*724ba675SRob Herring * 9*724ba675SRob Herring * Released under the terms of 3-clause BSD License 10*724ba675SRob Herring * Released under the terms of GNU General Public License Version 2.0 11*724ba675SRob Herring * 12*724ba675SRob Herring */ 13*724ba675SRob Herring 14*724ba675SRob Herring/ { 15*724ba675SRob Herring compatible = "nxp,lpc4350", "nxp,lpc4330"; 16*724ba675SRob Herring 17*724ba675SRob Herring cpus { 18*724ba675SRob Herring cpu@0 { 19*724ba675SRob Herring compatible = "arm,cortex-m4"; 20*724ba675SRob Herring }; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring soc { 24*724ba675SRob Herring sram0: sram@10000000 { 25*724ba675SRob Herring compatible = "mmio-sram"; 26*724ba675SRob Herring reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring sram1: sram@10080000 { 30*724ba675SRob Herring compatible = "mmio-sram"; 31*724ba675SRob Herring reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ 32*724ba675SRob Herring }; 33*724ba675SRob Herring 34*724ba675SRob Herring sram2: sram@20000000 { 35*724ba675SRob Herring compatible = "mmio-sram"; 36*724ba675SRob Herring reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 37*724ba675SRob Herring }; 38*724ba675SRob Herring }; 39*724ba675SRob Herring}; 40