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/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dsmi.h15 /* Offset 0x00: SMI Command Register */
16 #define MV88E6XXX_SMI_CMD 0x00
17 #define MV88E6XXX_SMI_CMD_BUSY 0x8000
18 #define MV88E6XXX_SMI_CMD_MODE_MASK 0x1000
19 #define MV88E6XXX_SMI_CMD_MODE_45 0x0000
20 #define MV88E6XXX_SMI_CMD_MODE_22 0x1000
21 #define MV88E6XXX_SMI_CMD_OP_MASK 0x0c00
22 #define MV88E6XXX_SMI_CMD_OP_22_WRITE 0x0400
23 #define MV88E6XXX_SMI_CMD_OP_22_READ 0x0800
24 #define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR 0x0000
[all …]
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Dgic.h6 #define GIC_DIST_OFFSET 0x1000
7 #define GIC_CPU_OFFSET_A9 0x0100
8 #define GIC_CPU_OFFSET_A15 0x2000
11 #define GICD_CTLR 0x0000
12 #define GICD_TYPER 0x0004
13 #define GICD_IIDR 0x0008
14 #define GICD_STATUSR 0x0010
15 #define GICD_SETSPI_NSR 0x0040
16 #define GICD_CLRSPI_NSR 0x0048
17 #define GICD_SETSPI_SR 0x0050
[all …]
/openbmc/linux/arch/x86/math-emu/
H A Dcontrol_w.h20 #define CW_RC _Const_(0x0C00) /* rounding control */
21 #define CW_PC _Const_(0x0300) /* precision control */
23 #define CW_Precision Const_(0x0020) /* loss of precision mask */
24 #define CW_Underflow Const_(0x0010) /* underflow mask */
25 #define CW_Overflow Const_(0x0008) /* overflow mask */
26 #define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */
27 #define CW_Denormal Const_(0x0002) /* denormalized operand mask */
28 #define CW_Invalid Const_(0x0001) /* invalid operation mask */
30 #define CW_Exceptions _Const_(0x003f) /* all masks */
32 #define RC_RND _Const_(0x0000)
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
H A Dbrcmu_wifi.h18 #define CH_UPPER_SB 0x01
19 #define CH_LOWER_SB 0x02
20 #define CH_EWA_VALID 0x04
32 #define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
42 #define WL_CHANSPEC_CHAN_MASK 0x00ff
43 #define WL_CHANSPEC_CHAN_SHIFT 0
45 #define WL_CHANSPEC_CTL_SB_MASK 0x0300
47 #define WL_CHANSPEC_CTL_SB_LOWER 0x0100
48 #define WL_CHANSPEC_CTL_SB_UPPER 0x0200
49 #define WL_CHANSPEC_CTL_SB_NONE 0x0300
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dgamecube-head.S28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
42 li 8, 0
43 mtspr 0x210, 8 /* IBAT0U */
44 mtspr 0x212, 8 /* IBAT1U */
45 mtspr 0x214, 8 /* IBAT2U */
46 mtspr 0x216, 8 /* IBAT3U */
47 mtspr 0x218, 8 /* DBAT0U */
48 mtspr 0x21a, 8 /* DBAT1U */
49 mtspr 0x21c, 8 /* DBAT2U */
50 mtspr 0x21e, 8 /* DBAT3U */
[all …]
H A Dwii-head.S29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dtfa9879.h12 #define TFA9879_DEVICE_CONTROL 0x00
13 #define TFA9879_SERIAL_INTERFACE_1 0x01
14 #define TFA9879_PCM_IOM2_FORMAT_1 0x02
15 #define TFA9879_SERIAL_INTERFACE_2 0x03
16 #define TFA9879_PCM_IOM2_FORMAT_2 0x04
17 #define TFA9879_EQUALIZER_A1 0x05
18 #define TFA9879_EQUALIZER_A2 0x06
19 #define TFA9879_EQUALIZER_B1 0x07
20 #define TFA9879_EQUALIZER_B2 0x08
21 #define TFA9879_EQUALIZER_C1 0x09
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5235.h18 #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
19 #define SCM_IPSBAR_V (0x00000001)
22 #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
23 #define SCM_RAMBAR_BDE (0x00000200)
26 #define SCM_CRSR_EXT (0x80)
29 #define SCM_CWCR_CWE (0x80)
30 #define SCM_CWCR_CWRI (0x40)
31 #define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
32 #define SCM_CWCR_CWTA (0x04)
33 #define SCM_CWCR_CWTAVAL (0x02)
[all …]
/openbmc/linux/net/nfc/
H A Ddigital_technology.c11 #define DIGITAL_CMD_SENS_REQ 0x26
12 #define DIGITAL_CMD_ALL_REQ 0x52
13 #define DIGITAL_CMD_SEL_REQ_CL1 0x93
14 #define DIGITAL_CMD_SEL_REQ_CL2 0x95
15 #define DIGITAL_CMD_SEL_REQ_CL3 0x97
17 #define DIGITAL_SDD_REQ_SEL_PAR 0x20
19 #define DIGITAL_SDD_RES_CT 0x88
23 #define DIGITAL_SEL_RES_NFCID1_COMPLETE(sel_res) (!((sel_res) & 0x04))
24 #define DIGITAL_SEL_RES_IS_T2T(sel_res) (!((sel_res) & 0x60))
25 #define DIGITAL_SEL_RES_IS_T4T(sel_res) ((sel_res) & 0x20)
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Domap.h15 #define SMX_APE_BASE 0x68000000
18 #define OMAP34XX_GPMC_BASE 0x6E000000
21 #define OMAP34XX_SMS_BASE 0x6C000000
24 #define OMAP34XX_SDRC_BASE 0x6D000000
29 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
30 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
31 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
32 #define OMAP34XX_L4_PER 0x49000000
36 #define OMAP34XX_DMA4_BASE 0x48056000
39 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_sbq_cmd.h14 ice_sbq_opc_neigh_dev_req = 0x0C00,
15 ice_sbq_opc_neigh_dev_ev = 0x0C01
50 rmn_0 = 0x02,
51 rmn_1 = 0x03,
52 rmn_2 = 0x04,
53 cgu = 0x06
57 ice_sbq_msg_rd = 0x00,
58 ice_sbq_msg_wr = 0x01
61 #define ICE_SBQ_MSG_FLAGS 0x40
62 #define ICE_SBQ_MSG_SBE_FBE 0x0F
/openbmc/linux/drivers/media/dvb-frontends/
H A Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/openbmc/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.h20 } while (0)
22 __CSKY_INSN_FUNCS(br16, 0xfc00, 0x0400)
23 __CSKY_INSN_FUNCS(bt16, 0xfc00, 0x0800)
24 __CSKY_INSN_FUNCS(bf16, 0xfc00, 0x0c00)
25 __CSKY_INSN_FUNCS(jmp16, 0xffc3, 0x7800)
26 __CSKY_INSN_FUNCS(jsr16, 0xffc3, 0x7801)
27 __CSKY_INSN_FUNCS(lrw16, 0xfc00, 0x1000)
28 __CSKY_INSN_FUNCS(pop16, 0xffe0, 0x1480)
30 __CSKY_INSN_FUNCS(br32, 0x0000ffff, 0x0000e800)
31 __CSKY_INSN_FUNCS(bt32, 0x0000ffff, 0x0000e860)
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Diim.h11 #define MXC_IIMSTAT 0x0000
12 #define MXC_IIMSTATM 0x0004
13 #define MXC_IIMERR 0x0008
14 #define MXC_IIMEMASK 0x000C
15 #define MXC_IIMFCTL 0x0010
16 #define MXC_IIMUA 0x0014
17 #define MXC_IIMLA 0x0018
18 #define MXC_IIMSDAT 0x001C
19 #define MXC_IIMPREV 0x0020
20 #define MXC_IIMSREV 0x0024
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dcavium-mmc.txt34 reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
36 #size-cells = <0>;
39 mmc-slot@0 {
41 reg = <0>;
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/openbmc/u-boot/arch/arm/dts/
H A Domap34xx-omap36xx-clocks.dtsi12 #clock-cells = <0>;
20 #clock-cells = <0>;
24 reg = <0x0a14>;
28 #clock-cells = <0>;
31 reg = <0x0a14>;
36 #clock-cells = <0>;
39 reg = <0x0a14>;
44 #clock-cells = <0>;
47 reg = <0x0a14>;
48 ti,bit-shift = <0>;
[all …]
/openbmc/u-boot/board/cssi/MCR3000/
H A Dnand.c13 #define BIT_CLE ((unsigned short)0x0800)
14 #define BIT_ALE ((unsigned short)0x0400)
15 #define BIT_NCE ((unsigned short)0x1000)
21 unsigned short pddat = 0; in nand_hwcontrol()
55 setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00); in board_nand_init()
56 clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00); in board_nand_init()
57 clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000); in board_nand_init()
63 return 0; in board_nand_init()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]

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