1*52e6676eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ddd04b98SVaibhav Hiremath /* 3ddd04b98SVaibhav Hiremath * AM33XX PRM instance offset macros 4ddd04b98SVaibhav Hiremath * 53aa36fddSAlexander A. Klimov * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 6ddd04b98SVaibhav Hiremath */ 7ddd04b98SVaibhav Hiremath 8ddd04b98SVaibhav Hiremath #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H 9ddd04b98SVaibhav Hiremath #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H 10ddd04b98SVaibhav Hiremath 11ddd04b98SVaibhav Hiremath #include "prcm-common.h" 12ddd04b98SVaibhav Hiremath #include "prm.h" 13ddd04b98SVaibhav Hiremath 14ddd04b98SVaibhav Hiremath #define AM33XX_PRM_BASE 0x44E00000 15ddd04b98SVaibhav Hiremath 16ddd04b98SVaibhav Hiremath #define AM33XX_PRM_REGADDR(inst, reg) \ 17ddd04b98SVaibhav Hiremath AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) 18ddd04b98SVaibhav Hiremath 19ddd04b98SVaibhav Hiremath 20ddd04b98SVaibhav Hiremath /* PRM instances */ 21ddd04b98SVaibhav Hiremath #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00 22ddd04b98SVaibhav Hiremath #define AM33XX_PRM_PER_MOD 0x0C00 23ddd04b98SVaibhav Hiremath #define AM33XX_PRM_WKUP_MOD 0x0D00 24ddd04b98SVaibhav Hiremath #define AM33XX_PRM_MPU_MOD 0x0E00 25ddd04b98SVaibhav Hiremath #define AM33XX_PRM_DEVICE_MOD 0x0F00 26ddd04b98SVaibhav Hiremath #define AM33XX_PRM_RTC_MOD 0x1000 27ddd04b98SVaibhav Hiremath #define AM33XX_PRM_GFX_MOD 0x1100 28ddd04b98SVaibhav Hiremath #define AM33XX_PRM_CEFUSE_MOD 0x1200 29ddd04b98SVaibhav Hiremath 30ddd04b98SVaibhav Hiremath /* PRM.PER_PRM register offsets */ 31ddd04b98SVaibhav Hiremath #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 32ddd04b98SVaibhav Hiremath #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) 33ddd04b98SVaibhav Hiremath #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c 34ddd04b98SVaibhav Hiremath #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) 35ddd04b98SVaibhav Hiremath 36ddd04b98SVaibhav Hiremath /* PRM.WKUP_PRM register offsets */ 37ddd04b98SVaibhav Hiremath #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 38ddd04b98SVaibhav Hiremath #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) 39ddd04b98SVaibhav Hiremath #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 40ddd04b98SVaibhav Hiremath #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) 41ddd04b98SVaibhav Hiremath 42ddd04b98SVaibhav Hiremath /* PRM.MPU_PRM register offsets */ 43ddd04b98SVaibhav Hiremath #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 44ddd04b98SVaibhav Hiremath #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) 45ddd04b98SVaibhav Hiremath #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 46ddd04b98SVaibhav Hiremath #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) 47ddd04b98SVaibhav Hiremath 48ddd04b98SVaibhav Hiremath /* PRM.DEVICE_PRM register offsets */ 49ddd04b98SVaibhav Hiremath #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 50ddd04b98SVaibhav Hiremath #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) 51ddd04b98SVaibhav Hiremath 52ddd04b98SVaibhav Hiremath /* PRM.RTC_PRM register offsets */ 53ddd04b98SVaibhav Hiremath #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 54ddd04b98SVaibhav Hiremath #define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000) 55ddd04b98SVaibhav Hiremath #define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004 56ddd04b98SVaibhav Hiremath #define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004) 57ddd04b98SVaibhav Hiremath 58ddd04b98SVaibhav Hiremath /* PRM.GFX_PRM register offsets */ 59ddd04b98SVaibhav Hiremath #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 60ddd04b98SVaibhav Hiremath #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) 61ddd04b98SVaibhav Hiremath #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 62ddd04b98SVaibhav Hiremath #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) 63ddd04b98SVaibhav Hiremath 64ddd04b98SVaibhav Hiremath /* PRM.CEFUSE_PRM register offsets */ 65ddd04b98SVaibhav Hiremath #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 66ddd04b98SVaibhav Hiremath #define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000) 67ddd04b98SVaibhav Hiremath #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 68ddd04b98SVaibhav Hiremath #define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) 69ddd04b98SVaibhav Hiremath 701a7cb4d9SVaibhav Bedia #ifndef __ASSEMBLER__ 71ab7b2ffcSTero Kristo int am33xx_prm_init(const struct omap_prcm_init_data *data); 72d9bbe84fSTero Kristo 731a7cb4d9SVaibhav Bedia #endif /* ASSEMBLER */ 74ddd04b98SVaibhav Hiremath #endif 75