1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2da957e11SThomas Gleixner /*---------------------------------------------------------------------------+ 3da957e11SThomas Gleixner | control_w.h | 4da957e11SThomas Gleixner | | 5da957e11SThomas Gleixner | Copyright (C) 1992,1993 | 6da957e11SThomas Gleixner | W. Metzenthen, 22 Parker St, Ormond, Vic 3163, | 7da957e11SThomas Gleixner | Australia. E-mail billm@vaxc.cc.monash.edu.au | 8da957e11SThomas Gleixner | | 9da957e11SThomas Gleixner +---------------------------------------------------------------------------*/ 10da957e11SThomas Gleixner 11da957e11SThomas Gleixner #ifndef _CONTROLW_H_ 12da957e11SThomas Gleixner #define _CONTROLW_H_ 13da957e11SThomas Gleixner 14da957e11SThomas Gleixner #ifdef __ASSEMBLY__ 15da957e11SThomas Gleixner #define _Const_(x) $##x 16da957e11SThomas Gleixner #else 17da957e11SThomas Gleixner #define _Const_(x) x 18da957e11SThomas Gleixner #endif 19da957e11SThomas Gleixner 20da957e11SThomas Gleixner #define CW_RC _Const_(0x0C00) /* rounding control */ 21da957e11SThomas Gleixner #define CW_PC _Const_(0x0300) /* precision control */ 22da957e11SThomas Gleixner 23da957e11SThomas Gleixner #define CW_Precision Const_(0x0020) /* loss of precision mask */ 24da957e11SThomas Gleixner #define CW_Underflow Const_(0x0010) /* underflow mask */ 25da957e11SThomas Gleixner #define CW_Overflow Const_(0x0008) /* overflow mask */ 26da957e11SThomas Gleixner #define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */ 27da957e11SThomas Gleixner #define CW_Denormal Const_(0x0002) /* denormalized operand mask */ 28da957e11SThomas Gleixner #define CW_Invalid Const_(0x0001) /* invalid operation mask */ 29da957e11SThomas Gleixner 30da957e11SThomas Gleixner #define CW_Exceptions _Const_(0x003f) /* all masks */ 31da957e11SThomas Gleixner 32da957e11SThomas Gleixner #define RC_RND _Const_(0x0000) 33da957e11SThomas Gleixner #define RC_DOWN _Const_(0x0400) 34da957e11SThomas Gleixner #define RC_UP _Const_(0x0800) 35da957e11SThomas Gleixner #define RC_CHOP _Const_(0x0C00) 36da957e11SThomas Gleixner 37da957e11SThomas Gleixner /* p 15-5: Precision control bits affect only the following: 38da957e11SThomas Gleixner ADD, SUB(R), MUL, DIV(R), and SQRT */ 39da957e11SThomas Gleixner #define PR_24_BITS _Const_(0x000) 40da957e11SThomas Gleixner #define PR_53_BITS _Const_(0x200) 41da957e11SThomas Gleixner #define PR_64_BITS _Const_(0x300) 42da957e11SThomas Gleixner #define PR_RESERVED_BITS _Const_(0x100) 43da957e11SThomas Gleixner /* FULL_PRECISION simulates all exceptions masked */ 44da957e11SThomas Gleixner #define FULL_PRECISION (PR_64_BITS | RC_RND | 0x3f) 45da957e11SThomas Gleixner 46da957e11SThomas Gleixner #endif /* _CONTROLW_H_ */ 47