xref: /openbmc/linux/arch/arm/mach-omap2/prcm43xx.h (revision 0fdebc5e)
1*0fdebc5eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
237fbc27eSAfzal Mohammed /*
337fbc27eSAfzal Mohammed  * AM43x PRCM defines
437fbc27eSAfzal Mohammed  *
583bf6db0SAlexander A. Klimov  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
637fbc27eSAfzal Mohammed  */
737fbc27eSAfzal Mohammed 
837fbc27eSAfzal Mohammed #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
937fbc27eSAfzal Mohammed #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
1037fbc27eSAfzal Mohammed 
1137fbc27eSAfzal Mohammed #define AM43XX_PRM_PARTITION				1
1237fbc27eSAfzal Mohammed #define AM43XX_CM_PARTITION				1
1337fbc27eSAfzal Mohammed 
1437fbc27eSAfzal Mohammed /* PRM instances */
1537fbc27eSAfzal Mohammed #define AM43XX_PRM_OCP_SOCKET_INST			0x0000
1637fbc27eSAfzal Mohammed #define AM43XX_PRM_MPU_INST				0x0300
1737fbc27eSAfzal Mohammed #define AM43XX_PRM_GFX_INST				0x0400
1837fbc27eSAfzal Mohammed #define AM43XX_PRM_RTC_INST				0x0500
1937fbc27eSAfzal Mohammed #define AM43XX_PRM_TAMPER_INST				0x0600
2037fbc27eSAfzal Mohammed #define AM43XX_PRM_CEFUSE_INST				0x0700
2137fbc27eSAfzal Mohammed #define AM43XX_PRM_PER_INST				0x0800
2237fbc27eSAfzal Mohammed #define AM43XX_PRM_WKUP_INST				0x2000
2337fbc27eSAfzal Mohammed #define AM43XX_PRM_DEVICE_INST				0x4000
2437fbc27eSAfzal Mohammed 
2539db67a5SKeerthy /* PRM_IRQ offsets */
2639db67a5SKeerthy #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET			0x0004
2739db67a5SKeerthy #define AM43XX_PRM_IRQENABLE_MPU_OFFSET			0x0008
2839db67a5SKeerthy 
2939db67a5SKeerthy /* Other PRM offsets */
3039db67a5SKeerthy #define AM43XX_PRM_IO_PMCTRL_OFFSET			0x0024
3139db67a5SKeerthy 
3237fbc27eSAfzal Mohammed /* CM instances */
3337fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_INST				0x2800
3437fbc27eSAfzal Mohammed #define AM43XX_CM_MPU_INST				0x8300
3537fbc27eSAfzal Mohammed #define AM43XX_CM_GFX_INST				0x8400
3637fbc27eSAfzal Mohammed #define AM43XX_CM_RTC_INST				0x8500
3737fbc27eSAfzal Mohammed #define AM43XX_CM_TAMPER_INST				0x8600
3837fbc27eSAfzal Mohammed #define AM43XX_CM_CEFUSE_INST				0x8700
3937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_INST				0x8800
4037fbc27eSAfzal Mohammed 
4137fbc27eSAfzal Mohammed /* CD offsets */
4237fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L3_AON_CDOFFS			0x0000
4337fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS			0x0100
4437fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS		0x0200
4537fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_WKUP_CDOFFS			0x0300
4637fbc27eSAfzal Mohammed #define AM43XX_CM_MPU_MPU_CDOFFS			0x0000
4737fbc27eSAfzal Mohammed #define AM43XX_CM_GFX_GFX_L3_CDOFFS			0x0000
4837fbc27eSAfzal Mohammed #define AM43XX_CM_RTC_RTC_CDOFFS			0x0000
4937fbc27eSAfzal Mohammed #define AM43XX_CM_TAMPER_TAMPER_CDOFFS			0x0000
5037fbc27eSAfzal Mohammed #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS			0x0000
5137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L3_CDOFFS				0x0000
5237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L3S_CDOFFS			0x0200
5337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_ICSS_CDOFFS			0x0300
5437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L4LS_CDOFFS			0x0400
5537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EMIF_CDOFFS			0x0700
56da4f2b4cSDave Gerlach #define AM43XX_CM_PER_LCDC_CDOFFS			0x0800
5737fbc27eSAfzal Mohammed #define AM43XX_CM_PER_DSS_CDOFFS			0x0a00
5837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_CPSW_CDOFFS			0x0b00
5937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_OCPWP_L3_CDOFFS			0x0c00
6037fbc27eSAfzal Mohammed 
6137fbc27eSAfzal Mohammed /* CLK CTRL offsets */
6237fbc27eSAfzal Mohammed #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0020
63fabbe6dfSDave Gerlach #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0720
64fabbe6dfSDave Gerlach 
6537fbc27eSAfzal Mohammed #endif
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