Home
last modified time | relevance | path

Searched +full:0 +full:x0b00 (Results 1 – 25 of 140) sorted by relevance

123456

/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
H A Dclk-exynos5433.c50 #define ISP_PLL_LOCK 0x0000
51 #define AUD_PLL_LOCK 0x0004
52 #define ISP_PLL_CON0 0x0100
53 #define ISP_PLL_CON1 0x0104
54 #define ISP_PLL_FREQ_DET 0x0108
55 #define AUD_PLL_CON0 0x0110
56 #define AUD_PLL_CON1 0x0114
57 #define AUD_PLL_CON2 0x0118
58 #define AUD_PLL_FREQ_DET 0x011c
59 #define MUX_SEL_TOP0 0x0200
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dhi556.c23 #define HI556_REG_CHIP_ID 0x0f16
24 #define HI556_CHIP_ID 0x0556
26 #define HI556_REG_MODE_SELECT 0x0a00
27 #define HI556_MODE_STANDBY 0x0000
28 #define HI556_MODE_STREAMING 0x0100
31 #define HI556_REG_FLL 0x0006
32 #define HI556_FLL_30FPS 0x0814
33 #define HI556_FLL_30FPS_MIN 0x0814
34 #define HI556_FLL_MAX 0x7fff
37 #define HI556_REG_LLP 0x0008
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
21 reg = <0x0b40>;
26 #clock-cells = <0>;
34 #clock-cells = <0>;
37 reg = <0x0b00>;
42 #clock-cells = <0>;
45 reg = <0x0b00>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/openbmc/linux/arch/sh/include/mach-se/mach/
H A Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_hcd.h24 #define MUSB_CONTROL_EP 0
42 #define RH_INTERFACE 0x01
43 #define RH_ENDPOINT 0x02
44 #define RH_OTHER 0x03
46 #define RH_CLASS 0x20
47 #define RH_VENDOR 0x40
50 #define RH_GET_STATUS 0x0080
51 #define RH_CLEAR_FEATURE 0x0100
52 #define RH_SET_FEATURE 0x0300
53 #define RH_SET_ADDRESS 0x0500
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dsl811.h11 #define PDEBUG(level, fmt, args...) do {} while(0)
15 #define SL811_CTRL_A 0x00
16 #define SL811_ADDR_A 0x01
17 #define SL811_LEN_A 0x02
18 #define SL811_STS_A 0x03 /* read */
19 #define SL811_PIDEP_A 0x03 /* write */
20 #define SL811_CNT_A 0x04 /* read */
21 #define SL811_DEV_A 0x04 /* write */
22 #define SL811_CTRL1 0x05
23 #define SL811_INTR 0x06
[all …]
/openbmc/openbmc/poky/meta/recipes-core/glibc/ldconfig-native-2.12.1/
H A Dadd-riscv-support.patch33 case 0:
41 #define FLAG_ARM_LIBHF 0x0900
42 #define FLAG_AARCH64_LIB64 0x0a00
43 #define FLAG_ARM_LIBSF 0x0b00
44 +#define FLAG_RISCV_FLOAT_ABI_SOFT 0x0f00
45 +#define FLAG_RISCV_FLOAT_ABI_DOUBLE 0x1000
75 error(0, 0, "%s is a 64-bit ELF for unknown machine %lx\n",
H A Dadd-64-bit-flag-for-ELF64-entries.patch33 case 0:
41 #define FLAG_POWERPC_LIB64 0x0500
42 #define FLAG_MIPS64_LIBN32 0x0600
43 #define FLAG_MIPS64_LIBN64 0x0700
44 +#define FLAG_X8664_LIBX32 0x0800
45 +#define FLAG_ARM_LIBHF 0x0900
46 +#define FLAG_AARCH64_LIB64 0x0a00
47 +#define FLAG_ARM_LIBSF 0x0b00
52 index 0bf0de3..6e87afc 100644
108 + error(0, 0, "%s is a 64-bit ELF for unknown machine %lx\n",
[all …]
/openbmc/u-boot/drivers/pcmcia/
H A Dmarubun_pcmcia.c46 outw( 0x0000 , MRSHPC_MODE ); in pcmcia_on()
48 if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */ in pcmcia_on()
49 if ((inw(MRSHPC_CSR) & 0x0080) == 0){ in pcmcia_on()
50 outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in pcmcia_on()
52 outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */ in pcmcia_on()
63 outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */ in pcmcia_on()
64 if ((inw(MRSHPC_CSR) & 0x4000) != 0) in pcmcia_on()
65 outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */ in pcmcia_on()
67 outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */ in pcmcia_on()
70 outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */ in pcmcia_on()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-mxs.c22 #define MXS_SET 0x4
23 #define MXS_CLR 0x8
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.h18 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
19 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
20 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
21 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
22 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
23 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
27 #define RW_MGR_RANK_NONE 0xFF
28 #define RW_MGR_RANK_ALL 0x00
30 #define RW_MGR_ODT_MODE_OFF 0
41 #define PASS_ONE_BIT 0
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dmxs_gpio.c17 #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
18 #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
19 #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
20 #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
21 #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
22 #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
25 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
26 #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
27 #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
28 #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt1019.h11 #define RT1019_DEVICE_ID_VAL 0x1019
12 #define RT1019_DEVICE_ID_VAL2 0x6731
14 #define RT1019_RESET 0x0000
15 #define RT1019_IDS_CTRL 0x0011
16 #define RT1019_ASEL_CTRL 0x0013
17 #define RT1019_PWR_STRP_2 0x0019
18 #define RT1019_BEEP_TONE 0x001b
19 #define RT1019_VER_ID 0x005c
20 #define RT1019_VEND_ID_1 0x005e
21 #define RT1019_VEND_ID_2 0x005f
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h27 // base address: 0x22000
28 …VCE_STATUS 0x0a01
29 …ne mmVCE_STATUS_BASE_IDX 0
30 …VCE_VCPU_CNTL 0x0a05
31 …ne mmVCE_VCPU_CNTL_BASE_IDX 0
32 …VCE_VCPU_CACHE_OFFSET0 0x0a09
33 …ne mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
34 …VCE_VCPU_CACHE_SIZE0 0x0a0a
35 …ne mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
36 …VCE_VCPU_CACHE_OFFSET1 0x0a0b
[all …]
/openbmc/linux/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
/openbmc/linux/sound/pci/cs46xx/
H A Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]

123456