118297a21SFeifei Xu /* 218297a21SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 318297a21SFeifei Xu * 418297a21SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 518297a21SFeifei Xu * copy of this software and associated documentation files (the "Software"), 618297a21SFeifei Xu * to deal in the Software without restriction, including without limitation 718297a21SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 818297a21SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 918297a21SFeifei Xu * Software is furnished to do so, subject to the following conditions: 1018297a21SFeifei Xu * 1118297a21SFeifei Xu * The above copyright notice and this permission notice shall be included 1218297a21SFeifei Xu * in all copies or substantial portions of the Software. 1318297a21SFeifei Xu * 1418297a21SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1518297a21SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1618297a21SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1718297a21SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 1818297a21SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1918297a21SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2018297a21SFeifei Xu */ 2118297a21SFeifei Xu #ifndef _vce_4_0_OFFSET_HEADER 2218297a21SFeifei Xu #define _vce_4_0_OFFSET_HEADER 2318297a21SFeifei Xu 2418297a21SFeifei Xu 2518297a21SFeifei Xu 2618297a21SFeifei Xu // addressBlock: vce0_vce_dec 2718297a21SFeifei Xu // base address: 0x22000 2818297a21SFeifei Xu #define mmVCE_STATUS 0x0a01 2918297a21SFeifei Xu #define mmVCE_STATUS_BASE_IDX 0 3018297a21SFeifei Xu #define mmVCE_VCPU_CNTL 0x0a05 3118297a21SFeifei Xu #define mmVCE_VCPU_CNTL_BASE_IDX 0 3218297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET0 0x0a09 3318297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0 3418297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE0 0x0a0a 3518297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0 3618297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b 3718297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0 3818297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE1 0x0a0c 3918297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0 4018297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d 4118297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0 4218297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE2 0x0a0e 4318297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0 4418297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f 4518297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0 4618297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE3 0x0a10 4718297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0 4818297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET4 0x0a11 4918297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0 5018297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE4 0x0a12 5118297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0 5218297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET5 0x0a13 5318297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0 5418297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE5 0x0a14 5518297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0 5618297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET6 0x0a15 5718297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0 5818297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE6 0x0a16 5918297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0 6018297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET7 0x0a17 6118297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0 6218297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE7 0x0a18 6318297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0 6418297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET8 0x0a19 6518297a21SFeifei Xu #define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0 6618297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE8 0x0a1a 6718297a21SFeifei Xu #define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0 6818297a21SFeifei Xu #define mmVCE_SOFT_RESET 0x0a48 6918297a21SFeifei Xu #define mmVCE_SOFT_RESET_BASE_IDX 0 7018297a21SFeifei Xu #define mmVCE_RB_BASE_LO2 0x0a5b 7118297a21SFeifei Xu #define mmVCE_RB_BASE_LO2_BASE_IDX 0 7218297a21SFeifei Xu #define mmVCE_RB_BASE_HI2 0x0a5c 7318297a21SFeifei Xu #define mmVCE_RB_BASE_HI2_BASE_IDX 0 7418297a21SFeifei Xu #define mmVCE_RB_SIZE2 0x0a5d 7518297a21SFeifei Xu #define mmVCE_RB_SIZE2_BASE_IDX 0 7618297a21SFeifei Xu #define mmVCE_RB_RPTR2 0x0a5e 7718297a21SFeifei Xu #define mmVCE_RB_RPTR2_BASE_IDX 0 7818297a21SFeifei Xu #define mmVCE_RB_WPTR2 0x0a5f 7918297a21SFeifei Xu #define mmVCE_RB_WPTR2_BASE_IDX 0 8018297a21SFeifei Xu #define mmVCE_RB_BASE_LO 0x0a60 8118297a21SFeifei Xu #define mmVCE_RB_BASE_LO_BASE_IDX 0 8218297a21SFeifei Xu #define mmVCE_RB_BASE_HI 0x0a61 8318297a21SFeifei Xu #define mmVCE_RB_BASE_HI_BASE_IDX 0 8418297a21SFeifei Xu #define mmVCE_RB_SIZE 0x0a62 8518297a21SFeifei Xu #define mmVCE_RB_SIZE_BASE_IDX 0 8618297a21SFeifei Xu #define mmVCE_RB_RPTR 0x0a63 8718297a21SFeifei Xu #define mmVCE_RB_RPTR_BASE_IDX 0 8818297a21SFeifei Xu #define mmVCE_RB_WPTR 0x0a64 8918297a21SFeifei Xu #define mmVCE_RB_WPTR_BASE_IDX 0 9018297a21SFeifei Xu #define mmVCE_RB_ARB_CTRL 0x0a9f 9118297a21SFeifei Xu #define mmVCE_RB_ARB_CTRL_BASE_IDX 0 9218297a21SFeifei Xu #define mmVCE_CLOCK_GATING_A 0x0abe 9318297a21SFeifei Xu #define mmVCE_CLOCK_GATING_A_BASE_IDX 0 9418297a21SFeifei Xu #define mmVCE_CLOCK_GATING_B 0x0abf 9518297a21SFeifei Xu #define mmVCE_CLOCK_GATING_B_BASE_IDX 0 9618297a21SFeifei Xu #define mmVCE_RB_BASE_LO3 0x0ad4 9718297a21SFeifei Xu #define mmVCE_RB_BASE_LO3_BASE_IDX 0 9818297a21SFeifei Xu #define mmVCE_RB_BASE_HI3 0x0ad5 9918297a21SFeifei Xu #define mmVCE_RB_BASE_HI3_BASE_IDX 0 10018297a21SFeifei Xu #define mmVCE_RB_SIZE3 0x0ad6 10118297a21SFeifei Xu #define mmVCE_RB_SIZE3_BASE_IDX 0 10218297a21SFeifei Xu #define mmVCE_RB_RPTR3 0x0ad7 10318297a21SFeifei Xu #define mmVCE_RB_RPTR3_BASE_IDX 0 10418297a21SFeifei Xu #define mmVCE_RB_WPTR3 0x0ad8 10518297a21SFeifei Xu #define mmVCE_RB_WPTR3_BASE_IDX 0 10618297a21SFeifei Xu #define mmVCE_SYS_INT_EN 0x0b00 10718297a21SFeifei Xu #define mmVCE_SYS_INT_EN_BASE_IDX 0 10818297a21SFeifei Xu #define mmVCE_SYS_INT_ACK 0x0b01 10918297a21SFeifei Xu #define mmVCE_SYS_INT_ACK_BASE_IDX 0 11018297a21SFeifei Xu #define mmVCE_SYS_INT_STATUS 0x0b01 11118297a21SFeifei Xu #define mmVCE_SYS_INT_STATUS_BASE_IDX 0 11218297a21SFeifei Xu 11318297a21SFeifei Xu 11418297a21SFeifei Xu // addressBlock: vce0_ctl_dec 11518297a21SFeifei Xu // base address: 0x22780 11618297a21SFeifei Xu #define mmVCE_UENC_CLOCK_GATING 0x0bef 11718297a21SFeifei Xu #define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0 11818297a21SFeifei Xu #define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0 11918297a21SFeifei Xu #define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0 12018297a21SFeifei Xu #define mmVCE_UENC_CLOCK_GATING_2 0x0c10 12118297a21SFeifei Xu #define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0 12218297a21SFeifei Xu 12318297a21SFeifei Xu 12418297a21SFeifei Xu // addressBlock: vce0_vce_sclk_dec 12518297a21SFeifei Xu // base address: 0x23700 12618297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc 12718297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0 12818297a21SFeifei Xu #define mmVCE_LMI_CTRL2 0x0fcf 12918297a21SFeifei Xu #define mmVCE_LMI_CTRL2_BASE_IDX 0 13018297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL3 0x0fd0 13118297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0 13218297a21SFeifei Xu #define mmVCE_LMI_CTRL 0x0fd6 13318297a21SFeifei Xu #define mmVCE_LMI_CTRL_BASE_IDX 0 13418297a21SFeifei Xu #define mmVCE_LMI_STATUS 0x0fd7 13518297a21SFeifei Xu #define mmVCE_LMI_STATUS_BASE_IDX 0 13618297a21SFeifei Xu #define mmVCE_LMI_VM_CTRL 0x0fd8 13718297a21SFeifei Xu #define mmVCE_LMI_VM_CTRL_BASE_IDX 0 13818297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL 0x0fdd 13918297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0 14018297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL1 0x0fde 14118297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0 14218297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL2 0x0fe2 14318297a21SFeifei Xu #define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0 14418297a21SFeifei Xu #define mmVCE_LMI_CACHE_CTRL 0x0fec 14518297a21SFeifei Xu #define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0 14618297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086 14718297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0 14818297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087 14918297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0 15018297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088 15118297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0 15218297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089 15318297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0 15418297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a 15518297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0 15618297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b 15718297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0 15818297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c 15918297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0 16018297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d 16118297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0 16218297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096 16318297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0 16418297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097 16518297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0 16618297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098 16718297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0 16818297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099 16918297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0 17018297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a 17118297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0 17218297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b 17318297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0 17418297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c 17518297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0 17618297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d 17718297a21SFeifei Xu #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0 17818297a21SFeifei Xu 17918297a21SFeifei Xu 18018297a21SFeifei Xu // addressBlock: vce0_mmsch_dec 18118297a21SFeifei Xu // base address: 0x23b00 18218297a21SFeifei Xu #define mmVCE_MMSCH_VF_VMID 0x10cb 18318297a21SFeifei Xu #define mmVCE_MMSCH_VF_VMID_BASE_IDX 0 18418297a21SFeifei Xu #define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc 18518297a21SFeifei Xu #define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 18618297a21SFeifei Xu #define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd 18718297a21SFeifei Xu #define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 18818297a21SFeifei Xu #define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce 18918297a21SFeifei Xu #define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0 19018297a21SFeifei Xu #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf 19118297a21SFeifei Xu #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0 19218297a21SFeifei Xu #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0 19318297a21SFeifei Xu #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0 19418297a21SFeifei Xu #define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1 19518297a21SFeifei Xu #define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0 19618297a21SFeifei Xu #define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2 19718297a21SFeifei Xu #define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0 19818297a21SFeifei Xu #define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3 19918297a21SFeifei Xu #define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0 20018297a21SFeifei Xu 20118297a21SFeifei Xu 20218297a21SFeifei Xu // addressBlock: vce0_vce_rb_pg_dec 20318297a21SFeifei Xu // base address: 0x23fa0 20418297a21SFeifei Xu #define mmVCE_HW_VERSION 0x11e8 20518297a21SFeifei Xu #define mmVCE_HW_VERSION_BASE_IDX 0 20618297a21SFeifei Xu 20718297a21SFeifei Xu 20818297a21SFeifei Xu #endif 209