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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
H A Dclk-exynos850.c34 /* Register Offset definitions for CMU_TOP (0x120e0000) */
35 #define PLL_LOCKTIME_PLL_MMC 0x0000
36 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
37 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
38 #define PLL_CON0_PLL_MMC 0x0100
39 #define PLL_CON3_PLL_MMC 0x010c
40 #define PLL_CON0_PLL_SHARED0 0x0140
41 #define PLL_CON3_PLL_SHARED0 0x014c
42 #define PLL_CON0_PLL_SHARED1 0x0180
43 #define PLL_CON3_PLL_SHARED1 0x018c
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
H A Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dcm81xx.h13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
25 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
26 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dcm1_7xx.h23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
H A Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmicrochip_t1s.c14 #define PHY_ID_LAN867X_REVB1 0x0007C162
15 #define PHY_ID_LAN865X_REVB0 0x0007C1B3
17 #define LAN867X_REG_STS2 0x0019
21 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
22 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
23 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
24 #define LAN865X_REG_STS2 0x0019
30 * RMW 0x1F 0x00D0 0x0002 0x0E03
31 * RMW 0x1F 0x00D1 0x0000 0x0300
32 * RMW 0x1F 0x0084 0x3380 0xFFC0
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dlantiq_pce.h11 OUT_MAC0 = 0,
55 #define INSTR 0
61 FLAG_ITAG = 0,
89 MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
90 MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
91 MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
92 MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
93 MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
94 MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
95 MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
[all …]
/openbmc/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/openbmc/u-boot/board/gdsys/a38x/
H A Dhydra.h2 u32 reflection_low; /* 0x0000 */
3 u32 versions; /* 0x0004 */
4 u32 fpga_version; /* 0x0008 */
5 u32 fpga_features; /* 0x000c */
6 u32 reserved0[4]; /* 0x0010 */
7 u32 control; /* 0x0020 */
8 u32 reserved1[375]; /* 0x0024 */
9 u32 qsgmii_port_state[80]; /* 0x0600 */
/openbmc/linux/samples/bpf/
H A Dnet_shared.h9 #define ETH_P_802_3_MIN 0x0600
10 #define ETH_P_8021Q 0x8100
11 #define ETH_P_8021AD 0x88A8
12 #define ETH_P_IP 0x0800
13 #define ETH_P_IPV6 0x86DD
14 #define ETH_P_ARP 0x0806
17 #define TC_ACT_OK 0
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dcm.h11 #define GCR_BASE 0x0008
12 #define GCR_BASE_UPPER 0x000c
13 #define GCR_REV 0x0030
14 #define GCR_L2_CONFIG 0x0130
15 #define GCR_L2_TAG_ADDR 0x0600
16 #define GCR_L2_TAG_ADDR_UPPER 0x0604
17 #define GCR_L2_TAG_STATE 0x0608
18 #define GCR_L2_TAG_STATE_UPPER 0x060c
19 #define GCR_L2_DATA 0x0610
20 #define GCR_L2_DATA_UPPER 0x0614
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dtegra186_gpio.c66 return 0; in tegra186_gpio_set_out()
82 return 0; in tegra186_gpio_set_val()
95 ret = tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_direction_output()
122 return tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_set_value()
143 gpio = args->args[0]; in tegra186_gpio_xlate()
149 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; in tegra186_gpio_xlate()
151 return 0; in tegra186_gpio_xlate()
177 return 0; in tegra186_gpio_bind()
183 for (port = 0; port < ctlr_data->port_count; port++) { in tegra186_gpio_bind()
200 return 0; in tegra186_gpio_bind()
[all …]
/openbmc/u-boot/arch/mips/mach-pic32/include/mach/
H A Dpic32.h13 #define PIC32_CFG_BASE 0x1f800000
16 #define CFGCON 0x0000
17 #define DEVID 0x0020
18 #define SYSKEY 0x0030
19 #define PMD1 0x0040
20 #define PMD7 0x00a0
21 #define CFGEBIA 0x00c0
22 #define CFGEBIC 0x00d0
23 #define CFGPG 0x00e0
24 #define CFGMPLL 0x0100
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl8712_debugctrl_bitdef.h11 #define _BIST_RST BIT(0)
14 #define _LMS_MSK 0x03
17 #define _OVSEL_MSK 0x0600
20 #define _WDGEN_MSK 0x00FF
21 #define _WDGEN_SHT 0
24 #define _TXTIMER_MSK 0xF000
26 #define _TXNUM_MSK 0x0F00
28 #define _RXTIMER_MSK 0x00F0
30 #define _RXNUM_MSK 0x000F
31 #define _RXNUM_SHT 0
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/openbmc/openpower-hw-diags/attn/
H A Dattn_common.hpp14 RC_SUCCESS = 0,
24 reserved = 0x0000,
25 attnHandler = 0x0100,
26 tiHandler = 0x0200,
27 handlePhypTi = 0x0300,
28 handleHbTi = 0x0400,
29 addHbStatusRegs = 0x0500,
30 attnLogging = 0x0600
36 ATTN_NO_ERROR = 0,
/openbmc/linux/drivers/media/usb/dvb-usb-v2/
H A Drtl28xxu.h40 #define DEMOD 0x0000
41 #define USB 0x0100
42 #define SYS 0x0200
43 #define I2C 0x0300
44 #define I2C_DA 0x0600
46 #define CMD_WR_FLAG 0x0010
47 #define CMD_DEMOD_RD 0x0000
48 #define CMD_DEMOD_WR 0x0010
49 #define CMD_USB_RD 0x0100
50 #define CMD_USB_WR 0x0110
[all …]

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