1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2a61ef470SAmbresh K /* 3a61ef470SAmbresh K * DRA7xx PRCM MPU instance offset macros 4a61ef470SAmbresh K * 583bf6db0SAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6a61ef470SAmbresh K * 7a61ef470SAmbresh K * Generated by code originally written by: 8a61ef470SAmbresh K * Paul Walmsley (paul@pwsan.com) 9a61ef470SAmbresh K * Rajendra Nayak (rnayak@ti.com) 10a61ef470SAmbresh K * Benoit Cousson (b-cousson@ti.com) 11a61ef470SAmbresh K * 12a61ef470SAmbresh K * This file is automatically generated from the OMAP hardware databases. 13a61ef470SAmbresh K * We respectfully ask that any modifications to this file be coordinated 14a61ef470SAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 15a61ef470SAmbresh K * authors above to ensure that the autogeneration scripts are kept 16a61ef470SAmbresh K * up-to-date with the file contents. 17a61ef470SAmbresh K */ 18a61ef470SAmbresh K 19a61ef470SAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H 20a61ef470SAmbresh K #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H 21a61ef470SAmbresh K 22a61ef470SAmbresh K #include "prcm_mpu_44xx_54xx.h" 23a61ef470SAmbresh K 24a61ef470SAmbresh K #define DRA7XX_PRCM_MPU_BASE 0x48243000 25a61ef470SAmbresh K 26a61ef470SAmbresh K #define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \ 27a61ef470SAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg)) 28a61ef470SAmbresh K 29a61ef470SAmbresh K /* MPU_PRCM instances */ 30a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000 31a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200 32a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400 33a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600 34a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800 35a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00 36a61ef470SAmbresh K 37a61ef470SAmbresh K /* PRCM_MPU clockdomain register offsets (from instance start) */ 38a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000 39a61ef470SAmbresh K #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000 40a61ef470SAmbresh K 41a61ef470SAmbresh K 42a61ef470SAmbresh K /* MPU_PRCM */ 43a61ef470SAmbresh K 44a61ef470SAmbresh K /* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */ 45a61ef470SAmbresh K #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000 46a61ef470SAmbresh K 47a61ef470SAmbresh K /* MPU_PRCM.PRCM_MPU_DEVICE register offsets */ 48a61ef470SAmbresh K #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 49a61ef470SAmbresh K #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 50a61ef470SAmbresh K 51a61ef470SAmbresh K /* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */ 52a61ef470SAmbresh K #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 53a61ef470SAmbresh K #define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004 54a61ef470SAmbresh K #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 55a61ef470SAmbresh K #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 56a61ef470SAmbresh K #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 57a61ef470SAmbresh K 58a61ef470SAmbresh K /* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */ 59a61ef470SAmbresh K #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 60a61ef470SAmbresh K #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 61a61ef470SAmbresh K #define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020) 62a61ef470SAmbresh K 63a61ef470SAmbresh K /* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */ 64a61ef470SAmbresh K #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 65a61ef470SAmbresh K #define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004 66a61ef470SAmbresh K #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 67a61ef470SAmbresh K #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 68a61ef470SAmbresh K #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 69a61ef470SAmbresh K 70a61ef470SAmbresh K /* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */ 71a61ef470SAmbresh K #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 72a61ef470SAmbresh K #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 73a61ef470SAmbresh K #define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020) 74a61ef470SAmbresh K 75a61ef470SAmbresh K #endif 76