1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 240ca6091SAmbresh K /* 340ca6091SAmbresh K * DRA7xx CM2 instance offset macros 440ca6091SAmbresh K * 583bf6db0SAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 640ca6091SAmbresh K * 740ca6091SAmbresh K * Generated by code originally written by: 840ca6091SAmbresh K * Paul Walmsley (paul@pwsan.com) 940ca6091SAmbresh K * Rajendra Nayak (rnayak@ti.com) 1040ca6091SAmbresh K * Benoit Cousson (b-cousson@ti.com) 1140ca6091SAmbresh K * 1240ca6091SAmbresh K * This file is automatically generated from the OMAP hardware databases. 1340ca6091SAmbresh K * We respectfully ask that any modifications to this file be coordinated 1440ca6091SAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 1540ca6091SAmbresh K * authors above to ensure that the autogeneration scripts are kept 1640ca6091SAmbresh K * up-to-date with the file contents. 1740ca6091SAmbresh K */ 1840ca6091SAmbresh K 1940ca6091SAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H 2040ca6091SAmbresh K #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H 2140ca6091SAmbresh K 2240ca6091SAmbresh K /* CM2 base address */ 2340ca6091SAmbresh K #define DRA7XX_CM_CORE_BASE 0x4a008000 2440ca6091SAmbresh K 2540ca6091SAmbresh K #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ 2640ca6091SAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) 2740ca6091SAmbresh K 2840ca6091SAmbresh K /* CM_CORE instances */ 2940ca6091SAmbresh K #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 3040ca6091SAmbresh K #define DRA7XX_CM_CORE_CKGEN_INST 0x0104 3140ca6091SAmbresh K #define DRA7XX_CM_CORE_COREAON_INST 0x0600 3240ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_INST 0x0700 3340ca6091SAmbresh K #define DRA7XX_CM_CORE_IVA_INST 0x0f00 3440ca6091SAmbresh K #define DRA7XX_CM_CORE_CAM_INST 0x1000 3540ca6091SAmbresh K #define DRA7XX_CM_CORE_DSS_INST 0x1100 3640ca6091SAmbresh K #define DRA7XX_CM_CORE_GPU_INST 0x1200 3740ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 3840ca6091SAmbresh K #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 3940ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_INST 0x1700 4040ca6091SAmbresh K 4140ca6091SAmbresh K /* CM_CORE clockdomain register offsets (from instance start) */ 4240ca6091SAmbresh K #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 4340ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 4440ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 4540ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 4640ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 4740ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 4840ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 4940ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 5040ca6091SAmbresh K #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 5140ca6091SAmbresh K #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 5240ca6091SAmbresh K #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 5340ca6091SAmbresh K #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 5440ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 5540ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 5640ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 5740ca6091SAmbresh K #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 5840ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 5940ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 6040ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc 6140ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 6240ca6091SAmbresh K 6340ca6091SAmbresh K #endif 64