1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 240ca6091SAmbresh K /* 340ca6091SAmbresh K * DRA7xx CM1 instance offset macros 440ca6091SAmbresh K * 583bf6db0SAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 640ca6091SAmbresh K * 740ca6091SAmbresh K * Generated by code originally written by: 840ca6091SAmbresh K * Paul Walmsley (paul@pwsan.com) 940ca6091SAmbresh K * Rajendra Nayak (rnayak@ti.com) 1040ca6091SAmbresh K * Benoit Cousson (b-cousson@ti.com) 1140ca6091SAmbresh K * 1240ca6091SAmbresh K * This file is automatically generated from the OMAP hardware databases. 1340ca6091SAmbresh K * We respectfully ask that any modifications to this file be coordinated 1440ca6091SAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 1540ca6091SAmbresh K * authors above to ensure that the autogeneration scripts are kept 1640ca6091SAmbresh K * up-to-date with the file contents. 1740ca6091SAmbresh K */ 1840ca6091SAmbresh K 1940ca6091SAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H 2040ca6091SAmbresh K #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H 2140ca6091SAmbresh K 2240ca6091SAmbresh K /* CM1 base address */ 2340ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 2440ca6091SAmbresh K 2540ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \ 2640ca6091SAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg)) 2740ca6091SAmbresh K 2840ca6091SAmbresh K /* CM_CORE_AON instances */ 2940ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 3040ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100 3140ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300 3240ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400 3340ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500 3440ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600 3540ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640 3640ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680 3740ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0 3840ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700 3940ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_RTC_INST 0x0740 4040ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_VPE_INST 0x0760 4140ca6091SAmbresh K 4240ca6091SAmbresh K /* CM_CORE_AON clockdomain register offsets (from instance start) */ 4340ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 4440ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000 4540ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000 4640ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040 4740ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000 4840ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000 4940ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000 5040ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000 5140ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000 5240ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000 5340ca6091SAmbresh K #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000 5440ca6091SAmbresh K 5540ca6091SAmbresh K #endif 56