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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcm1_54xx.h22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
35 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
36 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
37 #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
H A Dcm1_44xx.h26 #define OMAP4430_CM1_BASE 0x4a004000
32 #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM1_CKGEN_INST 0x0100
34 #define OMAP4430_CM1_MPU_INST 0x0300
35 #define OMAP4430_CM1_TESLA_INST 0x0400
36 #define OMAP4430_CM1_ABE_INST 0x0500
39 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
40 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
41 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dcm81xx.h13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
25 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
26 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
H A Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dcm1_7xx.h23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
H A Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/openbmc/linux/sound/soc/codecs/
H A Duda1380.h11 #define UDA1380_CLK 0x00
12 #define UDA1380_IFACE 0x01
13 #define UDA1380_PM 0x02
14 #define UDA1380_AMIX 0x03
15 #define UDA1380_HP 0x04
16 #define UDA1380_MVOL 0x10
17 #define UDA1380_MIXVOL 0x11
18 #define UDA1380_MODE 0x12
19 #define UDA1380_DEEMP 0x13
20 #define UDA1380_MIXER 0x14
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/openbmc/openpower-hw-diags/attn/
H A Dattn_common.hpp14 RC_SUCCESS = 0,
24 reserved = 0x0000,
25 attnHandler = 0x0100,
26 tiHandler = 0x0200,
27 handlePhypTi = 0x0300,
28 handleHbTi = 0x0400,
29 addHbStatusRegs = 0x0500,
30 attnLogging = 0x0600
36 ATTN_NO_ERROR = 0,
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt18 - #clock-cells : from common clock binding; shall be set to 0.
31 #clock-cells = <0>;
33 reg = <0x021c>, <0x0220>;
38 #clock-cells = <0>;
44 reg = <0x0500>, <0x0530>, <0x0520>;
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_hcd.h24 #define MUSB_CONTROL_EP 0
42 #define RH_INTERFACE 0x01
43 #define RH_ENDPOINT 0x02
44 #define RH_OTHER 0x03
46 #define RH_CLASS 0x20
47 #define RH_VENDOR 0x40
50 #define RH_GET_STATUS 0x0080
51 #define RH_CLEAR_FEATURE 0x0100
52 #define RH_SET_FEATURE 0x0300
53 #define RH_SET_ADDRESS 0x0500
[all …]
/openbmc/linux/drivers/net/ethernet/qualcomm/
H A Dqca_7k.h35 #define QCA7K_SPI_WRITE (0 << 15)
37 #define QCA7K_SPI_EXTERNAL (0 << 14)
41 #define QCASPI_HW_BUF_LEN 0xC5B
44 #define SPI_REG_BFR_SIZE 0x0100
45 #define SPI_REG_WRBUF_SPC_AVA 0x0200
46 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
47 #define SPI_REG_SPI_CONFIG 0x0400
48 #define SPI_REG_SPI_STATUS 0x0500
49 #define SPI_REG_INTR_CAUSE 0x0C00
50 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/
H A Diomap.h16 #define MCFG_BASE_SIZE 0x10000000
19 #define TEMP_BASE_ADDRESS 0xfd000000
22 #define ABORT_BASE_ADDRESS 0xfeb00000
23 #define ABORT_BASE_SIZE 0x00100000
26 #define HPET_BASE_ADDRESS 0xfed00000
27 #define HPET_BASE_SIZE 0x400
30 #define SPI_BASE_ADDRESS 0xfed01000
31 #define SPI_BASE_SIZE 0x400
34 #define PMC_BASE_ADDRESS 0xfed03000
35 #define PMC_BASE_SIZE 0x400
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dcell-regs.h28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
28 #define INTEL_CX0_LANE0 BIT(0)
44 return 0; in lane_mask_to_lane()
86 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
117 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
124 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
131 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
137 return 0; in intel_cx0_wait_for_ack()
162 if (ack < 0) in __intel_cx0_read_once()
179 for (i = 0; i < 3; i++) { in __intel_cx0_read()
[all …]
/openbmc/u-boot/include/
H A Dmsc01.h14 #define MSC01_BIU_IP1BAS1L_OFS 0x0208
15 #define MSC01_BIU_IP1MSK1L_OFS 0x0218
16 #define MSC01_BIU_IP1BAS2L_OFS 0x0248
17 #define MSC01_BIU_IP1MSK2L_OFS 0x0258
18 #define MSC01_BIU_IP2BAS1L_OFS 0x0288
19 #define MSC01_BIU_IP2MSK1L_OFS 0x0298
20 #define MSC01_BIU_IP2BAS2L_OFS 0x02c8
21 #define MSC01_BIU_IP2MSK2L_OFS 0x02d8
22 #define MSC01_BIU_IP3BAS1L_OFS 0x0308
23 #define MSC01_BIU_IP3MSK1L_OFS 0x0318
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dsl811.h11 #define PDEBUG(level, fmt, args...) do {} while(0)
15 #define SL811_CTRL_A 0x00
16 #define SL811_ADDR_A 0x01
17 #define SL811_LEN_A 0x02
18 #define SL811_STS_A 0x03 /* read */
19 #define SL811_PIDEP_A 0x03 /* write */
20 #define SL811_CNT_A 0x04 /* read */
21 #define SL811_DEV_A 0x04 /* write */
22 #define SL811_CTRL1 0x05
23 #define SL811_INTR 0x06
[all …]
/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz_ptp_reg.h9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120
11 #define LED_OVR_1 BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128
18 #define REG_PTP_CLK_CTRL 0x0500
26 #define PTP_CLK_RESET BIT(0)
28 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
30 #define PTP_RTC_SUB_NANOSEC_M 0x0007
31 #define PTP_RTC_0NS 0x00
33 #define REG_PTP_RTC_NANOSEC 0x0504
35 #define REG_PTP_RTC_SEC 0x0508
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sw/
H A Dchan.c35 case 0x0000: in nvkm_sw_chan_mthd()
37 case 0x0500: in nvkm_sw_chan_mthd()
38 nvkm_event_ntfy(&chan->event, 0, NVKM_SW_CHAN_EVENT_PAGE_FLIP); in nvkm_sw_chan_mthd()

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