1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 242f8ebfdSBin Meng /* 342f8ebfdSBin Meng * Copyright (C) 2013 Google Inc. 442f8ebfdSBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 542f8ebfdSBin Meng * 642f8ebfdSBin Meng * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h 742f8ebfdSBin Meng */ 842f8ebfdSBin Meng 942f8ebfdSBin Meng #ifndef _BAYTRAIL_IOMAP_H_ 1042f8ebfdSBin Meng #define _BAYTRAIL_IOMAP_H_ 1142f8ebfdSBin Meng 1242f8ebfdSBin Meng /* Memory Mapped IO bases */ 1342f8ebfdSBin Meng 1442f8ebfdSBin Meng /* PCI Configuration Space */ 1542f8ebfdSBin Meng #define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE 1642f8ebfdSBin Meng #define MCFG_BASE_SIZE 0x10000000 1742f8ebfdSBin Meng 1842f8ebfdSBin Meng /* Temporary Base Address */ 1942f8ebfdSBin Meng #define TEMP_BASE_ADDRESS 0xfd000000 2042f8ebfdSBin Meng 2142f8ebfdSBin Meng /* Transactions in this range will abort */ 2242f8ebfdSBin Meng #define ABORT_BASE_ADDRESS 0xfeb00000 2342f8ebfdSBin Meng #define ABORT_BASE_SIZE 0x00100000 2442f8ebfdSBin Meng 2542f8ebfdSBin Meng /* High Performance Event Timer */ 2642f8ebfdSBin Meng #define HPET_BASE_ADDRESS 0xfed00000 2742f8ebfdSBin Meng #define HPET_BASE_SIZE 0x400 2842f8ebfdSBin Meng 2942f8ebfdSBin Meng /* SPI Bus */ 3042f8ebfdSBin Meng #define SPI_BASE_ADDRESS 0xfed01000 3142f8ebfdSBin Meng #define SPI_BASE_SIZE 0x400 3242f8ebfdSBin Meng 3342f8ebfdSBin Meng /* Power Management Controller */ 3442f8ebfdSBin Meng #define PMC_BASE_ADDRESS 0xfed03000 3542f8ebfdSBin Meng #define PMC_BASE_SIZE 0x400 3642f8ebfdSBin Meng 37fcf2fba4SBin Meng #define GEN_PMCON1 0x20 38fcf2fba4SBin Meng #define UART_EN (1 << 24) 39fcf2fba4SBin Meng #define DISB (1 << 23) 40fcf2fba4SBin Meng #define MEM_SR (1 << 21) 41fcf2fba4SBin Meng #define SRS (1 << 20) 42fcf2fba4SBin Meng #define CTS (1 << 19) 43fcf2fba4SBin Meng #define MS4V (1 << 18) 44fcf2fba4SBin Meng #define PWR_FLR (1 << 16) 45fcf2fba4SBin Meng #define PME_B0_S5_DIS (1 << 15) 46fcf2fba4SBin Meng #define SUS_PWR_FLR (1 << 14) 47fcf2fba4SBin Meng #define WOL_EN_OVRD (1 << 13) 48fcf2fba4SBin Meng #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) 49fcf2fba4SBin Meng #define GEN_RST_STS (1 << 9) 50fcf2fba4SBin Meng #define RPS (1 << 2) 51fcf2fba4SBin Meng #define AFTERG3_EN (1 << 0) 52fcf2fba4SBin Meng #define GEN_PMCON2 0x24 53fcf2fba4SBin Meng #define SLPSX_STR_POL_LOCK (1 << 18) 54fcf2fba4SBin Meng #define BIOS_PCI_EXP_EN (1 << 10) 55fcf2fba4SBin Meng #define PWRBTN_LVL (1 << 9) 56fcf2fba4SBin Meng #define SMI_LOCK (1 << 4) 57fcf2fba4SBin Meng 5842f8ebfdSBin Meng /* Power Management Unit */ 5942f8ebfdSBin Meng #define PUNIT_BASE_ADDRESS 0xfed05000 6042f8ebfdSBin Meng #define PUNIT_BASE_SIZE 0x800 6142f8ebfdSBin Meng 6242f8ebfdSBin Meng /* Intel Legacy Block */ 6342f8ebfdSBin Meng #define ILB_BASE_ADDRESS 0xfed08000 6442f8ebfdSBin Meng #define ILB_BASE_SIZE 0x400 6542f8ebfdSBin Meng 6642f8ebfdSBin Meng /* IO Memory */ 6742f8ebfdSBin Meng #define IO_BASE_ADDRESS 0xfed0c000 6842f8ebfdSBin Meng #define IO_BASE_OFFSET_GPSCORE 0x0000 6942f8ebfdSBin Meng #define IO_BASE_OFFSET_GPNCORE 0x1000 7042f8ebfdSBin Meng #define IO_BASE_OFFSET_GPSSUS 0x2000 7142f8ebfdSBin Meng #define IO_BASE_SIZE 0x4000 7242f8ebfdSBin Meng 7342f8ebfdSBin Meng /* Root Complex Base Address */ 7442f8ebfdSBin Meng #define RCBA_BASE_ADDRESS 0xfed1c000 7542f8ebfdSBin Meng #define RCBA_BASE_SIZE 0x400 7642f8ebfdSBin Meng 7742f8ebfdSBin Meng /* MODPHY */ 7842f8ebfdSBin Meng #define MPHY_BASE_ADDRESS 0xfef00000 7942f8ebfdSBin Meng #define MPHY_BASE_SIZE 0x100000 8042f8ebfdSBin Meng 8142f8ebfdSBin Meng /* IO Port bases */ 8242f8ebfdSBin Meng #define ACPI_BASE_ADDRESS 0x0400 8342f8ebfdSBin Meng #define ACPI_BASE_SIZE 0x80 8442f8ebfdSBin Meng 85fcf2fba4SBin Meng #define PM1_STS 0x00 86fcf2fba4SBin Meng #define PM1_CNT 0x04 87fcf2fba4SBin Meng 8842f8ebfdSBin Meng #define GPIO_BASE_ADDRESS 0x0500 8942f8ebfdSBin Meng #define GPIO_BASE_SIZE 0x100 9042f8ebfdSBin Meng 9142f8ebfdSBin Meng #define SMBUS_BASE_ADDRESS 0xefa0 9242f8ebfdSBin Meng 9342f8ebfdSBin Meng #endif /* _BAYTRAIL_IOMAP_H_ */ 94