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Searched +full:0 +full:x03900000 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v12_0.h29 #define MP0_Public 0x03800000
30 #define MP0_SRAM 0x03900000
31 #define MP1_Public 0x03b00000
32 #define MP1_SRAM 0x03c00004
H A Dsmu_v13_0.h31 #define MP0_Public 0x03800000
32 #define MP0_SRAM 0x03900000
33 #define MP1_Public 0x03b00000
34 #define MP1_SRAM 0x03c00004
37 #define smnMP1_FIRMWARE_FLAGS 0x3010024
38 #define smnMP1_V13_0_4_FIRMWARE_FLAGS 0x3010028
39 #define smnMP0_FW_INTF 0x30101c0
40 #define smnMP1_PUB_CTRL 0x3010b14
42 #define TEMP_RANGE_MIN (0)
45 #define SMU13_TOOL_SIZE 0x19000
[all …]
H A Dsmu_v11_0.h28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30 #define SMU11_DRIVER_IF_VERSION_NV10 0x37
31 #define SMU11_DRIVER_IF_VERSION_NV12 0x38
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x38
33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x40
34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
35 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
36 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
37 #define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm7150-tlmm.yaml74 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
122 reg = <0x03500000 0x300000>,
123 <0x03900000 0x300000>,
124 <0x03d00000 0x300000>;
127 gpio-ranges = <&tlmm 0 0 120>;
H A Dqcom,sc7180-pinctrl.yaml71 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
123 reg = <0x03500000 0x300000>,
124 <0x03900000 0x300000>,
125 <0x03d00000 0x300000>;
132 gpio-ranges = <&tlmm 0 0 120>;
H A Dqcom,sm8150-pinctrl.yaml72 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
124 reg = <0x03100000 0x300000>,
125 <0x03500000 0x300000>,
126 <0x03900000 0x300000>,
127 <0x03d00000 0x300000>;
130 gpio-ranges = <&tlmm 0 0 176>;
H A Dqcom,sdm630-pinctrl.yaml77 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
141 reg = <0x03100000 0x400000>,
142 <0x03500000 0x400000>,
143 <0x03900000 0x400000>;
147 gpio-ranges = <&tlmm 0 0 114>;
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c32 #define MP0_Public 0x03800000
33 #define MP0_SRAM 0x03900000
34 #define MP1_Public 0x03b00000
35 #define MP1_SRAM 0x03c00004
37 …_FIRMWARE_FLAGS 0x3010028
45 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in smu9_is_smc_ram_running()
66 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
69 0, MP1_C2PMSG_103__CONTENT_MASK); in smu9_wait_for_response()
74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
76 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
[all …]
H A Dsmu10_smumgr.c41 #define MP0_Public 0x03800000
42 #define MP0_SRAM 0x03900000
43 #define MP1_Public 0x03b00000
44 #define MP1_SRAM 0x03c00004
46 #define smnMP1_FIRMWARE_FLAGS 0x3010028
54 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
57 0, MP1_C2PMSG_90__CONTENT_MASK); in smu10_wait_for_response()
59 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
67 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu10_send_msg_to_smc_without_waiting()
69 return 0; in smu10_send_msg_to_smc_without_waiting()
[all …]
H A Dvega20_smumgr.c39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
55 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in vega20_is_smc_ram_running()
75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c94 #define HDMITX_TOP_ADDR_REG 0x0
95 #define HDMITX_TOP_DATA_REG 0x4
96 #define HDMITX_TOP_CTRL_REG 0x8
97 #define HDMITX_TOP_G12A_OFFSET 0x8000
100 #define HDMITX_DWC_ADDR_REG 0x10
101 #define HDMITX_DWC_DATA_REG 0x14
102 #define HDMITX_DWC_CTRL_REG 0x18
105 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
106 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
107 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a.dtsi12 /memreserve/ 0x80000000 0x00010000;
26 #size-cells = <0>;
29 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
38 i-cache-size = <0xC000>;
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]