1d548c217SVabhav Sharma// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d548c217SVabhav Sharma// 3d548c217SVabhav Sharma// Device Tree Include file for Layerscape-LX2160A family SoC. 4d548c217SVabhav Sharma// 566dfd959SWasim Khan// Copyright 2018-2020 NXP 6d548c217SVabhav Sharma 78e9f7797SMichael Walle#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8d548c217SVabhav Sharma#include <dt-bindings/gpio/gpio.h> 9d548c217SVabhav Sharma#include <dt-bindings/interrupt-controller/arm-gic.h> 105363eaaeSYuantian Tang#include <dt-bindings/thermal/thermal.h> 11d548c217SVabhav Sharma 12d548c217SVabhav Sharma/memreserve/ 0x80000000 0x00010000; 13d548c217SVabhav Sharma 14d548c217SVabhav Sharma/ { 15d548c217SVabhav Sharma compatible = "fsl,lx2160a"; 16d548c217SVabhav Sharma interrupt-parent = <&gic>; 17d548c217SVabhav Sharma #address-cells = <2>; 18d548c217SVabhav Sharma #size-cells = <2>; 19d548c217SVabhav Sharma 20dca78e32SBiwen Li aliases { 21dca78e32SBiwen Li rtc1 = &ftm_alarm0; 22dca78e32SBiwen Li }; 23dca78e32SBiwen Li 24d548c217SVabhav Sharma cpus { 25d548c217SVabhav Sharma #address-cells = <1>; 26d548c217SVabhav Sharma #size-cells = <0>; 27d548c217SVabhav Sharma 28d548c217SVabhav Sharma // 8 clusters having 2 Cortex-A72 cores each 295363eaaeSYuantian Tang cpu0: cpu@0 { 30d548c217SVabhav Sharma device_type = "cpu"; 31d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 32d548c217SVabhav Sharma enable-method = "psci"; 33d548c217SVabhav Sharma reg = <0x0>; 348e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35d548c217SVabhav Sharma d-cache-size = <0x8000>; 36d548c217SVabhav Sharma d-cache-line-size = <64>; 37d548c217SVabhav Sharma d-cache-sets = <128>; 38d548c217SVabhav Sharma i-cache-size = <0xC000>; 39d548c217SVabhav Sharma i-cache-line-size = <64>; 40d548c217SVabhav Sharma i-cache-sets = <192>; 41d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 4207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 435363eaaeSYuantian Tang #cooling-cells = <2>; 44d548c217SVabhav Sharma }; 45d548c217SVabhav Sharma 465363eaaeSYuantian Tang cpu1: cpu@1 { 47d548c217SVabhav Sharma device_type = "cpu"; 48d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 49d548c217SVabhav Sharma enable-method = "psci"; 50d548c217SVabhav Sharma reg = <0x1>; 518e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52d548c217SVabhav Sharma d-cache-size = <0x8000>; 53d548c217SVabhav Sharma d-cache-line-size = <64>; 54d548c217SVabhav Sharma d-cache-sets = <128>; 55d548c217SVabhav Sharma i-cache-size = <0xC000>; 56d548c217SVabhav Sharma i-cache-line-size = <64>; 57d548c217SVabhav Sharma i-cache-sets = <192>; 58d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 5907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 605363eaaeSYuantian Tang #cooling-cells = <2>; 61d548c217SVabhav Sharma }; 62d548c217SVabhav Sharma 635363eaaeSYuantian Tang cpu100: cpu@100 { 64d548c217SVabhav Sharma device_type = "cpu"; 65d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 66d548c217SVabhav Sharma enable-method = "psci"; 67d548c217SVabhav Sharma reg = <0x100>; 688e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69d548c217SVabhav Sharma d-cache-size = <0x8000>; 70d548c217SVabhav Sharma d-cache-line-size = <64>; 71d548c217SVabhav Sharma d-cache-sets = <128>; 72d548c217SVabhav Sharma i-cache-size = <0xC000>; 73d548c217SVabhav Sharma i-cache-line-size = <64>; 74d548c217SVabhav Sharma i-cache-sets = <192>; 75d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 7607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 775363eaaeSYuantian Tang #cooling-cells = <2>; 78d548c217SVabhav Sharma }; 79d548c217SVabhav Sharma 805363eaaeSYuantian Tang cpu101: cpu@101 { 81d548c217SVabhav Sharma device_type = "cpu"; 82d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 83d548c217SVabhav Sharma enable-method = "psci"; 84d548c217SVabhav Sharma reg = <0x101>; 858e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86d548c217SVabhav Sharma d-cache-size = <0x8000>; 87d548c217SVabhav Sharma d-cache-line-size = <64>; 88d548c217SVabhav Sharma d-cache-sets = <128>; 89d548c217SVabhav Sharma i-cache-size = <0xC000>; 90d548c217SVabhav Sharma i-cache-line-size = <64>; 91d548c217SVabhav Sharma i-cache-sets = <192>; 92d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 9307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 945363eaaeSYuantian Tang #cooling-cells = <2>; 95d548c217SVabhav Sharma }; 96d548c217SVabhav Sharma 975363eaaeSYuantian Tang cpu200: cpu@200 { 98d548c217SVabhav Sharma device_type = "cpu"; 99d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 100d548c217SVabhav Sharma enable-method = "psci"; 101d548c217SVabhav Sharma reg = <0x200>; 1028e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103d548c217SVabhav Sharma d-cache-size = <0x8000>; 104d548c217SVabhav Sharma d-cache-line-size = <64>; 105d548c217SVabhav Sharma d-cache-sets = <128>; 106d548c217SVabhav Sharma i-cache-size = <0xC000>; 107d548c217SVabhav Sharma i-cache-line-size = <64>; 108d548c217SVabhav Sharma i-cache-sets = <192>; 109d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 11007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1115363eaaeSYuantian Tang #cooling-cells = <2>; 112d548c217SVabhav Sharma }; 113d548c217SVabhav Sharma 1145363eaaeSYuantian Tang cpu201: cpu@201 { 115d548c217SVabhav Sharma device_type = "cpu"; 116d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 117d548c217SVabhav Sharma enable-method = "psci"; 118d548c217SVabhav Sharma reg = <0x201>; 1198e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120d548c217SVabhav Sharma d-cache-size = <0x8000>; 121d548c217SVabhav Sharma d-cache-line-size = <64>; 122d548c217SVabhav Sharma d-cache-sets = <128>; 123d548c217SVabhav Sharma i-cache-size = <0xC000>; 124d548c217SVabhav Sharma i-cache-line-size = <64>; 125d548c217SVabhav Sharma i-cache-sets = <192>; 126d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 12707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1285363eaaeSYuantian Tang #cooling-cells = <2>; 129d548c217SVabhav Sharma }; 130d548c217SVabhav Sharma 1315363eaaeSYuantian Tang cpu300: cpu@300 { 132d548c217SVabhav Sharma device_type = "cpu"; 133d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 134d548c217SVabhav Sharma enable-method = "psci"; 135d548c217SVabhav Sharma reg = <0x300>; 1368e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137d548c217SVabhav Sharma d-cache-size = <0x8000>; 138d548c217SVabhav Sharma d-cache-line-size = <64>; 139d548c217SVabhav Sharma d-cache-sets = <128>; 140d548c217SVabhav Sharma i-cache-size = <0xC000>; 141d548c217SVabhav Sharma i-cache-line-size = <64>; 142d548c217SVabhav Sharma i-cache-sets = <192>; 143d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 14407159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1455363eaaeSYuantian Tang #cooling-cells = <2>; 146d548c217SVabhav Sharma }; 147d548c217SVabhav Sharma 1485363eaaeSYuantian Tang cpu301: cpu@301 { 149d548c217SVabhav Sharma device_type = "cpu"; 150d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 151d548c217SVabhav Sharma enable-method = "psci"; 152d548c217SVabhav Sharma reg = <0x301>; 1538e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154d548c217SVabhav Sharma d-cache-size = <0x8000>; 155d548c217SVabhav Sharma d-cache-line-size = <64>; 156d548c217SVabhav Sharma d-cache-sets = <128>; 157d548c217SVabhav Sharma i-cache-size = <0xC000>; 158d548c217SVabhav Sharma i-cache-line-size = <64>; 159d548c217SVabhav Sharma i-cache-sets = <192>; 160d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 16107159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1625363eaaeSYuantian Tang #cooling-cells = <2>; 163d548c217SVabhav Sharma }; 164d548c217SVabhav Sharma 1655363eaaeSYuantian Tang cpu400: cpu@400 { 166d548c217SVabhav Sharma device_type = "cpu"; 167d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 168d548c217SVabhav Sharma enable-method = "psci"; 169d548c217SVabhav Sharma reg = <0x400>; 1708e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171d548c217SVabhav Sharma d-cache-size = <0x8000>; 172d548c217SVabhav Sharma d-cache-line-size = <64>; 173d548c217SVabhav Sharma d-cache-sets = <128>; 174d548c217SVabhav Sharma i-cache-size = <0xC000>; 175d548c217SVabhav Sharma i-cache-line-size = <64>; 176d548c217SVabhav Sharma i-cache-sets = <192>; 177d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 17807159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1795363eaaeSYuantian Tang #cooling-cells = <2>; 180d548c217SVabhav Sharma }; 181d548c217SVabhav Sharma 1825363eaaeSYuantian Tang cpu401: cpu@401 { 183d548c217SVabhav Sharma device_type = "cpu"; 184d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 185d548c217SVabhav Sharma enable-method = "psci"; 186d548c217SVabhav Sharma reg = <0x401>; 1878e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188d548c217SVabhav Sharma d-cache-size = <0x8000>; 189d548c217SVabhav Sharma d-cache-line-size = <64>; 190d548c217SVabhav Sharma d-cache-sets = <128>; 191d548c217SVabhav Sharma i-cache-size = <0xC000>; 192d548c217SVabhav Sharma i-cache-line-size = <64>; 193d548c217SVabhav Sharma i-cache-sets = <192>; 194d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 19507159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1965363eaaeSYuantian Tang #cooling-cells = <2>; 197d548c217SVabhav Sharma }; 198d548c217SVabhav Sharma 1995363eaaeSYuantian Tang cpu500: cpu@500 { 200d548c217SVabhav Sharma device_type = "cpu"; 201d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 202d548c217SVabhav Sharma enable-method = "psci"; 203d548c217SVabhav Sharma reg = <0x500>; 2048e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205d548c217SVabhav Sharma d-cache-size = <0x8000>; 206d548c217SVabhav Sharma d-cache-line-size = <64>; 207d548c217SVabhav Sharma d-cache-sets = <128>; 208d548c217SVabhav Sharma i-cache-size = <0xC000>; 209d548c217SVabhav Sharma i-cache-line-size = <64>; 210d548c217SVabhav Sharma i-cache-sets = <192>; 211d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 21207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2135363eaaeSYuantian Tang #cooling-cells = <2>; 214d548c217SVabhav Sharma }; 215d548c217SVabhav Sharma 2165363eaaeSYuantian Tang cpu501: cpu@501 { 217d548c217SVabhav Sharma device_type = "cpu"; 218d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 219d548c217SVabhav Sharma enable-method = "psci"; 220d548c217SVabhav Sharma reg = <0x501>; 2218e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222d548c217SVabhav Sharma d-cache-size = <0x8000>; 223d548c217SVabhav Sharma d-cache-line-size = <64>; 224d548c217SVabhav Sharma d-cache-sets = <128>; 225d548c217SVabhav Sharma i-cache-size = <0xC000>; 226d548c217SVabhav Sharma i-cache-line-size = <64>; 227d548c217SVabhav Sharma i-cache-sets = <192>; 228d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 22907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2305363eaaeSYuantian Tang #cooling-cells = <2>; 231d548c217SVabhav Sharma }; 232d548c217SVabhav Sharma 2335363eaaeSYuantian Tang cpu600: cpu@600 { 234d548c217SVabhav Sharma device_type = "cpu"; 235d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 236d548c217SVabhav Sharma enable-method = "psci"; 237d548c217SVabhav Sharma reg = <0x600>; 2388e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239d548c217SVabhav Sharma d-cache-size = <0x8000>; 240d548c217SVabhav Sharma d-cache-line-size = <64>; 241d548c217SVabhav Sharma d-cache-sets = <128>; 242d548c217SVabhav Sharma i-cache-size = <0xC000>; 243d548c217SVabhav Sharma i-cache-line-size = <64>; 244d548c217SVabhav Sharma i-cache-sets = <192>; 245d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 24607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2475363eaaeSYuantian Tang #cooling-cells = <2>; 248d548c217SVabhav Sharma }; 249d548c217SVabhav Sharma 2505363eaaeSYuantian Tang cpu601: cpu@601 { 251d548c217SVabhav Sharma device_type = "cpu"; 252d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 253d548c217SVabhav Sharma enable-method = "psci"; 254d548c217SVabhav Sharma reg = <0x601>; 2558e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256d548c217SVabhav Sharma d-cache-size = <0x8000>; 257d548c217SVabhav Sharma d-cache-line-size = <64>; 258d548c217SVabhav Sharma d-cache-sets = <128>; 259d548c217SVabhav Sharma i-cache-size = <0xC000>; 260d548c217SVabhav Sharma i-cache-line-size = <64>; 261d548c217SVabhav Sharma i-cache-sets = <192>; 262d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 26307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2645363eaaeSYuantian Tang #cooling-cells = <2>; 265d548c217SVabhav Sharma }; 266d548c217SVabhav Sharma 2675363eaaeSYuantian Tang cpu700: cpu@700 { 268d548c217SVabhav Sharma device_type = "cpu"; 269d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 270d548c217SVabhav Sharma enable-method = "psci"; 271d548c217SVabhav Sharma reg = <0x700>; 2728e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273d548c217SVabhav Sharma d-cache-size = <0x8000>; 274d548c217SVabhav Sharma d-cache-line-size = <64>; 275d548c217SVabhav Sharma d-cache-sets = <128>; 276d548c217SVabhav Sharma i-cache-size = <0xC000>; 277d548c217SVabhav Sharma i-cache-line-size = <64>; 278d548c217SVabhav Sharma i-cache-sets = <192>; 279d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 28007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2815363eaaeSYuantian Tang #cooling-cells = <2>; 282d548c217SVabhav Sharma }; 283d548c217SVabhav Sharma 2845363eaaeSYuantian Tang cpu701: cpu@701 { 285d548c217SVabhav Sharma device_type = "cpu"; 286d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 287d548c217SVabhav Sharma enable-method = "psci"; 288d548c217SVabhav Sharma reg = <0x701>; 2898e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290d548c217SVabhav Sharma d-cache-size = <0x8000>; 291d548c217SVabhav Sharma d-cache-line-size = <64>; 292d548c217SVabhav Sharma d-cache-sets = <128>; 293d548c217SVabhav Sharma i-cache-size = <0xC000>; 294d548c217SVabhav Sharma i-cache-line-size = <64>; 295d548c217SVabhav Sharma i-cache-sets = <192>; 296d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 29707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2985363eaaeSYuantian Tang #cooling-cells = <2>; 299d548c217SVabhav Sharma }; 300d548c217SVabhav Sharma 301d548c217SVabhav Sharma cluster0_l2: l2-cache0 { 302d548c217SVabhav Sharma compatible = "cache"; 3033b450831SPierre Gondois cache-unified; 304d548c217SVabhav Sharma cache-size = <0x100000>; 305d548c217SVabhav Sharma cache-line-size = <64>; 306d548c217SVabhav Sharma cache-sets = <1024>; 307d548c217SVabhav Sharma cache-level = <2>; 308d548c217SVabhav Sharma }; 309d548c217SVabhav Sharma 310d548c217SVabhav Sharma cluster1_l2: l2-cache1 { 311d548c217SVabhav Sharma compatible = "cache"; 3123b450831SPierre Gondois cache-unified; 313d548c217SVabhav Sharma cache-size = <0x100000>; 314d548c217SVabhav Sharma cache-line-size = <64>; 315d548c217SVabhav Sharma cache-sets = <1024>; 316d548c217SVabhav Sharma cache-level = <2>; 317d548c217SVabhav Sharma }; 318d548c217SVabhav Sharma 319d548c217SVabhav Sharma cluster2_l2: l2-cache2 { 320d548c217SVabhav Sharma compatible = "cache"; 3213b450831SPierre Gondois cache-unified; 322d548c217SVabhav Sharma cache-size = <0x100000>; 323d548c217SVabhav Sharma cache-line-size = <64>; 324d548c217SVabhav Sharma cache-sets = <1024>; 325d548c217SVabhav Sharma cache-level = <2>; 326d548c217SVabhav Sharma }; 327d548c217SVabhav Sharma 328d548c217SVabhav Sharma cluster3_l2: l2-cache3 { 329d548c217SVabhav Sharma compatible = "cache"; 3303b450831SPierre Gondois cache-unified; 331d548c217SVabhav Sharma cache-size = <0x100000>; 332d548c217SVabhav Sharma cache-line-size = <64>; 333d548c217SVabhav Sharma cache-sets = <1024>; 334d548c217SVabhav Sharma cache-level = <2>; 335d548c217SVabhav Sharma }; 336d548c217SVabhav Sharma 337d548c217SVabhav Sharma cluster4_l2: l2-cache4 { 338d548c217SVabhav Sharma compatible = "cache"; 3393b450831SPierre Gondois cache-unified; 340d548c217SVabhav Sharma cache-size = <0x100000>; 341d548c217SVabhav Sharma cache-line-size = <64>; 342d548c217SVabhav Sharma cache-sets = <1024>; 343d548c217SVabhav Sharma cache-level = <2>; 344d548c217SVabhav Sharma }; 345d548c217SVabhav Sharma 346d548c217SVabhav Sharma cluster5_l2: l2-cache5 { 347d548c217SVabhav Sharma compatible = "cache"; 3483b450831SPierre Gondois cache-unified; 349d548c217SVabhav Sharma cache-size = <0x100000>; 350d548c217SVabhav Sharma cache-line-size = <64>; 351d548c217SVabhav Sharma cache-sets = <1024>; 352d548c217SVabhav Sharma cache-level = <2>; 353d548c217SVabhav Sharma }; 354d548c217SVabhav Sharma 355d548c217SVabhav Sharma cluster6_l2: l2-cache6 { 356d548c217SVabhav Sharma compatible = "cache"; 3573b450831SPierre Gondois cache-unified; 358d548c217SVabhav Sharma cache-size = <0x100000>; 359d548c217SVabhav Sharma cache-line-size = <64>; 360d548c217SVabhav Sharma cache-sets = <1024>; 361d548c217SVabhav Sharma cache-level = <2>; 362d548c217SVabhav Sharma }; 363d548c217SVabhav Sharma 364d548c217SVabhav Sharma cluster7_l2: l2-cache7 { 365d548c217SVabhav Sharma compatible = "cache"; 3663b450831SPierre Gondois cache-unified; 367d548c217SVabhav Sharma cache-size = <0x100000>; 368d548c217SVabhav Sharma cache-line-size = <64>; 369d548c217SVabhav Sharma cache-sets = <1024>; 370d548c217SVabhav Sharma cache-level = <2>; 371d548c217SVabhav Sharma }; 37200c5ce8aSRan Wang 37307159f67SRan Wang cpu_pw15: cpu-pw15 { 37400c5ce8aSRan Wang compatible = "arm,idle-state"; 37507159f67SRan Wang idle-state-name = "PW15"; 37600c5ce8aSRan Wang arm,psci-suspend-param = <0x0>; 37700c5ce8aSRan Wang entry-latency-us = <2000>; 37800c5ce8aSRan Wang exit-latency-us = <2000>; 37900c5ce8aSRan Wang min-residency-us = <6000>; 38000c5ce8aSRan Wang }; 381d548c217SVabhav Sharma }; 382d548c217SVabhav Sharma 383d548c217SVabhav Sharma gic: interrupt-controller@6000000 { 384d548c217SVabhav Sharma compatible = "arm,gic-v3"; 385d548c217SVabhav Sharma reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 386d548c217SVabhav Sharma <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 387d548c217SVabhav Sharma // SGI_base) 388d548c217SVabhav Sharma <0x0 0x0c0c0000 0 0x2000>, // GICC 389d548c217SVabhav Sharma <0x0 0x0c0d0000 0 0x1000>, // GICH 390d548c217SVabhav Sharma <0x0 0x0c0e0000 0 0x20000>; // GICV 391d548c217SVabhav Sharma #interrupt-cells = <3>; 392d548c217SVabhav Sharma #address-cells = <2>; 393d548c217SVabhav Sharma #size-cells = <2>; 394d548c217SVabhav Sharma ranges; 395d548c217SVabhav Sharma interrupt-controller; 396d548c217SVabhav Sharma interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 397d548c217SVabhav Sharma 398*04b09f6eSRob Herring its: msi-controller@6020000 { 399d548c217SVabhav Sharma compatible = "arm,gic-v3-its"; 400d548c217SVabhav Sharma msi-controller; 401d548c217SVabhav Sharma reg = <0x0 0x6020000 0 0x20000>; 402d548c217SVabhav Sharma }; 403d548c217SVabhav Sharma }; 404d548c217SVabhav Sharma 405d548c217SVabhav Sharma timer { 406d548c217SVabhav Sharma compatible = "arm,armv8-timer"; 407d548c217SVabhav Sharma interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 408d548c217SVabhav Sharma <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 409d548c217SVabhav Sharma <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 410d548c217SVabhav Sharma <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 411d548c217SVabhav Sharma }; 412d548c217SVabhav Sharma 413d548c217SVabhav Sharma pmu { 414d548c217SVabhav Sharma compatible = "arm,cortex-a72-pmu"; 415d548c217SVabhav Sharma interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 416d548c217SVabhav Sharma }; 417d548c217SVabhav Sharma 418d548c217SVabhav Sharma psci { 419d548c217SVabhav Sharma compatible = "arm,psci-0.2"; 420d548c217SVabhav Sharma method = "smc"; 421d548c217SVabhav Sharma }; 422d548c217SVabhav Sharma 423d548c217SVabhav Sharma memory@80000000 { 424d548c217SVabhav Sharma // DRAM space - 1, size : 2 GB DRAM 425d548c217SVabhav Sharma device_type = "memory"; 426d548c217SVabhav Sharma reg = <0x00000000 0x80000000 0 0x80000000>; 427d548c217SVabhav Sharma }; 428d548c217SVabhav Sharma 429d548c217SVabhav Sharma ddr1: memory-controller@1080000 { 430d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 431d548c217SVabhav Sharma reg = <0x0 0x1080000 0x0 0x1000>; 432d548c217SVabhav Sharma interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 433d548c217SVabhav Sharma little-endian; 434d548c217SVabhav Sharma }; 435d548c217SVabhav Sharma 436d548c217SVabhav Sharma ddr2: memory-controller@1090000 { 437d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 438d548c217SVabhav Sharma reg = <0x0 0x1090000 0x0 0x1000>; 439d548c217SVabhav Sharma interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 440d548c217SVabhav Sharma little-endian; 441d548c217SVabhav Sharma }; 442d548c217SVabhav Sharma 443d548c217SVabhav Sharma // One clock unit-sysclk node which bootloader require during DT fix-up 444d548c217SVabhav Sharma sysclk: sysclk { 445d548c217SVabhav Sharma compatible = "fixed-clock"; 446d548c217SVabhav Sharma #clock-cells = <0>; 447d548c217SVabhav Sharma clock-frequency = <100000000>; // fixed up by bootloader 448d548c217SVabhav Sharma clock-output-names = "sysclk"; 449d548c217SVabhav Sharma }; 450d548c217SVabhav Sharma 4515363eaaeSYuantian Tang thermal-zones { 452ac082ea8SYuantian Tang cluster6-7 { 4535363eaaeSYuantian Tang polling-delay-passive = <1000>; 4545363eaaeSYuantian Tang polling-delay = <5000>; 4555363eaaeSYuantian Tang thermal-sensors = <&tmu 0>; 4565363eaaeSYuantian Tang 4575363eaaeSYuantian Tang trips { 458ac082ea8SYuantian Tang cluster6_7_alert: cluster6-7-alert { 4595363eaaeSYuantian Tang temperature = <85000>; 4605363eaaeSYuantian Tang hysteresis = <2000>; 4615363eaaeSYuantian Tang type = "passive"; 4625363eaaeSYuantian Tang }; 4635363eaaeSYuantian Tang 464ac082ea8SYuantian Tang cluster6_7_crit: cluster6-7-crit { 4655363eaaeSYuantian Tang temperature = <95000>; 4665363eaaeSYuantian Tang hysteresis = <2000>; 4675363eaaeSYuantian Tang type = "critical"; 4685363eaaeSYuantian Tang }; 4695363eaaeSYuantian Tang }; 4705363eaaeSYuantian Tang 4715363eaaeSYuantian Tang cooling-maps { 4725363eaaeSYuantian Tang map0 { 473ac082ea8SYuantian Tang trip = <&cluster6_7_alert>; 4745363eaaeSYuantian Tang cooling-device = 4755363eaaeSYuantian Tang <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765363eaaeSYuantian Tang <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775363eaaeSYuantian Tang <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785363eaaeSYuantian Tang <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795363eaaeSYuantian Tang <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805363eaaeSYuantian Tang <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815363eaaeSYuantian Tang <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4825363eaaeSYuantian Tang <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4835363eaaeSYuantian Tang <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4845363eaaeSYuantian Tang <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4855363eaaeSYuantian Tang <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865363eaaeSYuantian Tang <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4875363eaaeSYuantian Tang <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4885363eaaeSYuantian Tang <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4895363eaaeSYuantian Tang <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905363eaaeSYuantian Tang <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4915363eaaeSYuantian Tang }; 4925363eaaeSYuantian Tang }; 4935363eaaeSYuantian Tang }; 494ac082ea8SYuantian Tang 495ac082ea8SYuantian Tang ddr-cluster5 { 496ac082ea8SYuantian Tang polling-delay-passive = <1000>; 497ac082ea8SYuantian Tang polling-delay = <5000>; 498ac082ea8SYuantian Tang thermal-sensors = <&tmu 1>; 499ac082ea8SYuantian Tang 500ac082ea8SYuantian Tang trips { 501ac082ea8SYuantian Tang ddr-cluster5-alert { 502ac082ea8SYuantian Tang temperature = <85000>; 503ac082ea8SYuantian Tang hysteresis = <2000>; 504ac082ea8SYuantian Tang type = "passive"; 505ac082ea8SYuantian Tang }; 506ac082ea8SYuantian Tang 507ac082ea8SYuantian Tang ddr-cluster5-crit { 508ac082ea8SYuantian Tang temperature = <95000>; 509ac082ea8SYuantian Tang hysteresis = <2000>; 510ac082ea8SYuantian Tang type = "critical"; 511ac082ea8SYuantian Tang }; 512ac082ea8SYuantian Tang }; 513ac082ea8SYuantian Tang }; 514ac082ea8SYuantian Tang 515ac082ea8SYuantian Tang wriop { 516ac082ea8SYuantian Tang polling-delay-passive = <1000>; 517ac082ea8SYuantian Tang polling-delay = <5000>; 518ac082ea8SYuantian Tang thermal-sensors = <&tmu 2>; 519ac082ea8SYuantian Tang 520ac082ea8SYuantian Tang trips { 521ac082ea8SYuantian Tang wriop-alert { 522ac082ea8SYuantian Tang temperature = <85000>; 523ac082ea8SYuantian Tang hysteresis = <2000>; 524ac082ea8SYuantian Tang type = "passive"; 525ac082ea8SYuantian Tang }; 526ac082ea8SYuantian Tang 527ac082ea8SYuantian Tang wriop-crit { 528ac082ea8SYuantian Tang temperature = <95000>; 529ac082ea8SYuantian Tang hysteresis = <2000>; 530ac082ea8SYuantian Tang type = "critical"; 531ac082ea8SYuantian Tang }; 532ac082ea8SYuantian Tang }; 533ac082ea8SYuantian Tang }; 534ac082ea8SYuantian Tang 535ac082ea8SYuantian Tang dce-qbman-hsio2 { 536ac082ea8SYuantian Tang polling-delay-passive = <1000>; 537ac082ea8SYuantian Tang polling-delay = <5000>; 538ac082ea8SYuantian Tang thermal-sensors = <&tmu 3>; 539ac082ea8SYuantian Tang 540ac082ea8SYuantian Tang trips { 541ac082ea8SYuantian Tang dce-qbman-alert { 542ac082ea8SYuantian Tang temperature = <85000>; 543ac082ea8SYuantian Tang hysteresis = <2000>; 544ac082ea8SYuantian Tang type = "passive"; 545ac082ea8SYuantian Tang }; 546ac082ea8SYuantian Tang 547ac082ea8SYuantian Tang dce-qbman-crit { 548ac082ea8SYuantian Tang temperature = <95000>; 549ac082ea8SYuantian Tang hysteresis = <2000>; 550ac082ea8SYuantian Tang type = "critical"; 551ac082ea8SYuantian Tang }; 552ac082ea8SYuantian Tang }; 553ac082ea8SYuantian Tang }; 554ac082ea8SYuantian Tang 555ac082ea8SYuantian Tang ccn-dpaa-tbu { 556ac082ea8SYuantian Tang polling-delay-passive = <1000>; 557ac082ea8SYuantian Tang polling-delay = <5000>; 558ac082ea8SYuantian Tang thermal-sensors = <&tmu 4>; 559ac082ea8SYuantian Tang 560ac082ea8SYuantian Tang trips { 561ac082ea8SYuantian Tang ccn-dpaa-alert { 562ac082ea8SYuantian Tang temperature = <85000>; 563ac082ea8SYuantian Tang hysteresis = <2000>; 564ac082ea8SYuantian Tang type = "passive"; 565ac082ea8SYuantian Tang }; 566ac082ea8SYuantian Tang 567ac082ea8SYuantian Tang ccn-dpaa-crit { 568ac082ea8SYuantian Tang temperature = <95000>; 569ac082ea8SYuantian Tang hysteresis = <2000>; 570ac082ea8SYuantian Tang type = "critical"; 571ac082ea8SYuantian Tang }; 572ac082ea8SYuantian Tang }; 573ac082ea8SYuantian Tang }; 574ac082ea8SYuantian Tang 575ac082ea8SYuantian Tang cluster4-hsio3 { 576ac082ea8SYuantian Tang polling-delay-passive = <1000>; 577ac082ea8SYuantian Tang polling-delay = <5000>; 578ac082ea8SYuantian Tang thermal-sensors = <&tmu 5>; 579ac082ea8SYuantian Tang 580ac082ea8SYuantian Tang trips { 581ac082ea8SYuantian Tang clust4-hsio3-alert { 582ac082ea8SYuantian Tang temperature = <85000>; 583ac082ea8SYuantian Tang hysteresis = <2000>; 584ac082ea8SYuantian Tang type = "passive"; 585ac082ea8SYuantian Tang }; 586ac082ea8SYuantian Tang 587ac082ea8SYuantian Tang clust4-hsio3-crit { 588ac082ea8SYuantian Tang temperature = <95000>; 589ac082ea8SYuantian Tang hysteresis = <2000>; 590ac082ea8SYuantian Tang type = "critical"; 591ac082ea8SYuantian Tang }; 592ac082ea8SYuantian Tang }; 593ac082ea8SYuantian Tang }; 594ac082ea8SYuantian Tang 595ac082ea8SYuantian Tang cluster2-3 { 596ac082ea8SYuantian Tang polling-delay-passive = <1000>; 597ac082ea8SYuantian Tang polling-delay = <5000>; 598ac082ea8SYuantian Tang thermal-sensors = <&tmu 6>; 599ac082ea8SYuantian Tang 600ac082ea8SYuantian Tang trips { 601ac082ea8SYuantian Tang cluster2-3-alert { 602ac082ea8SYuantian Tang temperature = <85000>; 603ac082ea8SYuantian Tang hysteresis = <2000>; 604ac082ea8SYuantian Tang type = "passive"; 605ac082ea8SYuantian Tang }; 606ac082ea8SYuantian Tang 607ac082ea8SYuantian Tang cluster2-3-crit { 608ac082ea8SYuantian Tang temperature = <95000>; 609ac082ea8SYuantian Tang hysteresis = <2000>; 610ac082ea8SYuantian Tang type = "critical"; 611ac082ea8SYuantian Tang }; 612ac082ea8SYuantian Tang }; 613ac082ea8SYuantian Tang }; 6145363eaaeSYuantian Tang }; 6155363eaaeSYuantian Tang 616d548c217SVabhav Sharma soc { 617d548c217SVabhav Sharma compatible = "simple-bus"; 618d548c217SVabhav Sharma #address-cells = <2>; 619d548c217SVabhav Sharma #size-cells = <2>; 620d548c217SVabhav Sharma ranges; 6210154878dSIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 622d548c217SVabhav Sharma 6233cbe93a1SIoana Ciornei serdes_1: phy@1ea0000 { 6243cbe93a1SIoana Ciornei compatible = "fsl,lynx-28g"; 6253cbe93a1SIoana Ciornei reg = <0x0 0x1ea0000 0x0 0x1e30>; 6263cbe93a1SIoana Ciornei #phy-cells = <1>; 6273cbe93a1SIoana Ciornei }; 6283cbe93a1SIoana Ciornei 629d548c217SVabhav Sharma crypto: crypto@8000000 { 630d548c217SVabhav Sharma compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 631d548c217SVabhav Sharma fsl,sec-era = <10>; 632d548c217SVabhav Sharma #address-cells = <1>; 633d548c217SVabhav Sharma #size-cells = <1>; 634d548c217SVabhav Sharma ranges = <0x0 0x00 0x8000000 0x100000>; 635d548c217SVabhav Sharma reg = <0x00 0x8000000 0x0 0x100000>; 636d548c217SVabhav Sharma interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 637d548c217SVabhav Sharma dma-coherent; 638d548c217SVabhav Sharma status = "disabled"; 639d548c217SVabhav Sharma 640d548c217SVabhav Sharma sec_jr0: jr@10000 { 641d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 642d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 643d548c217SVabhav Sharma reg = <0x10000 0x10000>; 644d548c217SVabhav Sharma interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 645d548c217SVabhav Sharma }; 646d548c217SVabhav Sharma 647d548c217SVabhav Sharma sec_jr1: jr@20000 { 648d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 649d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 650d548c217SVabhav Sharma reg = <0x20000 0x10000>; 651d548c217SVabhav Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 652d548c217SVabhav Sharma }; 653d548c217SVabhav Sharma 654d548c217SVabhav Sharma sec_jr2: jr@30000 { 655d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 656d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 657d548c217SVabhav Sharma reg = <0x30000 0x10000>; 658d548c217SVabhav Sharma interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 659d548c217SVabhav Sharma }; 660d548c217SVabhav Sharma 661d548c217SVabhav Sharma sec_jr3: jr@40000 { 662d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 663d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 664d548c217SVabhav Sharma reg = <0x40000 0x10000>; 665d548c217SVabhav Sharma interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 666d548c217SVabhav Sharma }; 667d548c217SVabhav Sharma }; 668d548c217SVabhav Sharma 669d548c217SVabhav Sharma clockgen: clock-controller@1300000 { 670d548c217SVabhav Sharma compatible = "fsl,lx2160a-clockgen"; 671d548c217SVabhav Sharma reg = <0 0x1300000 0 0xa0000>; 672d548c217SVabhav Sharma #clock-cells = <2>; 673d548c217SVabhav Sharma clocks = <&sysclk>; 674d548c217SVabhav Sharma }; 675d548c217SVabhav Sharma 676d548c217SVabhav Sharma dcfg: syscon@1e00000 { 677d548c217SVabhav Sharma compatible = "fsl,lx2160a-dcfg", "syscon"; 678d548c217SVabhav Sharma reg = <0x0 0x1e00000 0x0 0x10000>; 679d548c217SVabhav Sharma little-endian; 680d548c217SVabhav Sharma }; 681d548c217SVabhav Sharma 682e0f6d9ebSSean Anderson sfp: efuse@1e80000 { 683e0f6d9ebSSean Anderson compatible = "fsl,ls1028a-sfp"; 684e0f6d9ebSSean Anderson reg = <0x0 0x1e80000 0x0 0x10000>; 685e0f6d9ebSSean Anderson clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 686e0f6d9ebSSean Anderson QORIQ_CLK_PLL_DIV(4)>; 687e0f6d9ebSSean Anderson clock-names = "sfp"; 688e0f6d9ebSSean Anderson }; 689e0f6d9ebSSean Anderson 690332b6a79SBiwen Li isc: syscon@1f70000 { 691332b6a79SBiwen Li compatible = "fsl,lx2160a-isc", "syscon"; 692332b6a79SBiwen Li reg = <0x0 0x1f70000 0x0 0x10000>; 693332b6a79SBiwen Li little-endian; 694332b6a79SBiwen Li #address-cells = <1>; 695332b6a79SBiwen Li #size-cells = <1>; 696332b6a79SBiwen Li ranges = <0x0 0x0 0x1f70000 0x10000>; 697332b6a79SBiwen Li 698332b6a79SBiwen Li extirq: interrupt-controller@14 { 699332b6a79SBiwen Li compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 700332b6a79SBiwen Li #interrupt-cells = <2>; 701332b6a79SBiwen Li #address-cells = <0>; 702332b6a79SBiwen Li interrupt-controller; 703332b6a79SBiwen Li reg = <0x14 4>; 704332b6a79SBiwen Li interrupt-map = 7051447c635SVladimir Oltean <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7061447c635SVladimir Oltean <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7071447c635SVladimir Oltean <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7081447c635SVladimir Oltean <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7091447c635SVladimir Oltean <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7101447c635SVladimir Oltean <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7111447c635SVladimir Oltean <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7121447c635SVladimir Oltean <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7131447c635SVladimir Oltean <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7141447c635SVladimir Oltean <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 7151447c635SVladimir Oltean <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 7161447c635SVladimir Oltean <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 717339c8beaSMichael Walle interrupt-map-mask = <0xf 0x0>; 718332b6a79SBiwen Li }; 719332b6a79SBiwen Li }; 720332b6a79SBiwen Li 7215363eaaeSYuantian Tang tmu: tmu@1f80000 { 7225363eaaeSYuantian Tang compatible = "fsl,qoriq-tmu"; 7235363eaaeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 7245363eaaeSYuantian Tang interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 7255363eaaeSYuantian Tang fsl,tmu-range = <0x800000e6 0x8001017d>; 7265363eaaeSYuantian Tang fsl,tmu-calibration = 7275363eaaeSYuantian Tang /* Calibration data group 1 */ 7285363eaaeSYuantian Tang <0x00000000 0x00000035 7295363eaaeSYuantian Tang /* Calibration data group 2 */ 730ac082ea8SYuantian Tang 0x00000001 0x00000154>; 7315363eaaeSYuantian Tang little-endian; 7325363eaaeSYuantian Tang #thermal-sensor-cells = <1>; 7335363eaaeSYuantian Tang }; 7345363eaaeSYuantian Tang 735d548c217SVabhav Sharma i2c0: i2c@2000000 { 736d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 737d548c217SVabhav Sharma #address-cells = <1>; 738d548c217SVabhav Sharma #size-cells = <0>; 739d548c217SVabhav Sharma reg = <0x0 0x2000000 0x0 0x10000>; 740d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 741d548c217SVabhav Sharma clock-names = "i2c"; 7428e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7438e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 744849e087bSZhang Ying-22455 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 745d548c217SVabhav Sharma status = "disabled"; 746d548c217SVabhav Sharma }; 747d548c217SVabhav Sharma 748d548c217SVabhav Sharma i2c1: i2c@2010000 { 749d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 750d548c217SVabhav Sharma #address-cells = <1>; 751d548c217SVabhav Sharma #size-cells = <0>; 752d548c217SVabhav Sharma reg = <0x0 0x2010000 0x0 0x10000>; 753d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 754d548c217SVabhav Sharma clock-names = "i2c"; 7558e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7568e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 757d548c217SVabhav Sharma status = "disabled"; 758d548c217SVabhav Sharma }; 759d548c217SVabhav Sharma 760d548c217SVabhav Sharma i2c2: i2c@2020000 { 761d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 762d548c217SVabhav Sharma #address-cells = <1>; 763d548c217SVabhav Sharma #size-cells = <0>; 764d548c217SVabhav Sharma reg = <0x0 0x2020000 0x0 0x10000>; 765d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 766d548c217SVabhav Sharma clock-names = "i2c"; 7678e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7688e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 769d548c217SVabhav Sharma status = "disabled"; 770d548c217SVabhav Sharma }; 771d548c217SVabhav Sharma 772d548c217SVabhav Sharma i2c3: i2c@2030000 { 773d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 774d548c217SVabhav Sharma #address-cells = <1>; 775d548c217SVabhav Sharma #size-cells = <0>; 776d548c217SVabhav Sharma reg = <0x0 0x2030000 0x0 0x10000>; 777d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 778d548c217SVabhav Sharma clock-names = "i2c"; 7798e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7808e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 781d548c217SVabhav Sharma status = "disabled"; 782d548c217SVabhav Sharma }; 783d548c217SVabhav Sharma 784d548c217SVabhav Sharma i2c4: i2c@2040000 { 785d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 786d548c217SVabhav Sharma #address-cells = <1>; 787d548c217SVabhav Sharma #size-cells = <0>; 788d548c217SVabhav Sharma reg = <0x0 0x2040000 0x0 0x10000>; 789d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 790d548c217SVabhav Sharma clock-names = "i2c"; 7918e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7928e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 793849e087bSZhang Ying-22455 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 794d548c217SVabhav Sharma status = "disabled"; 795d548c217SVabhav Sharma }; 796d548c217SVabhav Sharma 797d548c217SVabhav Sharma i2c5: i2c@2050000 { 798d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 799d548c217SVabhav Sharma #address-cells = <1>; 800d548c217SVabhav Sharma #size-cells = <0>; 801d548c217SVabhav Sharma reg = <0x0 0x2050000 0x0 0x10000>; 802d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 803d548c217SVabhav Sharma clock-names = "i2c"; 8048e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8058e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 806d548c217SVabhav Sharma status = "disabled"; 807d548c217SVabhav Sharma }; 808d548c217SVabhav Sharma 809d548c217SVabhav Sharma i2c6: i2c@2060000 { 810d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 811d548c217SVabhav Sharma #address-cells = <1>; 812d548c217SVabhav Sharma #size-cells = <0>; 813d548c217SVabhav Sharma reg = <0x0 0x2060000 0x0 0x10000>; 814d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 815d548c217SVabhav Sharma clock-names = "i2c"; 8168e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8178e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 818d548c217SVabhav Sharma status = "disabled"; 819d548c217SVabhav Sharma }; 820d548c217SVabhav Sharma 821d548c217SVabhav Sharma i2c7: i2c@2070000 { 822d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 823d548c217SVabhav Sharma #address-cells = <1>; 824d548c217SVabhav Sharma #size-cells = <0>; 825d548c217SVabhav Sharma reg = <0x0 0x2070000 0x0 0x10000>; 826d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 827d548c217SVabhav Sharma clock-names = "i2c"; 8288e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8298e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 830d548c217SVabhav Sharma status = "disabled"; 831d548c217SVabhav Sharma }; 832d548c217SVabhav Sharma 8331ffeef4eSYogesh Narayan Gaur fspi: spi@20c0000 { 8341ffeef4eSYogesh Narayan Gaur compatible = "nxp,lx2160a-fspi"; 8351ffeef4eSYogesh Narayan Gaur #address-cells = <1>; 8361ffeef4eSYogesh Narayan Gaur #size-cells = <0>; 8371ffeef4eSYogesh Narayan Gaur reg = <0x0 0x20c0000 0x0 0x10000>, 8381ffeef4eSYogesh Narayan Gaur <0x0 0x20000000 0x0 0x10000000>; 8391ffeef4eSYogesh Narayan Gaur reg-names = "fspi_base", "fspi_mmap"; 8401ffeef4eSYogesh Narayan Gaur interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8418e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8428e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>, 8438e9f7797SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 8448e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 8451ffeef4eSYogesh Narayan Gaur clock-names = "fspi_en", "fspi"; 8461ffeef4eSYogesh Narayan Gaur status = "disabled"; 8471ffeef4eSYogesh Narayan Gaur }; 8481ffeef4eSYogesh Narayan Gaur 84983ebd4a5SChuanhua Han dspi0: spi@2100000 { 85083ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 85183ebd4a5SChuanhua Han #address-cells = <1>; 85283ebd4a5SChuanhua Han #size-cells = <0>; 85383ebd4a5SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 85483ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 8558e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8568e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 85783ebd4a5SChuanhua Han clock-names = "dspi"; 85883ebd4a5SChuanhua Han spi-num-chipselects = <5>; 85983ebd4a5SChuanhua Han bus-num = <0>; 86083ebd4a5SChuanhua Han status = "disabled"; 86183ebd4a5SChuanhua Han }; 86283ebd4a5SChuanhua Han 86383ebd4a5SChuanhua Han dspi1: spi@2110000 { 86483ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 86583ebd4a5SChuanhua Han #address-cells = <1>; 86683ebd4a5SChuanhua Han #size-cells = <0>; 86783ebd4a5SChuanhua Han reg = <0x0 0x2110000 0x0 0x10000>; 86883ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 8698e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8708e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 87183ebd4a5SChuanhua Han clock-names = "dspi"; 87283ebd4a5SChuanhua Han spi-num-chipselects = <5>; 87383ebd4a5SChuanhua Han bus-num = <1>; 87483ebd4a5SChuanhua Han status = "disabled"; 87583ebd4a5SChuanhua Han }; 87683ebd4a5SChuanhua Han 87783ebd4a5SChuanhua Han dspi2: spi@2120000 { 87883ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 87983ebd4a5SChuanhua Han #address-cells = <1>; 88083ebd4a5SChuanhua Han #size-cells = <0>; 88183ebd4a5SChuanhua Han reg = <0x0 0x2120000 0x0 0x10000>; 88283ebd4a5SChuanhua Han interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 8838e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8848e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 88583ebd4a5SChuanhua Han clock-names = "dspi"; 88683ebd4a5SChuanhua Han spi-num-chipselects = <5>; 88783ebd4a5SChuanhua Han bus-num = <2>; 88883ebd4a5SChuanhua Han status = "disabled"; 88983ebd4a5SChuanhua Han }; 89083ebd4a5SChuanhua Han 891d548c217SVabhav Sharma esdhc0: esdhc@2140000 { 892d548c217SVabhav Sharma compatible = "fsl,esdhc"; 893d548c217SVabhav Sharma reg = <0x0 0x2140000 0x0 0x10000>; 894d548c217SVabhav Sharma interrupts = <0 28 0x4>; /* Level high type */ 8958e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8968e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 89762b4359cSRussell King dma-coherent; 898d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 899d548c217SVabhav Sharma sdhci,auto-cmd12; 900d548c217SVabhav Sharma little-endian; 901d548c217SVabhav Sharma bus-width = <4>; 902d548c217SVabhav Sharma status = "disabled"; 903d548c217SVabhav Sharma }; 904d548c217SVabhav Sharma 905d548c217SVabhav Sharma esdhc1: esdhc@2150000 { 906d548c217SVabhav Sharma compatible = "fsl,esdhc"; 907d548c217SVabhav Sharma reg = <0x0 0x2150000 0x0 0x10000>; 908d548c217SVabhav Sharma interrupts = <0 63 0x4>; /* Level high type */ 9098e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 9108e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 91162b4359cSRussell King dma-coherent; 912d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 913d548c217SVabhav Sharma sdhci,auto-cmd12; 914d548c217SVabhav Sharma broken-cd; 915d548c217SVabhav Sharma little-endian; 916d548c217SVabhav Sharma bus-width = <4>; 917d548c217SVabhav Sharma status = "disabled"; 918d548c217SVabhav Sharma }; 919d548c217SVabhav Sharma 920930a0968SKuldeep Singh can0: can@2180000 { 921930a0968SKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 922930a0968SKuldeep Singh reg = <0x0 0x2180000 0x0 0x10000>; 923930a0968SKuldeep Singh interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 924930a0968SKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 925930a0968SKuldeep Singh QORIQ_CLK_PLL_DIV(8)>, 926930a0968SKuldeep Singh <&clockgen QORIQ_CLK_SYSCLK 0>; 927930a0968SKuldeep Singh clock-names = "ipg", "per"; 9287cbeeb05SKuldeep Singh fsl,clk-source = /bits/ 8 <0>; 929930a0968SKuldeep Singh status = "disabled"; 930930a0968SKuldeep Singh }; 931930a0968SKuldeep Singh 932930a0968SKuldeep Singh can1: can@2190000 { 933930a0968SKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 934930a0968SKuldeep Singh reg = <0x0 0x2190000 0x0 0x10000>; 935930a0968SKuldeep Singh interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 936930a0968SKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 937930a0968SKuldeep Singh QORIQ_CLK_PLL_DIV(8)>, 938930a0968SKuldeep Singh <&clockgen QORIQ_CLK_SYSCLK 0>; 939930a0968SKuldeep Singh clock-names = "ipg", "per"; 9407cbeeb05SKuldeep Singh fsl,clk-source = /bits/ 8 <0>; 941930a0968SKuldeep Singh status = "disabled"; 942930a0968SKuldeep Singh }; 943930a0968SKuldeep Singh 944d548c217SVabhav Sharma uart0: serial@21c0000 { 945d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 946d548c217SVabhav Sharma reg = <0x0 0x21c0000 0x0 0x1000>; 947d548c217SVabhav Sharma interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 948d548c217SVabhav Sharma current-speed = <115200>; 949d548c217SVabhav Sharma status = "disabled"; 950d548c217SVabhav Sharma }; 951d548c217SVabhav Sharma 952d548c217SVabhav Sharma uart1: serial@21d0000 { 953d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 954d548c217SVabhav Sharma reg = <0x0 0x21d0000 0x0 0x1000>; 955d548c217SVabhav Sharma interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 956d548c217SVabhav Sharma current-speed = <115200>; 957d548c217SVabhav Sharma status = "disabled"; 958d548c217SVabhav Sharma }; 959d548c217SVabhav Sharma 960d548c217SVabhav Sharma uart2: serial@21e0000 { 961d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 962d548c217SVabhav Sharma reg = <0x0 0x21e0000 0x0 0x1000>; 963d548c217SVabhav Sharma interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 964d548c217SVabhav Sharma current-speed = <115200>; 965d548c217SVabhav Sharma status = "disabled"; 966d548c217SVabhav Sharma }; 967d548c217SVabhav Sharma 968d548c217SVabhav Sharma uart3: serial@21f0000 { 969d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 970d548c217SVabhav Sharma reg = <0x0 0x21f0000 0x0 0x1000>; 971d548c217SVabhav Sharma interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 972d548c217SVabhav Sharma current-speed = <115200>; 973d548c217SVabhav Sharma status = "disabled"; 974d548c217SVabhav Sharma }; 975d548c217SVabhav Sharma 976d548c217SVabhav Sharma gpio0: gpio@2300000 { 977d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 978d548c217SVabhav Sharma reg = <0x0 0x2300000 0x0 0x10000>; 979d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 980d548c217SVabhav Sharma gpio-controller; 981d548c217SVabhav Sharma little-endian; 982d548c217SVabhav Sharma #gpio-cells = <2>; 983d548c217SVabhav Sharma interrupt-controller; 984d548c217SVabhav Sharma #interrupt-cells = <2>; 985d548c217SVabhav Sharma }; 986d548c217SVabhav Sharma 987d548c217SVabhav Sharma gpio1: gpio@2310000 { 988d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 989d548c217SVabhav Sharma reg = <0x0 0x2310000 0x0 0x10000>; 990d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 991d548c217SVabhav Sharma gpio-controller; 992d548c217SVabhav Sharma little-endian; 993d548c217SVabhav Sharma #gpio-cells = <2>; 994d548c217SVabhav Sharma interrupt-controller; 995d548c217SVabhav Sharma #interrupt-cells = <2>; 996d548c217SVabhav Sharma }; 997d548c217SVabhav Sharma 998d548c217SVabhav Sharma gpio2: gpio@2320000 { 999d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 1000d548c217SVabhav Sharma reg = <0x0 0x2320000 0x0 0x10000>; 1001d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1002d548c217SVabhav Sharma gpio-controller; 1003d548c217SVabhav Sharma little-endian; 1004d548c217SVabhav Sharma #gpio-cells = <2>; 1005d548c217SVabhav Sharma interrupt-controller; 1006d548c217SVabhav Sharma #interrupt-cells = <2>; 1007d548c217SVabhav Sharma }; 1008d548c217SVabhav Sharma 1009d548c217SVabhav Sharma gpio3: gpio@2330000 { 1010d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 1011d548c217SVabhav Sharma reg = <0x0 0x2330000 0x0 0x10000>; 1012d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1013d548c217SVabhav Sharma gpio-controller; 1014d548c217SVabhav Sharma little-endian; 1015d548c217SVabhav Sharma #gpio-cells = <2>; 1016d548c217SVabhav Sharma interrupt-controller; 1017d548c217SVabhav Sharma #interrupt-cells = <2>; 1018d548c217SVabhav Sharma }; 1019d548c217SVabhav Sharma 1020d548c217SVabhav Sharma watchdog@23a0000 { 1021d548c217SVabhav Sharma compatible = "arm,sbsa-gwdt"; 1022d548c217SVabhav Sharma reg = <0x0 0x23a0000 0 0x1000>, 1023d548c217SVabhav Sharma <0x0 0x2390000 0 0x1000>; 1024d548c217SVabhav Sharma interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1025d548c217SVabhav Sharma timeout-sec = <30>; 1026d548c217SVabhav Sharma }; 1027d548c217SVabhav Sharma 1028dca78e32SBiwen Li rcpm: power-controller@1e34040 { 1029dca78e32SBiwen Li compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1030dca78e32SBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 1031dca78e32SBiwen Li #fsl,rcpm-wakeup-cells = <7>; 1032dca78e32SBiwen Li little-endian; 1033dca78e32SBiwen Li }; 1034dca78e32SBiwen Li 1035dca78e32SBiwen Li ftm_alarm0: timer@2800000 { 1036dca78e32SBiwen Li compatible = "fsl,lx2160a-ftm-alarm"; 1037dca78e32SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1038dca78e32SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1039dca78e32SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1040dca78e32SBiwen Li }; 1041dca78e32SBiwen Li 1042d548c217SVabhav Sharma usb0: usb@3100000 { 1043d548c217SVabhav Sharma compatible = "snps,dwc3"; 1044d548c217SVabhav Sharma reg = <0x0 0x3100000 0x0 0x10000>; 1045d548c217SVabhav Sharma interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1046d548c217SVabhav Sharma dr_mode = "host"; 1047d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 1048a5b13770SRan Wang usb3-lpm-capable; 1049d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 10501000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1051d548c217SVabhav Sharma status = "disabled"; 1052d548c217SVabhav Sharma }; 1053d548c217SVabhav Sharma 1054d548c217SVabhav Sharma usb1: usb@3110000 { 1055d548c217SVabhav Sharma compatible = "snps,dwc3"; 1056d548c217SVabhav Sharma reg = <0x0 0x3110000 0x0 0x10000>; 1057d548c217SVabhav Sharma interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1058d548c217SVabhav Sharma dr_mode = "host"; 1059d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 1060a5b13770SRan Wang usb3-lpm-capable; 1061d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 10621000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1063d548c217SVabhav Sharma status = "disabled"; 1064d548c217SVabhav Sharma }; 1065d548c217SVabhav Sharma 1066071f7855SPeng Ma sata0: sata@3200000 { 1067071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1068071f7855SPeng Ma reg = <0x0 0x3200000 0x0 0x10000>, 1069071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1070071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1071071f7855SPeng Ma interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 10728e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 10738e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1074071f7855SPeng Ma dma-coherent; 1075071f7855SPeng Ma status = "disabled"; 1076071f7855SPeng Ma }; 1077071f7855SPeng Ma 1078071f7855SPeng Ma sata1: sata@3210000 { 1079071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1080071f7855SPeng Ma reg = <0x0 0x3210000 0x0 0x10000>, 1081071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1082071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1083071f7855SPeng Ma interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 10848e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 10858e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1086071f7855SPeng Ma dma-coherent; 1087071f7855SPeng Ma status = "disabled"; 1088071f7855SPeng Ma }; 1089071f7855SPeng Ma 1090071f7855SPeng Ma sata2: sata@3220000 { 1091071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1092071f7855SPeng Ma reg = <0x0 0x3220000 0x0 0x10000>, 1093071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1094071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1095071f7855SPeng Ma interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 10968e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 10978e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1098071f7855SPeng Ma dma-coherent; 1099071f7855SPeng Ma status = "disabled"; 1100071f7855SPeng Ma }; 1101071f7855SPeng Ma 1102071f7855SPeng Ma sata3: sata@3230000 { 1103071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1104071f7855SPeng Ma reg = <0x0 0x3230000 0x0 0x10000>, 1105071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1106071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1107071f7855SPeng Ma interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 11088e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 11098e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1110071f7855SPeng Ma dma-coherent; 1111071f7855SPeng Ma status = "disabled"; 1112071f7855SPeng Ma }; 1113071f7855SPeng Ma 1114f7d48ffcSWasim Khan pcie1: pcie@3400000 { 1115b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1116ce87d936SZhen Lei reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1117ce87d936SZhen Lei <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1118b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1119b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1120b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1121b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1122b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1123b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1124b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1125b1ad0e7dSHou Zhiqiang device_type = "pci"; 1126b1ad0e7dSHou Zhiqiang dma-coherent; 1127b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1128b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1129b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1130b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1131b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1132b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1133b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1134b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1135b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1136b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1137b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1138f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1139b1ad0e7dSHou Zhiqiang status = "disabled"; 1140b1ad0e7dSHou Zhiqiang }; 1141b1ad0e7dSHou Zhiqiang 1142f7d48ffcSWasim Khan pcie2: pcie@3500000 { 1143b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1144ce87d936SZhen Lei reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1145ce87d936SZhen Lei <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1146b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1147b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1148b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1149b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1150b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1151b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1152b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1153b1ad0e7dSHou Zhiqiang device_type = "pci"; 1154b1ad0e7dSHou Zhiqiang dma-coherent; 1155b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1156b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1157b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1158b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1159b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1160b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1161b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1162b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1163b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1164b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1165b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1166f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1167b1ad0e7dSHou Zhiqiang status = "disabled"; 1168b1ad0e7dSHou Zhiqiang }; 1169b1ad0e7dSHou Zhiqiang 1170f7d48ffcSWasim Khan pcie3: pcie@3600000 { 1171b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1172ce87d936SZhen Lei reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1173ce87d936SZhen Lei <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1174b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1175b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1176b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1177b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1178b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1179b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1180b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1181b1ad0e7dSHou Zhiqiang device_type = "pci"; 1182b1ad0e7dSHou Zhiqiang dma-coherent; 1183b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1184b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1185b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1186b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1187b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1188b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1189b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1190b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1191b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1192b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1193b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1194f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1195b1ad0e7dSHou Zhiqiang status = "disabled"; 1196b1ad0e7dSHou Zhiqiang }; 1197b1ad0e7dSHou Zhiqiang 1198f7d48ffcSWasim Khan pcie4: pcie@3700000 { 1199b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1200ce87d936SZhen Lei reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1201ce87d936SZhen Lei <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1202b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1203b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1204b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1205b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1206b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1207b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1208b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1209b1ad0e7dSHou Zhiqiang device_type = "pci"; 1210b1ad0e7dSHou Zhiqiang dma-coherent; 1211b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1212b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1213b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1214b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1215b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1216b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1217b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1218b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1219b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1220b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1221b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1222f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1223b1ad0e7dSHou Zhiqiang status = "disabled"; 1224b1ad0e7dSHou Zhiqiang }; 1225b1ad0e7dSHou Zhiqiang 1226f7d48ffcSWasim Khan pcie5: pcie@3800000 { 1227b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1228ce87d936SZhen Lei reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1229ce87d936SZhen Lei <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1230b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1231b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1232b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1233b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1234b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1235b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1236b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1237b1ad0e7dSHou Zhiqiang device_type = "pci"; 1238b1ad0e7dSHou Zhiqiang dma-coherent; 1239b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1240b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1241b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1242b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1243b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1244b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1245b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1246b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1247b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1248b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1249b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1250f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1251b1ad0e7dSHou Zhiqiang status = "disabled"; 1252b1ad0e7dSHou Zhiqiang }; 1253b1ad0e7dSHou Zhiqiang 1254f7d48ffcSWasim Khan pcie6: pcie@3900000 { 1255b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1256ce87d936SZhen Lei reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1257ce87d936SZhen Lei <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1258b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1259b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1260b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1261b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1262b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1263b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1264b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1265b1ad0e7dSHou Zhiqiang device_type = "pci"; 1266b1ad0e7dSHou Zhiqiang dma-coherent; 1267b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1268b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1269b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1270b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1271b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1272b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1273b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1274b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1275b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1276b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1277b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1278f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1279b1ad0e7dSHou Zhiqiang status = "disabled"; 1280b1ad0e7dSHou Zhiqiang }; 1281b1ad0e7dSHou Zhiqiang 1282d548c217SVabhav Sharma smmu: iommu@5000000 { 1283d548c217SVabhav Sharma compatible = "arm,mmu-500"; 1284d548c217SVabhav Sharma reg = <0 0x5000000 0 0x800000>; 1285d548c217SVabhav Sharma #iommu-cells = <1>; 1286d548c217SVabhav Sharma #global-interrupts = <14>; 1287d548c217SVabhav Sharma // global secure fault 1288d548c217SVabhav Sharma interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1289d548c217SVabhav Sharma // combined secure 1290d548c217SVabhav Sharma <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1291d548c217SVabhav Sharma // global non-secure fault 1292d548c217SVabhav Sharma <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1293d548c217SVabhav Sharma // combined non-secure 1294d548c217SVabhav Sharma <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1295d548c217SVabhav Sharma // performance counter interrupts 0-9 1296d548c217SVabhav Sharma <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1297d548c217SVabhav Sharma <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1298d548c217SVabhav Sharma <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1299d548c217SVabhav Sharma <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1300d548c217SVabhav Sharma <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1301d548c217SVabhav Sharma <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1302d548c217SVabhav Sharma <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1303d548c217SVabhav Sharma <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1304d548c217SVabhav Sharma <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1305d548c217SVabhav Sharma <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1306d548c217SVabhav Sharma // per context interrupt, 64 interrupts 1307d548c217SVabhav Sharma <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1308d548c217SVabhav Sharma <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1309d548c217SVabhav Sharma <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1310d548c217SVabhav Sharma <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1311d548c217SVabhav Sharma <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1312d548c217SVabhav Sharma <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1313d548c217SVabhav Sharma <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1314d548c217SVabhav Sharma <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1315d548c217SVabhav Sharma <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1316d548c217SVabhav Sharma <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1317d548c217SVabhav Sharma <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1318d548c217SVabhav Sharma <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1319d548c217SVabhav Sharma <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1320d548c217SVabhav Sharma <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1321d548c217SVabhav Sharma <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1322d548c217SVabhav Sharma <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1323d548c217SVabhav Sharma <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1324d548c217SVabhav Sharma <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1325d548c217SVabhav Sharma <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1326d548c217SVabhav Sharma <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1327d548c217SVabhav Sharma <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1328d548c217SVabhav Sharma <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1329d548c217SVabhav Sharma <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1330d548c217SVabhav Sharma <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1331d548c217SVabhav Sharma <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1332d548c217SVabhav Sharma <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1333d548c217SVabhav Sharma <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1334d548c217SVabhav Sharma <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1335d548c217SVabhav Sharma <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1336d548c217SVabhav Sharma <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1337d548c217SVabhav Sharma <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1338d548c217SVabhav Sharma <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1339d548c217SVabhav Sharma <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1340d548c217SVabhav Sharma <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1341d548c217SVabhav Sharma <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1342d548c217SVabhav Sharma <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1343d548c217SVabhav Sharma <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1344d548c217SVabhav Sharma <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1345d548c217SVabhav Sharma <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1346d548c217SVabhav Sharma <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1347d548c217SVabhav Sharma <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1348d548c217SVabhav Sharma <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1349d548c217SVabhav Sharma <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1350d548c217SVabhav Sharma <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1351d548c217SVabhav Sharma <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1352d548c217SVabhav Sharma <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1353d548c217SVabhav Sharma <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1354d548c217SVabhav Sharma <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1355d548c217SVabhav Sharma <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1356d548c217SVabhav Sharma <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1357d548c217SVabhav Sharma <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1358d548c217SVabhav Sharma <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1359d548c217SVabhav Sharma <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1360d548c217SVabhav Sharma <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1361d548c217SVabhav Sharma <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1362d548c217SVabhav Sharma <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1363d548c217SVabhav Sharma <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1364d548c217SVabhav Sharma <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1365d548c217SVabhav Sharma <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1366d548c217SVabhav Sharma <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1367d548c217SVabhav Sharma <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1368d548c217SVabhav Sharma <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1369d548c217SVabhav Sharma <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1370d548c217SVabhav Sharma <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1371d548c217SVabhav Sharma dma-coherent; 1372d548c217SVabhav Sharma }; 1373703c5e40SIoana Ciocoi Radulescu 1374546d92d3SIoana Ciornei console@8340020 { 1375546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 1376546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 1377546d92d3SIoana Ciornei }; 1378546d92d3SIoana Ciornei 1379fe844f19SYangbo Lu ptp-timer@8b95000 { 1380fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 1381fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 13828e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 13838e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 1384fe844f19SYangbo Lu little-endian; 1385fe844f19SYangbo Lu fsl,extts-fifo; 1386fe844f19SYangbo Lu }; 1387fe844f19SYangbo Lu 13886e1b8faeSIoana Ciornei /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 13896e1b8faeSIoana Ciornei emdio1: mdio@8b96000 { 13906e1b8faeSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 13916e1b8faeSIoana Ciornei reg = <0x0 0x8b96000 0x0 0x1000>; 13926e1b8faeSIoana Ciornei interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 13936e1b8faeSIoana Ciornei #address-cells = <1>; 13946e1b8faeSIoana Ciornei #size-cells = <0>; 13956e1b8faeSIoana Ciornei little-endian; 1396c126a0abSIoana Ciornei clock-frequency = <2500000>; 1397c126a0abSIoana Ciornei clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1398c126a0abSIoana Ciornei QORIQ_CLK_PLL_DIV(2)>; 13996e1b8faeSIoana Ciornei status = "disabled"; 14006e1b8faeSIoana Ciornei }; 14016e1b8faeSIoana Ciornei 14025705b9dcSRussell King emdio2: mdio@8b97000 { 14035705b9dcSRussell King compatible = "fsl,fman-memac-mdio"; 14045705b9dcSRussell King reg = <0x0 0x8b97000 0x0 0x1000>; 14055705b9dcSRussell King interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 14065705b9dcSRussell King little-endian; 14075705b9dcSRussell King #address-cells = <1>; 14085705b9dcSRussell King #size-cells = <0>; 1409c126a0abSIoana Ciornei clock-frequency = <2500000>; 1410c126a0abSIoana Ciornei clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1411c126a0abSIoana Ciornei QORIQ_CLK_PLL_DIV(2)>; 14125705b9dcSRussell King status = "disabled"; 14135705b9dcSRussell King }; 14145705b9dcSRussell King 1415f94cfe32SIoana Ciornei pcs_mdio1: mdio@8c07000 { 1416f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1417f94cfe32SIoana Ciornei reg = <0x0 0x8c07000 0x0 0x1000>; 1418f94cfe32SIoana Ciornei little-endian; 1419f94cfe32SIoana Ciornei #address-cells = <1>; 1420f94cfe32SIoana Ciornei #size-cells = <0>; 1421f94cfe32SIoana Ciornei status = "disabled"; 1422f94cfe32SIoana Ciornei 1423f94cfe32SIoana Ciornei pcs1: ethernet-phy@0 { 1424f94cfe32SIoana Ciornei reg = <0>; 1425f94cfe32SIoana Ciornei }; 1426f94cfe32SIoana Ciornei }; 1427f94cfe32SIoana Ciornei 1428f94cfe32SIoana Ciornei pcs_mdio2: mdio@8c0b000 { 1429f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1430f94cfe32SIoana Ciornei reg = <0x0 0x8c0b000 0x0 0x1000>; 1431f94cfe32SIoana Ciornei little-endian; 1432f94cfe32SIoana Ciornei #address-cells = <1>; 1433f94cfe32SIoana Ciornei #size-cells = <0>; 1434f94cfe32SIoana Ciornei status = "disabled"; 1435f94cfe32SIoana Ciornei 1436f94cfe32SIoana Ciornei pcs2: ethernet-phy@0 { 1437f94cfe32SIoana Ciornei reg = <0>; 1438f94cfe32SIoana Ciornei }; 1439f94cfe32SIoana Ciornei }; 1440f94cfe32SIoana Ciornei 1441f94cfe32SIoana Ciornei pcs_mdio3: mdio@8c0f000 { 1442f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1443f94cfe32SIoana Ciornei reg = <0x0 0x8c0f000 0x0 0x1000>; 1444f94cfe32SIoana Ciornei little-endian; 1445f94cfe32SIoana Ciornei #address-cells = <1>; 1446f94cfe32SIoana Ciornei #size-cells = <0>; 1447f94cfe32SIoana Ciornei status = "disabled"; 1448f94cfe32SIoana Ciornei 1449f94cfe32SIoana Ciornei pcs3: ethernet-phy@0 { 1450f94cfe32SIoana Ciornei reg = <0>; 1451f94cfe32SIoana Ciornei }; 1452f94cfe32SIoana Ciornei }; 1453f94cfe32SIoana Ciornei 1454f94cfe32SIoana Ciornei pcs_mdio4: mdio@8c13000 { 1455f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1456f94cfe32SIoana Ciornei reg = <0x0 0x8c13000 0x0 0x1000>; 1457f94cfe32SIoana Ciornei little-endian; 1458f94cfe32SIoana Ciornei #address-cells = <1>; 1459f94cfe32SIoana Ciornei #size-cells = <0>; 1460f94cfe32SIoana Ciornei status = "disabled"; 1461f94cfe32SIoana Ciornei 1462f94cfe32SIoana Ciornei pcs4: ethernet-phy@0 { 1463f94cfe32SIoana Ciornei reg = <0>; 1464f94cfe32SIoana Ciornei }; 1465f94cfe32SIoana Ciornei }; 1466f94cfe32SIoana Ciornei 1467f94cfe32SIoana Ciornei pcs_mdio5: mdio@8c17000 { 1468f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1469f94cfe32SIoana Ciornei reg = <0x0 0x8c17000 0x0 0x1000>; 1470f94cfe32SIoana Ciornei little-endian; 1471f94cfe32SIoana Ciornei #address-cells = <1>; 1472f94cfe32SIoana Ciornei #size-cells = <0>; 1473f94cfe32SIoana Ciornei status = "disabled"; 1474f94cfe32SIoana Ciornei 1475f94cfe32SIoana Ciornei pcs5: ethernet-phy@0 { 1476f94cfe32SIoana Ciornei reg = <0>; 1477f94cfe32SIoana Ciornei }; 1478f94cfe32SIoana Ciornei }; 1479f94cfe32SIoana Ciornei 1480f94cfe32SIoana Ciornei pcs_mdio6: mdio@8c1b000 { 1481f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1482f94cfe32SIoana Ciornei reg = <0x0 0x8c1b000 0x0 0x1000>; 1483f94cfe32SIoana Ciornei little-endian; 1484f94cfe32SIoana Ciornei #address-cells = <1>; 1485f94cfe32SIoana Ciornei #size-cells = <0>; 1486f94cfe32SIoana Ciornei status = "disabled"; 1487f94cfe32SIoana Ciornei 1488f94cfe32SIoana Ciornei pcs6: ethernet-phy@0 { 1489f94cfe32SIoana Ciornei reg = <0>; 1490f94cfe32SIoana Ciornei }; 1491f94cfe32SIoana Ciornei }; 1492f94cfe32SIoana Ciornei 1493f94cfe32SIoana Ciornei pcs_mdio7: mdio@8c1f000 { 1494f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1495f94cfe32SIoana Ciornei reg = <0x0 0x8c1f000 0x0 0x1000>; 1496f94cfe32SIoana Ciornei little-endian; 1497f94cfe32SIoana Ciornei #address-cells = <1>; 1498f94cfe32SIoana Ciornei #size-cells = <0>; 1499f94cfe32SIoana Ciornei status = "disabled"; 1500f94cfe32SIoana Ciornei 1501f94cfe32SIoana Ciornei pcs7: ethernet-phy@0 { 1502f94cfe32SIoana Ciornei reg = <0>; 1503f94cfe32SIoana Ciornei }; 1504f94cfe32SIoana Ciornei }; 1505f94cfe32SIoana Ciornei 1506f94cfe32SIoana Ciornei pcs_mdio8: mdio@8c23000 { 1507f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1508f94cfe32SIoana Ciornei reg = <0x0 0x8c23000 0x0 0x1000>; 1509f94cfe32SIoana Ciornei little-endian; 1510f94cfe32SIoana Ciornei #address-cells = <1>; 1511f94cfe32SIoana Ciornei #size-cells = <0>; 1512f94cfe32SIoana Ciornei status = "disabled"; 1513f94cfe32SIoana Ciornei 1514f94cfe32SIoana Ciornei pcs8: ethernet-phy@0 { 1515f94cfe32SIoana Ciornei reg = <0>; 1516f94cfe32SIoana Ciornei }; 1517f94cfe32SIoana Ciornei }; 1518f94cfe32SIoana Ciornei 1519f94cfe32SIoana Ciornei pcs_mdio9: mdio@8c27000 { 1520f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1521f94cfe32SIoana Ciornei reg = <0x0 0x8c27000 0x0 0x1000>; 1522f94cfe32SIoana Ciornei little-endian; 1523f94cfe32SIoana Ciornei #address-cells = <1>; 1524f94cfe32SIoana Ciornei #size-cells = <0>; 1525f94cfe32SIoana Ciornei status = "disabled"; 1526f94cfe32SIoana Ciornei 1527f94cfe32SIoana Ciornei pcs9: ethernet-phy@0 { 1528f94cfe32SIoana Ciornei reg = <0>; 1529f94cfe32SIoana Ciornei }; 1530f94cfe32SIoana Ciornei }; 1531f94cfe32SIoana Ciornei 1532f94cfe32SIoana Ciornei pcs_mdio10: mdio@8c2b000 { 1533f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1534f94cfe32SIoana Ciornei reg = <0x0 0x8c2b000 0x0 0x1000>; 1535f94cfe32SIoana Ciornei little-endian; 1536f94cfe32SIoana Ciornei #address-cells = <1>; 1537f94cfe32SIoana Ciornei #size-cells = <0>; 1538f94cfe32SIoana Ciornei status = "disabled"; 1539f94cfe32SIoana Ciornei 1540f94cfe32SIoana Ciornei pcs10: ethernet-phy@0 { 1541f94cfe32SIoana Ciornei reg = <0>; 1542f94cfe32SIoana Ciornei }; 1543f94cfe32SIoana Ciornei }; 1544f94cfe32SIoana Ciornei 1545f94cfe32SIoana Ciornei pcs_mdio11: mdio@8c2f000 { 1546f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1547f94cfe32SIoana Ciornei reg = <0x0 0x8c2f000 0x0 0x1000>; 1548f94cfe32SIoana Ciornei little-endian; 1549f94cfe32SIoana Ciornei #address-cells = <1>; 1550f94cfe32SIoana Ciornei #size-cells = <0>; 1551f94cfe32SIoana Ciornei status = "disabled"; 1552f94cfe32SIoana Ciornei 1553f94cfe32SIoana Ciornei pcs11: ethernet-phy@0 { 1554f94cfe32SIoana Ciornei reg = <0>; 1555f94cfe32SIoana Ciornei }; 1556f94cfe32SIoana Ciornei }; 1557f94cfe32SIoana Ciornei 1558f94cfe32SIoana Ciornei pcs_mdio12: mdio@8c33000 { 1559f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1560f94cfe32SIoana Ciornei reg = <0x0 0x8c33000 0x0 0x1000>; 1561f94cfe32SIoana Ciornei little-endian; 1562f94cfe32SIoana Ciornei #address-cells = <1>; 1563f94cfe32SIoana Ciornei #size-cells = <0>; 1564f94cfe32SIoana Ciornei status = "disabled"; 1565f94cfe32SIoana Ciornei 1566f94cfe32SIoana Ciornei pcs12: ethernet-phy@0 { 1567f94cfe32SIoana Ciornei reg = <0>; 1568f94cfe32SIoana Ciornei }; 1569f94cfe32SIoana Ciornei }; 1570f94cfe32SIoana Ciornei 1571f94cfe32SIoana Ciornei pcs_mdio13: mdio@8c37000 { 1572f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1573f94cfe32SIoana Ciornei reg = <0x0 0x8c37000 0x0 0x1000>; 1574f94cfe32SIoana Ciornei little-endian; 1575f94cfe32SIoana Ciornei #address-cells = <1>; 1576f94cfe32SIoana Ciornei #size-cells = <0>; 1577f94cfe32SIoana Ciornei status = "disabled"; 1578f94cfe32SIoana Ciornei 1579f94cfe32SIoana Ciornei pcs13: ethernet-phy@0 { 1580f94cfe32SIoana Ciornei reg = <0>; 1581f94cfe32SIoana Ciornei }; 1582f94cfe32SIoana Ciornei }; 1583f94cfe32SIoana Ciornei 1584f94cfe32SIoana Ciornei pcs_mdio14: mdio@8c3b000 { 1585f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1586f94cfe32SIoana Ciornei reg = <0x0 0x8c3b000 0x0 0x1000>; 1587f94cfe32SIoana Ciornei little-endian; 1588f94cfe32SIoana Ciornei #address-cells = <1>; 1589f94cfe32SIoana Ciornei #size-cells = <0>; 1590f94cfe32SIoana Ciornei status = "disabled"; 1591f94cfe32SIoana Ciornei 1592f94cfe32SIoana Ciornei pcs14: ethernet-phy@0 { 1593f94cfe32SIoana Ciornei reg = <0>; 1594f94cfe32SIoana Ciornei }; 1595f94cfe32SIoana Ciornei }; 1596f94cfe32SIoana Ciornei 1597f94cfe32SIoana Ciornei pcs_mdio15: mdio@8c3f000 { 1598f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1599f94cfe32SIoana Ciornei reg = <0x0 0x8c3f000 0x0 0x1000>; 1600f94cfe32SIoana Ciornei little-endian; 1601f94cfe32SIoana Ciornei #address-cells = <1>; 1602f94cfe32SIoana Ciornei #size-cells = <0>; 1603f94cfe32SIoana Ciornei status = "disabled"; 1604f94cfe32SIoana Ciornei 1605f94cfe32SIoana Ciornei pcs15: ethernet-phy@0 { 1606f94cfe32SIoana Ciornei reg = <0>; 1607f94cfe32SIoana Ciornei }; 1608f94cfe32SIoana Ciornei }; 1609f94cfe32SIoana Ciornei 1610f94cfe32SIoana Ciornei pcs_mdio16: mdio@8c43000 { 1611f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1612f94cfe32SIoana Ciornei reg = <0x0 0x8c43000 0x0 0x1000>; 1613f94cfe32SIoana Ciornei little-endian; 1614f94cfe32SIoana Ciornei #address-cells = <1>; 1615f94cfe32SIoana Ciornei #size-cells = <0>; 1616f94cfe32SIoana Ciornei status = "disabled"; 1617f94cfe32SIoana Ciornei 1618f94cfe32SIoana Ciornei pcs16: ethernet-phy@0 { 1619f94cfe32SIoana Ciornei reg = <0>; 1620f94cfe32SIoana Ciornei }; 1621f94cfe32SIoana Ciornei }; 1622f94cfe32SIoana Ciornei 1623f94cfe32SIoana Ciornei pcs_mdio17: mdio@8c47000 { 1624f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1625f94cfe32SIoana Ciornei reg = <0x0 0x8c47000 0x0 0x1000>; 1626f94cfe32SIoana Ciornei little-endian; 1627f94cfe32SIoana Ciornei #address-cells = <1>; 1628f94cfe32SIoana Ciornei #size-cells = <0>; 1629f94cfe32SIoana Ciornei status = "disabled"; 1630f94cfe32SIoana Ciornei 1631f94cfe32SIoana Ciornei pcs17: ethernet-phy@0 { 1632f94cfe32SIoana Ciornei reg = <0>; 1633f94cfe32SIoana Ciornei }; 1634f94cfe32SIoana Ciornei }; 1635f94cfe32SIoana Ciornei 1636f94cfe32SIoana Ciornei pcs_mdio18: mdio@8c4b000 { 1637f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1638f94cfe32SIoana Ciornei reg = <0x0 0x8c4b000 0x0 0x1000>; 1639f94cfe32SIoana Ciornei little-endian; 1640f94cfe32SIoana Ciornei #address-cells = <1>; 1641f94cfe32SIoana Ciornei #size-cells = <0>; 1642f94cfe32SIoana Ciornei status = "disabled"; 1643f94cfe32SIoana Ciornei 1644f94cfe32SIoana Ciornei pcs18: ethernet-phy@0 { 1645f94cfe32SIoana Ciornei reg = <0>; 1646f94cfe32SIoana Ciornei }; 1647f94cfe32SIoana Ciornei }; 1648f94cfe32SIoana Ciornei 1649703c5e40SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 1650703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 1651703c5e40SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, 1652703c5e40SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; 1653703c5e40SIoana Ciocoi Radulescu msi-parent = <&its>; 1654703c5e40SIoana Ciocoi Radulescu /* iommu-map property is fixed up by u-boot */ 1655703c5e40SIoana Ciocoi Radulescu iommu-map = <0 &smmu 0 0>; 1656703c5e40SIoana Ciocoi Radulescu dma-coherent; 1657703c5e40SIoana Ciocoi Radulescu #address-cells = <3>; 1658703c5e40SIoana Ciocoi Radulescu #size-cells = <1>; 1659703c5e40SIoana Ciocoi Radulescu 1660703c5e40SIoana Ciocoi Radulescu /* 1661703c5e40SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 1662703c5e40SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 1663703c5e40SIoana Ciocoi Radulescu */ 1664703c5e40SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1665703c5e40SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1666703c5e40SIoana Ciocoi Radulescu 1667703c5e40SIoana Ciocoi Radulescu /* 1668703c5e40SIoana Ciocoi Radulescu * Define the maximum number of MACs present on the SoC. 1669703c5e40SIoana Ciocoi Radulescu */ 1670703c5e40SIoana Ciocoi Radulescu dpmacs { 1671703c5e40SIoana Ciocoi Radulescu #address-cells = <1>; 1672703c5e40SIoana Ciocoi Radulescu #size-cells = <0>; 1673703c5e40SIoana Ciocoi Radulescu 1674f94cfe32SIoana Ciornei dpmac1: ethernet@1 { 1675703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1676703c5e40SIoana Ciocoi Radulescu reg = <0x1>; 1677f94cfe32SIoana Ciornei pcs-handle = <&pcs1>; 1678703c5e40SIoana Ciocoi Radulescu }; 1679703c5e40SIoana Ciocoi Radulescu 1680f94cfe32SIoana Ciornei dpmac2: ethernet@2 { 1681703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1682703c5e40SIoana Ciocoi Radulescu reg = <0x2>; 1683f94cfe32SIoana Ciornei pcs-handle = <&pcs2>; 1684703c5e40SIoana Ciocoi Radulescu }; 1685703c5e40SIoana Ciocoi Radulescu 1686f94cfe32SIoana Ciornei dpmac3: ethernet@3 { 1687703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1688703c5e40SIoana Ciocoi Radulescu reg = <0x3>; 1689f94cfe32SIoana Ciornei pcs-handle = <&pcs3>; 1690703c5e40SIoana Ciocoi Radulescu }; 1691703c5e40SIoana Ciocoi Radulescu 1692f94cfe32SIoana Ciornei dpmac4: ethernet@4 { 1693703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1694703c5e40SIoana Ciocoi Radulescu reg = <0x4>; 1695f94cfe32SIoana Ciornei pcs-handle = <&pcs4>; 1696703c5e40SIoana Ciocoi Radulescu }; 1697703c5e40SIoana Ciocoi Radulescu 1698f94cfe32SIoana Ciornei dpmac5: ethernet@5 { 1699703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1700703c5e40SIoana Ciocoi Radulescu reg = <0x5>; 1701f94cfe32SIoana Ciornei pcs-handle = <&pcs5>; 1702703c5e40SIoana Ciocoi Radulescu }; 1703703c5e40SIoana Ciocoi Radulescu 1704f94cfe32SIoana Ciornei dpmac6: ethernet@6 { 1705703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1706703c5e40SIoana Ciocoi Radulescu reg = <0x6>; 1707f94cfe32SIoana Ciornei pcs-handle = <&pcs6>; 1708703c5e40SIoana Ciocoi Radulescu }; 1709703c5e40SIoana Ciocoi Radulescu 1710f94cfe32SIoana Ciornei dpmac7: ethernet@7 { 1711703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1712703c5e40SIoana Ciocoi Radulescu reg = <0x7>; 1713f94cfe32SIoana Ciornei pcs-handle = <&pcs7>; 1714703c5e40SIoana Ciocoi Radulescu }; 1715703c5e40SIoana Ciocoi Radulescu 1716f94cfe32SIoana Ciornei dpmac8: ethernet@8 { 1717703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1718703c5e40SIoana Ciocoi Radulescu reg = <0x8>; 1719f94cfe32SIoana Ciornei pcs-handle = <&pcs8>; 1720703c5e40SIoana Ciocoi Radulescu }; 1721703c5e40SIoana Ciocoi Radulescu 1722f94cfe32SIoana Ciornei dpmac9: ethernet@9 { 1723703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1724703c5e40SIoana Ciocoi Radulescu reg = <0x9>; 1725f94cfe32SIoana Ciornei pcs-handle = <&pcs9>; 1726703c5e40SIoana Ciocoi Radulescu }; 1727703c5e40SIoana Ciocoi Radulescu 1728f94cfe32SIoana Ciornei dpmac10: ethernet@a { 1729703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1730703c5e40SIoana Ciocoi Radulescu reg = <0xa>; 1731f94cfe32SIoana Ciornei pcs-handle = <&pcs10>; 1732703c5e40SIoana Ciocoi Radulescu }; 1733703c5e40SIoana Ciocoi Radulescu 1734f94cfe32SIoana Ciornei dpmac11: ethernet@b { 1735703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1736703c5e40SIoana Ciocoi Radulescu reg = <0xb>; 1737f94cfe32SIoana Ciornei pcs-handle = <&pcs11>; 1738703c5e40SIoana Ciocoi Radulescu }; 1739703c5e40SIoana Ciocoi Radulescu 1740f94cfe32SIoana Ciornei dpmac12: ethernet@c { 1741703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1742703c5e40SIoana Ciocoi Radulescu reg = <0xc>; 1743f94cfe32SIoana Ciornei pcs-handle = <&pcs12>; 1744703c5e40SIoana Ciocoi Radulescu }; 1745703c5e40SIoana Ciocoi Radulescu 1746f94cfe32SIoana Ciornei dpmac13: ethernet@d { 1747703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1748703c5e40SIoana Ciocoi Radulescu reg = <0xd>; 1749f94cfe32SIoana Ciornei pcs-handle = <&pcs13>; 1750703c5e40SIoana Ciocoi Radulescu }; 1751703c5e40SIoana Ciocoi Radulescu 1752f94cfe32SIoana Ciornei dpmac14: ethernet@e { 1753703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1754703c5e40SIoana Ciocoi Radulescu reg = <0xe>; 1755f94cfe32SIoana Ciornei pcs-handle = <&pcs14>; 1756703c5e40SIoana Ciocoi Radulescu }; 1757703c5e40SIoana Ciocoi Radulescu 1758f94cfe32SIoana Ciornei dpmac15: ethernet@f { 1759703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1760703c5e40SIoana Ciocoi Radulescu reg = <0xf>; 1761f94cfe32SIoana Ciornei pcs-handle = <&pcs15>; 1762703c5e40SIoana Ciocoi Radulescu }; 1763703c5e40SIoana Ciocoi Radulescu 1764f94cfe32SIoana Ciornei dpmac16: ethernet@10 { 1765703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1766703c5e40SIoana Ciocoi Radulescu reg = <0x10>; 1767f94cfe32SIoana Ciornei pcs-handle = <&pcs16>; 1768703c5e40SIoana Ciocoi Radulescu }; 1769703c5e40SIoana Ciocoi Radulescu 1770f94cfe32SIoana Ciornei dpmac17: ethernet@11 { 1771703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1772703c5e40SIoana Ciocoi Radulescu reg = <0x11>; 1773f94cfe32SIoana Ciornei pcs-handle = <&pcs17>; 1774703c5e40SIoana Ciocoi Radulescu }; 1775703c5e40SIoana Ciocoi Radulescu 1776f94cfe32SIoana Ciornei dpmac18: ethernet@12 { 1777703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1778703c5e40SIoana Ciocoi Radulescu reg = <0x12>; 1779f94cfe32SIoana Ciornei pcs-handle = <&pcs18>; 1780703c5e40SIoana Ciocoi Radulescu }; 1781703c5e40SIoana Ciocoi Radulescu }; 1782703c5e40SIoana Ciocoi Radulescu }; 1783d548c217SVabhav Sharma }; 1784519bace3SPankaj Gupta 1785519bace3SPankaj Gupta firmware { 1786519bace3SPankaj Gupta optee: optee { 1787519bace3SPankaj Gupta compatible = "linaro,optee-tz"; 1788519bace3SPankaj Gupta method = "smc"; 1789519bace3SPankaj Gupta status = "disabled"; 1790519bace3SPankaj Gupta }; 1791519bace3SPankaj Gupta }; 1792d548c217SVabhav Sharma}; 1793