1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2019 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan #ifndef __SMU_V12_0_H__ 24*837d542aSEvan Quan #define __SMU_V12_0_H__ 25*837d542aSEvan Quan 26*837d542aSEvan Quan #include "amdgpu_smu.h" 27*837d542aSEvan Quan 28*837d542aSEvan Quan /* MP Apertures */ 29*837d542aSEvan Quan #define MP0_Public 0x03800000 30*837d542aSEvan Quan #define MP0_SRAM 0x03900000 31*837d542aSEvan Quan #define MP1_Public 0x03b00000 32*837d542aSEvan Quan #define MP1_SRAM 0x03c00004 33*837d542aSEvan Quan 34*837d542aSEvan Quan #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 35*837d542aSEvan Quan 36*837d542aSEvan Quan int smu_v12_0_check_fw_status(struct smu_context *smu); 37*837d542aSEvan Quan 38*837d542aSEvan Quan int smu_v12_0_check_fw_version(struct smu_context *smu); 39*837d542aSEvan Quan 40*837d542aSEvan Quan int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate); 41*837d542aSEvan Quan 42*837d542aSEvan Quan int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate); 43*837d542aSEvan Quan 44*837d542aSEvan Quan int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate); 45*837d542aSEvan Quan 46*837d542aSEvan Quan int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable); 47*837d542aSEvan Quan 48*837d542aSEvan Quan uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu); 49*837d542aSEvan Quan 50*837d542aSEvan Quan int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable); 51*837d542aSEvan Quan 52*837d542aSEvan Quan int smu_v12_0_fini_smc_tables(struct smu_context *smu); 53*837d542aSEvan Quan 54*837d542aSEvan Quan int smu_v12_0_set_default_dpm_tables(struct smu_context *smu); 55*837d542aSEvan Quan 56*837d542aSEvan Quan int smu_v12_0_mode2_reset(struct smu_context *smu); 57*837d542aSEvan Quan 58*837d542aSEvan Quan int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 59*837d542aSEvan Quan uint32_t min, uint32_t max); 60*837d542aSEvan Quan 61*837d542aSEvan Quan int smu_v12_0_set_driver_table_location(struct smu_context *smu); 62*837d542aSEvan Quan 63*837d542aSEvan Quan int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu); 64*837d542aSEvan Quan 65*837d542aSEvan Quan #endif 66*837d542aSEvan Quan #endif 67