Home
last modified time | relevance | path

Searched +full:0 +full:x00780000 (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_ops.c26 0,
27 0,
28 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
29 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
30 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
31 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
32 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
33 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
34 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
35 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dts209-setup.c29 #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
38 * [2] 0x00000000-0x00200000 : "Kernel"
39 * [3] 0x00200000-0x00600000 : "RootFS1"
40 * [4] 0x00600000-0x00700000 : "RootFS2"
41 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
42 * [5] 0x00760000-0x00780000 : "U-Boot Config"
43 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
48 .size = 0x00080000,
49 .offset = 0x00780000,
53 .size = 0x00200000,
[all …]
H A Dts409-setup.c40 * - RTC S35390A (@0x30) on I2C bus
49 #define QNAP_TS409_NOR_BOOT_BASE 0xff800000
58 * [2] 0x00000000-0x00200000 : "Kernel"
59 * [3] 0x00200000-0x00600000 : "RootFS1"
60 * [4] 0x00600000-0x00700000 : "RootFS2"
61 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
62 * [5] 0x00760000-0x00780000 : "U-Boot Config"
63 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
68 .size = 0x00080000,
69 .offset = 0x00780000,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml88 reg = <0 0x00784000 0 0x8ff>,
89 <0 0x00780000 0 0x7a0>,
90 <0 0x00782000 0 0x100>,
91 <0 0x00786000 0 0x1fff>;
100 reg = <0x25b 0x1>;
113 reg = <0 0x00784000 0 0x8ff>;
118 reg = <0x1eb 0x1>;
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-igep0033.dtsi15 cpu@0 {
22 reg = <0x80000000 0x10000000>; /* 256 MB */
27 pinctrl-0 = <&leds_pins>;
102 ethphy0: ethernet-phy@0 {
103 reg = <0>;
130 pinctrl-0 = <&nandflash_pins>;
132 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
134 nand@0,0 {
136 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
138 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
[all …]
/openbmc/linux/arch/powerpc/include/asm/nohash/
H A Dmmu-e500.h9 #define BOOK3E_PAGESZ_1K 0
44 #define MAS0_TLBSEL_MASK 0x30000000
49 #define MAS0_ESEL_MASK 0x0FFF0000
52 #define MAS0_NV(x) ((x) & 0x00000FFF)
53 #define MAS0_HES 0x00004000
54 #define MAS0_WQ_ALLWAYS 0x00000000
55 #define MAS0_WQ_COND 0x00001000
56 #define MAS0_WQ_CLR_RSRV 0x00002000
58 #define MAS1_VALID 0x80000000
59 #define MAS1_IPROT 0x40000000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-igep0033.dtsi18 cpu@0 {
25 reg = <0x80000000 0x10000000>; /* 256 MB */
30 pinctrl-0 = <&leds_pins>;
60 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
61 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
67 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
68 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
69 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
70 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
71 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h22 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
29 u32 dram_timing4; /* 0x10 */
34 u32 dram_addrw; /* 0x2c */
35 u32 dram_if_width; /* 0x30 */
39 u32 sbe_count; /* 0x40 */
43 u32 drop_addr; /* 0x50 */
47 u32 ctrl_width; /* 0x60 */
51 u32 rfifo_cmap; /* 0x70 */
55 u32 fpgaport_rst; /* 0x80 */
59 u32 prot_rule_addr; /* 0x90 */
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_combios.c134 uint16_t offset = 0, check_offset; in combios_get_table_offset()
137 return 0; in combios_get_table_offset()
142 check_offset = 0xc; in combios_get_table_offset()
145 check_offset = 0x14; in combios_get_table_offset()
148 check_offset = 0x2a; in combios_get_table_offset()
151 check_offset = 0x2c; in combios_get_table_offset()
154 check_offset = 0x2e; in combios_get_table_offset()
157 check_offset = 0x30; in combios_get_table_offset()
160 check_offset = 0x32; in combios_get_table_offset()
163 check_offset = 0x34; in combios_get_table_offset()
[all …]
/openbmc/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c30 * 0 = Rtt disabled
35 * 0 = Rtt disabled
48 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
62 rtt = 0; in fsl_ddr_get_rtt()
66 rtt = 0; in fsl_ddr_get_rtt()
152 unsigned int cs_n_en = 0; /* Chip Select enable */ in set_csn_config()
153 unsigned int intlv_en = 0; /* Memory controller interleave enable */ in set_csn_config()
154 unsigned int intlv_ctl = 0; /* Interleaving control */ in set_csn_config()
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
156 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ in set_csn_config()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dniu.h10 #define PIO 0x000000UL
11 #define FZC_PIO 0x080000UL
12 #define FZC_MAC 0x180000UL
13 #define FZC_IPP 0x280000UL
14 #define FFLP 0x300000UL
15 #define FZC_FFLP 0x380000UL
16 #define PIO_VADDR 0x400000UL
17 #define ZCP 0x500000UL
18 #define FZC_ZCP 0x580000UL
19 #define DMC 0x600000UL
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h28 #define CCSRAR_C 0x80000000 /* Commit */
37 u8 res3[0xbd4];
44 u8 res35[0x204];
57 u32 lawbar0; /* Local Access Window 0 Base Addr */
59 u32 lawar0; /* Local Access Window 0 Attrs */
117 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
118 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
177 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
178 u8 res2[4048]; /* fill up to 0x1000 */
191 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
[all …]
/openbmc/qemu/target/ppc/
H A Dcpu.h42 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
44 #define PPC_BIT32(bit) (0x80000000 >> (bit))
45 #define PPC_BIT8(bit) (0x80 >> (bit))
68 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
151 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
157 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
158 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
159 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
160 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
161 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlegacy/
H A Dcommands.h72 #define IL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
73 #define IL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
74 #define IL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
75 #define IL_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
83 N_ALIVE = 0x1,
84 N_ERROR = 0x2,
87 C_RXON = 0x10,
88 C_RXON_ASSOC = 0x11,
89 C_QOS_PARAM = 0x13,
90 C_RXON_TIMING = 0x14,
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/dvm/
H A Dcommands.h19 REPLY_ALIVE = 0x1,
20 REPLY_ERROR = 0x2,
21 REPLY_ECHO = 0x3, /* test command */
24 REPLY_RXON = 0x10,
25 REPLY_RXON_ASSOC = 0x11,
26 REPLY_QOS_PARAM = 0x13,
27 REPLY_RXON_TIMING = 0x14,
30 REPLY_ADD_STA = 0x18,
31 REPLY_REMOVE_STA = 0x19,
32 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx.xml.h52 TILE6_LINEAR = 0,
194 DEPTH6_NONE = 0,
309 PERF_CP_ALWAYS_COUNT = 0,
362 PERF_RBBM_ALWAYS_COUNT = 0,
379 PERF_PC_BUSY_CYCLES = 0,
424 PERF_VFD_BUSY_CYCLES = 0,
450 PERF_HLSQ_BUSY_CYCLES = 0,
474 PERF_VPC_BUSY_CYCLES = 0,
505 PERF_TSE_BUSY_CYCLES = 0,
528 PERF_RAS_BUSY_CYCLES = 0,
[all …]