17ac9a364SKalle Valo /******************************************************************************
27ac9a364SKalle Valo  *
37ac9a364SKalle Valo  * This file is provided under a dual BSD/GPLv2 license.  When using or
47ac9a364SKalle Valo  * redistributing this file, you may do so under either license.
57ac9a364SKalle Valo  *
67ac9a364SKalle Valo  * GPL LICENSE SUMMARY
77ac9a364SKalle Valo  *
87ac9a364SKalle Valo  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
97ac9a364SKalle Valo  *
107ac9a364SKalle Valo  * This program is free software; you can redistribute it and/or modify
117ac9a364SKalle Valo  * it under the terms of version 2 of the GNU General Public License as
127ac9a364SKalle Valo  * published by the Free Software Foundation.
137ac9a364SKalle Valo  *
147ac9a364SKalle Valo  * This program is distributed in the hope that it will be useful, but
157ac9a364SKalle Valo  * WITHOUT ANY WARRANTY; without even the implied warranty of
167ac9a364SKalle Valo  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
177ac9a364SKalle Valo  * General Public License for more details.
187ac9a364SKalle Valo  *
197ac9a364SKalle Valo  * You should have received a copy of the GNU General Public License
207ac9a364SKalle Valo  * along with this program; if not, write to the Free Software
217ac9a364SKalle Valo  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
227ac9a364SKalle Valo  * USA
237ac9a364SKalle Valo  *
247ac9a364SKalle Valo  * The full GNU General Public License is included in this distribution
257ac9a364SKalle Valo  * in the file called LICENSE.GPL.
267ac9a364SKalle Valo  *
277ac9a364SKalle Valo  * Contact Information:
287ac9a364SKalle Valo  *  Intel Linux Wireless <ilw@linux.intel.com>
297ac9a364SKalle Valo  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
307ac9a364SKalle Valo  *
317ac9a364SKalle Valo  * BSD LICENSE
327ac9a364SKalle Valo  *
337ac9a364SKalle Valo  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
347ac9a364SKalle Valo  * All rights reserved.
357ac9a364SKalle Valo  *
367ac9a364SKalle Valo  * Redistribution and use in source and binary forms, with or without
377ac9a364SKalle Valo  * modification, are permitted provided that the following conditions
387ac9a364SKalle Valo  * are met:
397ac9a364SKalle Valo  *
407ac9a364SKalle Valo  *  * Redistributions of source code must retain the above copyright
417ac9a364SKalle Valo  *    notice, this list of conditions and the following disclaimer.
427ac9a364SKalle Valo  *  * Redistributions in binary form must reproduce the above copyright
437ac9a364SKalle Valo  *    notice, this list of conditions and the following disclaimer in
447ac9a364SKalle Valo  *    the documentation and/or other materials provided with the
457ac9a364SKalle Valo  *    distribution.
467ac9a364SKalle Valo  *  * Neither the name Intel Corporation nor the names of its
477ac9a364SKalle Valo  *    contributors may be used to endorse or promote products derived
487ac9a364SKalle Valo  *    from this software without specific prior written permission.
497ac9a364SKalle Valo  *
507ac9a364SKalle Valo  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
517ac9a364SKalle Valo  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
527ac9a364SKalle Valo  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
537ac9a364SKalle Valo  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
547ac9a364SKalle Valo  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
557ac9a364SKalle Valo  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
567ac9a364SKalle Valo  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
577ac9a364SKalle Valo  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
587ac9a364SKalle Valo  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
597ac9a364SKalle Valo  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
607ac9a364SKalle Valo  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
617ac9a364SKalle Valo  *
627ac9a364SKalle Valo  *****************************************************************************/
637ac9a364SKalle Valo 
647ac9a364SKalle Valo #ifndef __il_commands_h__
657ac9a364SKalle Valo #define __il_commands_h__
667ac9a364SKalle Valo 
677ac9a364SKalle Valo #include <linux/ieee80211.h>
687ac9a364SKalle Valo 
697ac9a364SKalle Valo struct il_priv;
707ac9a364SKalle Valo 
717ac9a364SKalle Valo /* uCode version contains 4 values: Major/Minor/API/Serial */
727ac9a364SKalle Valo #define IL_UCODE_MAJOR(ver)	(((ver) & 0xFF000000) >> 24)
737ac9a364SKalle Valo #define IL_UCODE_MINOR(ver)	(((ver) & 0x00FF0000) >> 16)
747ac9a364SKalle Valo #define IL_UCODE_API(ver)	(((ver) & 0x0000FF00) >> 8)
757ac9a364SKalle Valo #define IL_UCODE_SERIAL(ver)	((ver) & 0x000000FF)
767ac9a364SKalle Valo 
777ac9a364SKalle Valo /* Tx rates */
787ac9a364SKalle Valo #define IL_CCK_RATES	4
797ac9a364SKalle Valo #define IL_OFDM_RATES	8
807ac9a364SKalle Valo #define IL_MAX_RATES	(IL_CCK_RATES + IL_OFDM_RATES)
817ac9a364SKalle Valo 
827ac9a364SKalle Valo enum {
837ac9a364SKalle Valo 	N_ALIVE = 0x1,
847ac9a364SKalle Valo 	N_ERROR = 0x2,
857ac9a364SKalle Valo 
867ac9a364SKalle Valo 	/* RXON and QOS commands */
877ac9a364SKalle Valo 	C_RXON = 0x10,
887ac9a364SKalle Valo 	C_RXON_ASSOC = 0x11,
897ac9a364SKalle Valo 	C_QOS_PARAM = 0x13,
907ac9a364SKalle Valo 	C_RXON_TIMING = 0x14,
917ac9a364SKalle Valo 
927ac9a364SKalle Valo 	/* Multi-Station support */
937ac9a364SKalle Valo 	C_ADD_STA = 0x18,
947ac9a364SKalle Valo 	C_REM_STA = 0x19,
957ac9a364SKalle Valo 
967ac9a364SKalle Valo 	/* Security */
977ac9a364SKalle Valo 	C_WEPKEY = 0x20,
987ac9a364SKalle Valo 
997ac9a364SKalle Valo 	/* RX, TX, LEDs */
1007ac9a364SKalle Valo 	N_3945_RX = 0x1b,	/* 3945 only */
1017ac9a364SKalle Valo 	C_TX = 0x1c,
1027ac9a364SKalle Valo 	C_RATE_SCALE = 0x47,	/* 3945 only */
1037ac9a364SKalle Valo 	C_LEDS = 0x48,
1047ac9a364SKalle Valo 	C_TX_LINK_QUALITY_CMD = 0x4e,	/* for 4965 */
1057ac9a364SKalle Valo 
1067ac9a364SKalle Valo 	/* 802.11h related */
1077ac9a364SKalle Valo 	C_CHANNEL_SWITCH = 0x72,
1087ac9a364SKalle Valo 	N_CHANNEL_SWITCH = 0x73,
1097ac9a364SKalle Valo 	C_SPECTRUM_MEASUREMENT = 0x74,
1107ac9a364SKalle Valo 	N_SPECTRUM_MEASUREMENT = 0x75,
1117ac9a364SKalle Valo 
1127ac9a364SKalle Valo 	/* Power Management */
1137ac9a364SKalle Valo 	C_POWER_TBL = 0x77,
1147ac9a364SKalle Valo 	N_PM_SLEEP = 0x7A,
1157ac9a364SKalle Valo 	N_PM_DEBUG_STATS = 0x7B,
1167ac9a364SKalle Valo 
1177ac9a364SKalle Valo 	/* Scan commands and notifications */
1187ac9a364SKalle Valo 	C_SCAN = 0x80,
1197ac9a364SKalle Valo 	C_SCAN_ABORT = 0x81,
1207ac9a364SKalle Valo 	N_SCAN_START = 0x82,
1217ac9a364SKalle Valo 	N_SCAN_RESULTS = 0x83,
1227ac9a364SKalle Valo 	N_SCAN_COMPLETE = 0x84,
1237ac9a364SKalle Valo 
1247ac9a364SKalle Valo 	/* IBSS/AP commands */
1257ac9a364SKalle Valo 	N_BEACON = 0x90,
1267ac9a364SKalle Valo 	C_TX_BEACON = 0x91,
1277ac9a364SKalle Valo 
1287ac9a364SKalle Valo 	/* Miscellaneous commands */
1297ac9a364SKalle Valo 	C_TX_PWR_TBL = 0x97,
1307ac9a364SKalle Valo 
1317ac9a364SKalle Valo 	/* Bluetooth device coexistence config command */
1327ac9a364SKalle Valo 	C_BT_CONFIG = 0x9b,
1337ac9a364SKalle Valo 
1347ac9a364SKalle Valo 	/* Statistics */
1357ac9a364SKalle Valo 	C_STATS = 0x9c,
1367ac9a364SKalle Valo 	N_STATS = 0x9d,
1377ac9a364SKalle Valo 
1387ac9a364SKalle Valo 	/* RF-KILL commands and notifications */
1397ac9a364SKalle Valo 	N_CARD_STATE = 0xa1,
1407ac9a364SKalle Valo 
1417ac9a364SKalle Valo 	/* Missed beacons notification */
1427ac9a364SKalle Valo 	N_MISSED_BEACONS = 0xa2,
1437ac9a364SKalle Valo 
1447ac9a364SKalle Valo 	C_CT_KILL_CONFIG = 0xa4,
1457ac9a364SKalle Valo 	C_SENSITIVITY = 0xa8,
1467ac9a364SKalle Valo 	C_PHY_CALIBRATION = 0xb0,
1477ac9a364SKalle Valo 	N_RX_PHY = 0xc0,
1487ac9a364SKalle Valo 	N_RX_MPDU = 0xc1,
1497ac9a364SKalle Valo 	N_RX = 0xc3,
1507ac9a364SKalle Valo 	N_COMPRESSED_BA = 0xc5,
1517ac9a364SKalle Valo 
1527ac9a364SKalle Valo 	IL_CN_MAX = 0xff
1537ac9a364SKalle Valo };
1547ac9a364SKalle Valo 
1557ac9a364SKalle Valo /******************************************************************************
1567ac9a364SKalle Valo  * (0)
1577ac9a364SKalle Valo  * Commonly used structures and definitions:
1587ac9a364SKalle Valo  * Command header, rate_n_flags, txpower
1597ac9a364SKalle Valo  *
1607ac9a364SKalle Valo  *****************************************************************************/
1617ac9a364SKalle Valo 
1627ac9a364SKalle Valo /* il_cmd_header flags value */
1637ac9a364SKalle Valo #define IL_CMD_FAILED_MSK 0x40
1647ac9a364SKalle Valo 
1657ac9a364SKalle Valo #define SEQ_TO_QUEUE(s)	(((s) >> 8) & 0x1f)
1667ac9a364SKalle Valo #define QUEUE_TO_SEQ(q)	(((q) & 0x1f) << 8)
1677ac9a364SKalle Valo #define SEQ_TO_IDX(s)	((s) & 0xff)
1687ac9a364SKalle Valo #define IDX_TO_SEQ(i)	((i) & 0xff)
1697ac9a364SKalle Valo #define SEQ_HUGE_FRAME	cpu_to_le16(0x4000)
1707ac9a364SKalle Valo #define SEQ_RX_FRAME	cpu_to_le16(0x8000)
1717ac9a364SKalle Valo 
1727ac9a364SKalle Valo /**
1737ac9a364SKalle Valo  * struct il_cmd_header
1747ac9a364SKalle Valo  *
1757ac9a364SKalle Valo  * This header format appears in the beginning of each command sent from the
1767ac9a364SKalle Valo  * driver, and each response/notification received from uCode.
1777ac9a364SKalle Valo  */
1787ac9a364SKalle Valo struct il_cmd_header {
1797ac9a364SKalle Valo 	u8 cmd;			/* Command ID:  C_RXON, etc. */
1807ac9a364SKalle Valo 	u8 flags;		/* 0:5 reserved, 6 abort, 7 internal */
1817ac9a364SKalle Valo 	/*
1827ac9a364SKalle Valo 	 * The driver sets up the sequence number to values of its choosing.
1837ac9a364SKalle Valo 	 * uCode does not use this value, but passes it back to the driver
1847ac9a364SKalle Valo 	 * when sending the response to each driver-originated command, so
1857ac9a364SKalle Valo 	 * the driver can match the response to the command.  Since the values
1867ac9a364SKalle Valo 	 * don't get used by uCode, the driver may set up an arbitrary format.
1877ac9a364SKalle Valo 	 *
1887ac9a364SKalle Valo 	 * There is one exception:  uCode sets bit 15 when it originates
1897ac9a364SKalle Valo 	 * the response/notification, i.e. when the response/notification
1907ac9a364SKalle Valo 	 * is not a direct response to a command sent by the driver.  For
1917ac9a364SKalle Valo 	 * example, uCode issues N_3945_RX when it sends a received frame
1927ac9a364SKalle Valo 	 * to the driver; it is not a direct response to any driver command.
1937ac9a364SKalle Valo 	 *
1947ac9a364SKalle Valo 	 * The Linux driver uses the following format:
1957ac9a364SKalle Valo 	 *
1967ac9a364SKalle Valo 	 *  0:7         tfd idx - position within TX queue
1977ac9a364SKalle Valo 	 *  8:12        TX queue id
1987ac9a364SKalle Valo 	 *  13          reserved
1997ac9a364SKalle Valo 	 *  14          huge - driver sets this to indicate command is in the
2007ac9a364SKalle Valo 	 *              'huge' storage at the end of the command buffers
2017ac9a364SKalle Valo 	 *  15          unsolicited RX or uCode-originated notification
2027ac9a364SKalle Valo 	 */
2037ac9a364SKalle Valo 	__le16 sequence;
2047ac9a364SKalle Valo 
2057ac9a364SKalle Valo 	/* command or response/notification data follows immediately */
2068863b121SGustavo A. R. Silva 	u8 data[];
2077ac9a364SKalle Valo } __packed;
2087ac9a364SKalle Valo 
2097ac9a364SKalle Valo /**
2107ac9a364SKalle Valo  * struct il3945_tx_power
2117ac9a364SKalle Valo  *
2127ac9a364SKalle Valo  * Used in C_TX_PWR_TBL, C_SCAN, C_CHANNEL_SWITCH
2137ac9a364SKalle Valo  *
2147ac9a364SKalle Valo  * Each entry contains two values:
2157ac9a364SKalle Valo  * 1)  DSP gain (or sometimes called DSP attenuation).  This is a fine-grained
2167ac9a364SKalle Valo  *     linear value that multiplies the output of the digital signal processor,
2177ac9a364SKalle Valo  *     before being sent to the analog radio.
2187ac9a364SKalle Valo  * 2)  Radio gain.  This sets the analog gain of the radio Tx path.
2197ac9a364SKalle Valo  *     It is a coarser setting, and behaves in a logarithmic (dB) fashion.
2207ac9a364SKalle Valo  *
2217ac9a364SKalle Valo  * Driver obtains values from struct il3945_tx_power power_gain_table[][].
2227ac9a364SKalle Valo  */
2237ac9a364SKalle Valo struct il3945_tx_power {
2247ac9a364SKalle Valo 	u8 tx_gain;		/* gain for analog radio */
2257ac9a364SKalle Valo 	u8 dsp_atten;		/* gain for DSP */
2267ac9a364SKalle Valo } __packed;
2277ac9a364SKalle Valo 
2287ac9a364SKalle Valo /**
2297ac9a364SKalle Valo  * struct il3945_power_per_rate
2307ac9a364SKalle Valo  *
2317ac9a364SKalle Valo  * Used in C_TX_PWR_TBL, C_CHANNEL_SWITCH
2327ac9a364SKalle Valo  */
2337ac9a364SKalle Valo struct il3945_power_per_rate {
2347ac9a364SKalle Valo 	u8 rate;		/* plcp */
2357ac9a364SKalle Valo 	struct il3945_tx_power tpc;
2367ac9a364SKalle Valo 	u8 reserved;
2377ac9a364SKalle Valo } __packed;
2387ac9a364SKalle Valo 
2397ac9a364SKalle Valo /**
2407ac9a364SKalle Valo  * iwl4965 rate_n_flags bit fields
2417ac9a364SKalle Valo  *
2427ac9a364SKalle Valo  * rate_n_flags format is used in following iwl4965 commands:
2437ac9a364SKalle Valo  *  N_RX (response only)
2447ac9a364SKalle Valo  *  N_RX_MPDU (response only)
2457ac9a364SKalle Valo  *  C_TX (both command and response)
2467ac9a364SKalle Valo  *  C_TX_LINK_QUALITY_CMD
2477ac9a364SKalle Valo  *
2487ac9a364SKalle Valo  * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"):
2497ac9a364SKalle Valo  *  2-0:  0)   6 Mbps
2507ac9a364SKalle Valo  *        1)  12 Mbps
2517ac9a364SKalle Valo  *        2)  18 Mbps
2527ac9a364SKalle Valo  *        3)  24 Mbps
2537ac9a364SKalle Valo  *        4)  36 Mbps
2547ac9a364SKalle Valo  *        5)  48 Mbps
2557ac9a364SKalle Valo  *        6)  54 Mbps
2567ac9a364SKalle Valo  *        7)  60 Mbps
2577ac9a364SKalle Valo  *
2587ac9a364SKalle Valo  *  4-3:  0)  Single stream (SISO)
2597ac9a364SKalle Valo  *        1)  Dual stream (MIMO)
2607ac9a364SKalle Valo  *        2)  Triple stream (MIMO)
2617ac9a364SKalle Valo  *
2627ac9a364SKalle Valo  *    5:  Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
2637ac9a364SKalle Valo  *
2647ac9a364SKalle Valo  * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"):
2657ac9a364SKalle Valo  *  3-0:  0xD)   6 Mbps
2667ac9a364SKalle Valo  *        0xF)   9 Mbps
2677ac9a364SKalle Valo  *        0x5)  12 Mbps
2687ac9a364SKalle Valo  *        0x7)  18 Mbps
2697ac9a364SKalle Valo  *        0x9)  24 Mbps
2707ac9a364SKalle Valo  *        0xB)  36 Mbps
2717ac9a364SKalle Valo  *        0x1)  48 Mbps
2727ac9a364SKalle Valo  *        0x3)  54 Mbps
2737ac9a364SKalle Valo  *
2747ac9a364SKalle Valo  * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"):
2757ac9a364SKalle Valo  *  6-0:   10)  1 Mbps
2767ac9a364SKalle Valo  *         20)  2 Mbps
2777ac9a364SKalle Valo  *         55)  5.5 Mbps
2787ac9a364SKalle Valo  *        110)  11 Mbps
2797ac9a364SKalle Valo  */
2807ac9a364SKalle Valo #define RATE_MCS_CODE_MSK 0x7
2817ac9a364SKalle Valo #define RATE_MCS_SPATIAL_POS 3
2827ac9a364SKalle Valo #define RATE_MCS_SPATIAL_MSK 0x18
2837ac9a364SKalle Valo #define RATE_MCS_HT_DUP_POS 5
2847ac9a364SKalle Valo #define RATE_MCS_HT_DUP_MSK 0x20
2857ac9a364SKalle Valo 
2867ac9a364SKalle Valo /* Bit 8: (1) HT format, (0) legacy format in bits 7:0 */
2877ac9a364SKalle Valo #define RATE_MCS_FLAGS_POS 8
2887ac9a364SKalle Valo #define RATE_MCS_HT_POS 8
2897ac9a364SKalle Valo #define RATE_MCS_HT_MSK 0x100
2907ac9a364SKalle Valo 
2917ac9a364SKalle Valo /* Bit 9: (1) CCK, (0) OFDM.  HT (bit 8) must be "0" for this bit to be valid */
2927ac9a364SKalle Valo #define RATE_MCS_CCK_POS 9
2937ac9a364SKalle Valo #define RATE_MCS_CCK_MSK 0x200
2947ac9a364SKalle Valo 
2957ac9a364SKalle Valo /* Bit 10: (1) Use Green Field preamble */
2967ac9a364SKalle Valo #define RATE_MCS_GF_POS 10
2977ac9a364SKalle Valo #define RATE_MCS_GF_MSK 0x400
2987ac9a364SKalle Valo 
2997ac9a364SKalle Valo /* Bit 11: (1) Use 40Mhz HT40 chnl width, (0) use 20 MHz legacy chnl width */
3007ac9a364SKalle Valo #define RATE_MCS_HT40_POS 11
3017ac9a364SKalle Valo #define RATE_MCS_HT40_MSK 0x800
3027ac9a364SKalle Valo 
3037ac9a364SKalle Valo /* Bit 12: (1) Duplicate data on both 20MHz chnls. HT40 (bit 11) must be set. */
3047ac9a364SKalle Valo #define RATE_MCS_DUP_POS 12
3057ac9a364SKalle Valo #define RATE_MCS_DUP_MSK 0x1000
3067ac9a364SKalle Valo 
3077ac9a364SKalle Valo /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3087ac9a364SKalle Valo #define RATE_MCS_SGI_POS 13
3097ac9a364SKalle Valo #define RATE_MCS_SGI_MSK 0x2000
3107ac9a364SKalle Valo 
3117ac9a364SKalle Valo /**
3127ac9a364SKalle Valo  * rate_n_flags Tx antenna masks
3137ac9a364SKalle Valo  * 4965 has 2 transmitters
3147ac9a364SKalle Valo  * bit14:16
3157ac9a364SKalle Valo  */
3167ac9a364SKalle Valo #define RATE_MCS_ANT_POS	14
3177ac9a364SKalle Valo #define RATE_MCS_ANT_A_MSK	0x04000
3187ac9a364SKalle Valo #define RATE_MCS_ANT_B_MSK	0x08000
3197ac9a364SKalle Valo #define RATE_MCS_ANT_C_MSK	0x10000
3207ac9a364SKalle Valo #define RATE_MCS_ANT_AB_MSK	(RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
3217ac9a364SKalle Valo #define RATE_MCS_ANT_ABC_MSK	(RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
3227ac9a364SKalle Valo #define RATE_ANT_NUM 3
3237ac9a364SKalle Valo 
3247ac9a364SKalle Valo #define POWER_TBL_NUM_ENTRIES			33
3257ac9a364SKalle Valo #define POWER_TBL_NUM_HT_OFDM_ENTRIES		32
3267ac9a364SKalle Valo #define POWER_TBL_CCK_ENTRY			32
3277ac9a364SKalle Valo 
3287ac9a364SKalle Valo #define IL_PWR_NUM_HT_OFDM_ENTRIES		24
3297ac9a364SKalle Valo #define IL_PWR_CCK_ENTRIES			2
3307ac9a364SKalle Valo 
3317ac9a364SKalle Valo /**
3327ac9a364SKalle Valo  * union il4965_tx_power_dual_stream
3337ac9a364SKalle Valo  *
3347ac9a364SKalle Valo  * Host format used for C_TX_PWR_TBL, C_CHANNEL_SWITCH
3357ac9a364SKalle Valo  * Use __le32 version (struct tx_power_dual_stream) when building command.
3367ac9a364SKalle Valo  *
3377ac9a364SKalle Valo  * Driver provides radio gain and DSP attenuation settings to device in pairs,
3387ac9a364SKalle Valo  * one value for each transmitter chain.  The first value is for transmitter A,
3397ac9a364SKalle Valo  * second for transmitter B.
3407ac9a364SKalle Valo  *
3417ac9a364SKalle Valo  * For SISO bit rates, both values in a pair should be identical.
3427ac9a364SKalle Valo  * For MIMO rates, one value may be different from the other,
3437ac9a364SKalle Valo  * in order to balance the Tx output between the two transmitters.
3447ac9a364SKalle Valo  *
3457ac9a364SKalle Valo  * See more details in doc for TXPOWER in 4965.h.
3467ac9a364SKalle Valo  */
3477ac9a364SKalle Valo union il4965_tx_power_dual_stream {
3487ac9a364SKalle Valo 	struct {
3497ac9a364SKalle Valo 		u8 radio_tx_gain[2];
3507ac9a364SKalle Valo 		u8 dsp_predis_atten[2];
3517ac9a364SKalle Valo 	} s;
3527ac9a364SKalle Valo 	u32 dw;
3537ac9a364SKalle Valo };
3547ac9a364SKalle Valo 
3557ac9a364SKalle Valo /**
3567ac9a364SKalle Valo  * struct tx_power_dual_stream
3577ac9a364SKalle Valo  *
3587ac9a364SKalle Valo  * Table entries in C_TX_PWR_TBL, C_CHANNEL_SWITCH
3597ac9a364SKalle Valo  *
3607ac9a364SKalle Valo  * Same format as il_tx_power_dual_stream, but __le32
3617ac9a364SKalle Valo  */
3627ac9a364SKalle Valo struct tx_power_dual_stream {
3637ac9a364SKalle Valo 	__le32 dw;
3647ac9a364SKalle Valo } __packed;
3657ac9a364SKalle Valo 
3667ac9a364SKalle Valo /**
3677ac9a364SKalle Valo  * struct il4965_tx_power_db
3687ac9a364SKalle Valo  *
3697ac9a364SKalle Valo  * Entire table within C_TX_PWR_TBL, C_CHANNEL_SWITCH
3707ac9a364SKalle Valo  */
3717ac9a364SKalle Valo struct il4965_tx_power_db {
3727ac9a364SKalle Valo 	struct tx_power_dual_stream power_tbl[POWER_TBL_NUM_ENTRIES];
3737ac9a364SKalle Valo } __packed;
3747ac9a364SKalle Valo 
3757ac9a364SKalle Valo /******************************************************************************
3767ac9a364SKalle Valo  * (0a)
3777ac9a364SKalle Valo  * Alive and Error Commands & Responses:
3787ac9a364SKalle Valo  *
3797ac9a364SKalle Valo  *****************************************************************************/
3807ac9a364SKalle Valo 
3817ac9a364SKalle Valo #define UCODE_VALID_OK	cpu_to_le32(0x1)
3827ac9a364SKalle Valo #define INITIALIZE_SUBTYPE    (9)
3837ac9a364SKalle Valo 
3847ac9a364SKalle Valo /*
3857ac9a364SKalle Valo  * ("Initialize") N_ALIVE = 0x1 (response only, not a command)
3867ac9a364SKalle Valo  *
3877ac9a364SKalle Valo  * uCode issues this "initialize alive" notification once the initialization
3887ac9a364SKalle Valo  * uCode image has completed its work, and is ready to load the runtime image.
3897ac9a364SKalle Valo  * This is the *first* "alive" notification that the driver will receive after
3907ac9a364SKalle Valo  * rebooting uCode; the "initialize" alive is indicated by subtype field == 9.
3917ac9a364SKalle Valo  *
3927ac9a364SKalle Valo  * See comments documenting "BSM" (bootstrap state machine).
3937ac9a364SKalle Valo  *
3947ac9a364SKalle Valo  * For 4965, this notification contains important calibration data for
3957ac9a364SKalle Valo  * calculating txpower settings:
3967ac9a364SKalle Valo  *
3977ac9a364SKalle Valo  * 1)  Power supply voltage indication.  The voltage sensor outputs higher
3987ac9a364SKalle Valo  *     values for lower voltage, and vice verse.
3997ac9a364SKalle Valo  *
4007ac9a364SKalle Valo  * 2)  Temperature measurement parameters, for each of two channel widths
4017ac9a364SKalle Valo  *     (20 MHz and 40 MHz) supported by the radios.  Temperature sensing
4027ac9a364SKalle Valo  *     is done via one of the receiver chains, and channel width influences
4037ac9a364SKalle Valo  *     the results.
4047ac9a364SKalle Valo  *
4057ac9a364SKalle Valo  * 3)  Tx gain compensation to balance 4965's 2 Tx chains for MIMO operation,
4067ac9a364SKalle Valo  *     for each of 5 frequency ranges.
4077ac9a364SKalle Valo  */
4087ac9a364SKalle Valo struct il_init_alive_resp {
4097ac9a364SKalle Valo 	u8 ucode_minor;
4107ac9a364SKalle Valo 	u8 ucode_major;
4117ac9a364SKalle Valo 	__le16 reserved1;
4127ac9a364SKalle Valo 	u8 sw_rev[8];
4137ac9a364SKalle Valo 	u8 ver_type;
4147ac9a364SKalle Valo 	u8 ver_subtype;		/* "9" for initialize alive */
4157ac9a364SKalle Valo 	__le16 reserved2;
4167ac9a364SKalle Valo 	__le32 log_event_table_ptr;
4177ac9a364SKalle Valo 	__le32 error_event_table_ptr;
4187ac9a364SKalle Valo 	__le32 timestamp;
4197ac9a364SKalle Valo 	__le32 is_valid;
4207ac9a364SKalle Valo 
4217ac9a364SKalle Valo 	/* calibration values from "initialize" uCode */
4227ac9a364SKalle Valo 	__le32 voltage;		/* signed, higher value is lower voltage */
4237ac9a364SKalle Valo 	__le32 therm_r1[2];	/* signed, 1st for normal, 2nd for HT40 */
4247ac9a364SKalle Valo 	__le32 therm_r2[2];	/* signed */
4257ac9a364SKalle Valo 	__le32 therm_r3[2];	/* signed */
4267ac9a364SKalle Valo 	__le32 therm_r4[2];	/* signed */
4277ac9a364SKalle Valo 	__le32 tx_atten[5][2];	/* signed MIMO gain comp, 5 freq groups,
4287ac9a364SKalle Valo 				 * 2 Tx chains */
4297ac9a364SKalle Valo } __packed;
4307ac9a364SKalle Valo 
4317ac9a364SKalle Valo /**
4327ac9a364SKalle Valo  * N_ALIVE = 0x1 (response only, not a command)
4337ac9a364SKalle Valo  *
4347ac9a364SKalle Valo  * uCode issues this "alive" notification once the runtime image is ready
4357ac9a364SKalle Valo  * to receive commands from the driver.  This is the *second* "alive"
4367ac9a364SKalle Valo  * notification that the driver will receive after rebooting uCode;
4377ac9a364SKalle Valo  * this "alive" is indicated by subtype field != 9.
4387ac9a364SKalle Valo  *
4397ac9a364SKalle Valo  * See comments documenting "BSM" (bootstrap state machine).
4407ac9a364SKalle Valo  *
4417ac9a364SKalle Valo  * This response includes two pointers to structures within the device's
4427ac9a364SKalle Valo  * data SRAM (access via HBUS_TARG_MEM_* regs) that are useful for debugging:
4437ac9a364SKalle Valo  *
4447ac9a364SKalle Valo  * 1)  log_event_table_ptr indicates base of the event log.  This traces
4457ac9a364SKalle Valo  *     a 256-entry history of uCode execution within a circular buffer.
4467ac9a364SKalle Valo  *     Its header format is:
4477ac9a364SKalle Valo  *
4487ac9a364SKalle Valo  *	__le32 log_size;     log capacity (in number of entries)
4497ac9a364SKalle Valo  *	__le32 type;         (1) timestamp with each entry, (0) no timestamp
4507ac9a364SKalle Valo  *	__le32 wraps;        # times uCode has wrapped to top of circular buffer
4517ac9a364SKalle Valo  *      __le32 write_idx;  next circular buffer entry that uCode would fill
4527ac9a364SKalle Valo  *
4537ac9a364SKalle Valo  *     The header is followed by the circular buffer of log entries.  Entries
4547ac9a364SKalle Valo  *     with timestamps have the following format:
4557ac9a364SKalle Valo  *
4567ac9a364SKalle Valo  *	__le32 event_id;     range 0 - 1500
4577ac9a364SKalle Valo  *	__le32 timestamp;    low 32 bits of TSF (of network, if associated)
4587ac9a364SKalle Valo  *	__le32 data;         event_id-specific data value
4597ac9a364SKalle Valo  *
4607ac9a364SKalle Valo  *     Entries without timestamps contain only event_id and data.
4617ac9a364SKalle Valo  *
4627ac9a364SKalle Valo  *
4637ac9a364SKalle Valo  * 2)  error_event_table_ptr indicates base of the error log.  This contains
4647ac9a364SKalle Valo  *     information about any uCode error that occurs.  For 4965, the format
4657ac9a364SKalle Valo  *     of the error log is:
4667ac9a364SKalle Valo  *
4677ac9a364SKalle Valo  *	__le32 valid;        (nonzero) valid, (0) log is empty
4687ac9a364SKalle Valo  *	__le32 error_id;     type of error
4697ac9a364SKalle Valo  *	__le32 pc;           program counter
4707ac9a364SKalle Valo  *	__le32 blink1;       branch link
4717ac9a364SKalle Valo  *	__le32 blink2;       branch link
4727ac9a364SKalle Valo  *	__le32 ilink1;       interrupt link
4737ac9a364SKalle Valo  *	__le32 ilink2;       interrupt link
4747ac9a364SKalle Valo  *	__le32 data1;        error-specific data
4757ac9a364SKalle Valo  *	__le32 data2;        error-specific data
4767ac9a364SKalle Valo  *	__le32 line;         source code line of error
4777ac9a364SKalle Valo  *	__le32 bcon_time;    beacon timer
4787ac9a364SKalle Valo  *	__le32 tsf_low;      network timestamp function timer
4797ac9a364SKalle Valo  *	__le32 tsf_hi;       network timestamp function timer
4807ac9a364SKalle Valo  *	__le32 gp1;          GP1 timer register
4817ac9a364SKalle Valo  *	__le32 gp2;          GP2 timer register
4827ac9a364SKalle Valo  *	__le32 gp3;          GP3 timer register
4837ac9a364SKalle Valo  *	__le32 ucode_ver;    uCode version
4847ac9a364SKalle Valo  *	__le32 hw_ver;       HW Silicon version
4857ac9a364SKalle Valo  *	__le32 brd_ver;      HW board version
4867ac9a364SKalle Valo  *	__le32 log_pc;       log program counter
4877ac9a364SKalle Valo  *	__le32 frame_ptr;    frame pointer
4887ac9a364SKalle Valo  *	__le32 stack_ptr;    stack pointer
4897ac9a364SKalle Valo  *	__le32 hcmd;         last host command
4907ac9a364SKalle Valo  *	__le32 isr0;         isr status register LMPM_NIC_ISR0: rxtx_flag
4917ac9a364SKalle Valo  *	__le32 isr1;         isr status register LMPM_NIC_ISR1: host_flag
4927ac9a364SKalle Valo  *	__le32 isr2;         isr status register LMPM_NIC_ISR2: enc_flag
4937ac9a364SKalle Valo  *	__le32 isr3;         isr status register LMPM_NIC_ISR3: time_flag
4947ac9a364SKalle Valo  *	__le32 isr4;         isr status register LMPM_NIC_ISR4: wico interrupt
4957ac9a364SKalle Valo  *	__le32 isr_pref;     isr status register LMPM_NIC_PREF_STAT
4967ac9a364SKalle Valo  *	__le32 wait_event;   wait event() caller address
4977ac9a364SKalle Valo  *	__le32 l2p_control;  L2pControlField
4987ac9a364SKalle Valo  *	__le32 l2p_duration; L2pDurationField
4997ac9a364SKalle Valo  *	__le32 l2p_mhvalid;  L2pMhValidBits
5007ac9a364SKalle Valo  *	__le32 l2p_addr_match; L2pAddrMatchStat
5017ac9a364SKalle Valo  *	__le32 lmpm_pmg_sel; indicate which clocks are turned on (LMPM_PMG_SEL)
5027ac9a364SKalle Valo  *	__le32 u_timestamp;  indicate when the date and time of the compilation
5037ac9a364SKalle Valo  *	__le32 reserved;
5047ac9a364SKalle Valo  *
5057ac9a364SKalle Valo  * The Linux driver can print both logs to the system log when a uCode error
5067ac9a364SKalle Valo  * occurs.
5077ac9a364SKalle Valo  */
5087ac9a364SKalle Valo struct il_alive_resp {
5097ac9a364SKalle Valo 	u8 ucode_minor;
5107ac9a364SKalle Valo 	u8 ucode_major;
5117ac9a364SKalle Valo 	__le16 reserved1;
5127ac9a364SKalle Valo 	u8 sw_rev[8];
5137ac9a364SKalle Valo 	u8 ver_type;
5147ac9a364SKalle Valo 	u8 ver_subtype;		/* not "9" for runtime alive */
5157ac9a364SKalle Valo 	__le16 reserved2;
5167ac9a364SKalle Valo 	__le32 log_event_table_ptr;	/* SRAM address for event log */
5177ac9a364SKalle Valo 	__le32 error_event_table_ptr;	/* SRAM address for error log */
5187ac9a364SKalle Valo 	__le32 timestamp;
5197ac9a364SKalle Valo 	__le32 is_valid;
5207ac9a364SKalle Valo } __packed;
5217ac9a364SKalle Valo 
5227ac9a364SKalle Valo /*
5237ac9a364SKalle Valo  * N_ERROR = 0x2 (response only, not a command)
5247ac9a364SKalle Valo  */
5257ac9a364SKalle Valo struct il_error_resp {
5267ac9a364SKalle Valo 	__le32 error_type;
5277ac9a364SKalle Valo 	u8 cmd_id;
5287ac9a364SKalle Valo 	u8 reserved1;
5297ac9a364SKalle Valo 	__le16 bad_cmd_seq_num;
5307ac9a364SKalle Valo 	__le32 error_info;
5317ac9a364SKalle Valo 	__le64 timestamp;
5327ac9a364SKalle Valo } __packed;
5337ac9a364SKalle Valo 
5347ac9a364SKalle Valo /******************************************************************************
5357ac9a364SKalle Valo  * (1)
5367ac9a364SKalle Valo  * RXON Commands & Responses:
5377ac9a364SKalle Valo  *
5387ac9a364SKalle Valo  *****************************************************************************/
5397ac9a364SKalle Valo 
5407ac9a364SKalle Valo /*
5417ac9a364SKalle Valo  * Rx config defines & structure
5427ac9a364SKalle Valo  */
5437ac9a364SKalle Valo /* rx_config device types  */
5447ac9a364SKalle Valo enum {
5457ac9a364SKalle Valo 	RXON_DEV_TYPE_AP = 1,
5467ac9a364SKalle Valo 	RXON_DEV_TYPE_ESS = 3,
5477ac9a364SKalle Valo 	RXON_DEV_TYPE_IBSS = 4,
5487ac9a364SKalle Valo 	RXON_DEV_TYPE_SNIFFER = 6,
5497ac9a364SKalle Valo };
5507ac9a364SKalle Valo 
5517ac9a364SKalle Valo #define RXON_RX_CHAIN_DRIVER_FORCE_MSK		cpu_to_le16(0x1 << 0)
5527ac9a364SKalle Valo #define RXON_RX_CHAIN_DRIVER_FORCE_POS		(0)
5537ac9a364SKalle Valo #define RXON_RX_CHAIN_VALID_MSK			cpu_to_le16(0x7 << 1)
5547ac9a364SKalle Valo #define RXON_RX_CHAIN_VALID_POS			(1)
5557ac9a364SKalle Valo #define RXON_RX_CHAIN_FORCE_SEL_MSK		cpu_to_le16(0x7 << 4)
5567ac9a364SKalle Valo #define RXON_RX_CHAIN_FORCE_SEL_POS		(4)
5577ac9a364SKalle Valo #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK	cpu_to_le16(0x7 << 7)
5587ac9a364SKalle Valo #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS	(7)
5597ac9a364SKalle Valo #define RXON_RX_CHAIN_CNT_MSK			cpu_to_le16(0x3 << 10)
5607ac9a364SKalle Valo #define RXON_RX_CHAIN_CNT_POS			(10)
5617ac9a364SKalle Valo #define RXON_RX_CHAIN_MIMO_CNT_MSK		cpu_to_le16(0x3 << 12)
5627ac9a364SKalle Valo #define RXON_RX_CHAIN_MIMO_CNT_POS		(12)
5637ac9a364SKalle Valo #define RXON_RX_CHAIN_MIMO_FORCE_MSK		cpu_to_le16(0x1 << 14)
5647ac9a364SKalle Valo #define RXON_RX_CHAIN_MIMO_FORCE_POS		(14)
5657ac9a364SKalle Valo 
5667ac9a364SKalle Valo /* rx_config flags */
5677ac9a364SKalle Valo /* band & modulation selection */
5687ac9a364SKalle Valo #define RXON_FLG_BAND_24G_MSK           cpu_to_le32(1 << 0)
5697ac9a364SKalle Valo #define RXON_FLG_CCK_MSK                cpu_to_le32(1 << 1)
5707ac9a364SKalle Valo /* auto detection enable */
5717ac9a364SKalle Valo #define RXON_FLG_AUTO_DETECT_MSK        cpu_to_le32(1 << 2)
5727ac9a364SKalle Valo /* TGg protection when tx */
5737ac9a364SKalle Valo #define RXON_FLG_TGG_PROTECT_MSK        cpu_to_le32(1 << 3)
5747ac9a364SKalle Valo /* cck short slot & preamble */
5757ac9a364SKalle Valo #define RXON_FLG_SHORT_SLOT_MSK          cpu_to_le32(1 << 4)
5767ac9a364SKalle Valo #define RXON_FLG_SHORT_PREAMBLE_MSK     cpu_to_le32(1 << 5)
5777ac9a364SKalle Valo /* antenna selection */
5787ac9a364SKalle Valo #define RXON_FLG_DIS_DIV_MSK            cpu_to_le32(1 << 7)
5797ac9a364SKalle Valo #define RXON_FLG_ANT_SEL_MSK            cpu_to_le32(0x0f00)
5807ac9a364SKalle Valo #define RXON_FLG_ANT_A_MSK              cpu_to_le32(1 << 8)
5817ac9a364SKalle Valo #define RXON_FLG_ANT_B_MSK              cpu_to_le32(1 << 9)
5827ac9a364SKalle Valo /* radar detection enable */
5837ac9a364SKalle Valo #define RXON_FLG_RADAR_DETECT_MSK       cpu_to_le32(1 << 12)
5847ac9a364SKalle Valo #define RXON_FLG_TGJ_NARROW_BAND_MSK    cpu_to_le32(1 << 13)
5857ac9a364SKalle Valo /* rx response to host with 8-byte TSF
5867ac9a364SKalle Valo * (according to ON_AIR deassertion) */
5877ac9a364SKalle Valo #define RXON_FLG_TSF2HOST_MSK           cpu_to_le32(1 << 15)
5887ac9a364SKalle Valo 
5897ac9a364SKalle Valo /* HT flags */
5907ac9a364SKalle Valo #define RXON_FLG_CTRL_CHANNEL_LOC_POS		(22)
5917ac9a364SKalle Valo #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK	cpu_to_le32(0x1 << 22)
5927ac9a364SKalle Valo 
5937ac9a364SKalle Valo #define RXON_FLG_HT_OPERATING_MODE_POS		(23)
5947ac9a364SKalle Valo 
5957ac9a364SKalle Valo #define RXON_FLG_HT_PROT_MSK			cpu_to_le32(0x1 << 23)
5967ac9a364SKalle Valo #define RXON_FLG_HT40_PROT_MSK			cpu_to_le32(0x2 << 23)
5977ac9a364SKalle Valo 
5987ac9a364SKalle Valo #define RXON_FLG_CHANNEL_MODE_POS		(25)
5997ac9a364SKalle Valo #define RXON_FLG_CHANNEL_MODE_MSK		cpu_to_le32(0x3 << 25)
6007ac9a364SKalle Valo 
6017ac9a364SKalle Valo /* channel mode */
6027ac9a364SKalle Valo enum {
6037ac9a364SKalle Valo 	CHANNEL_MODE_LEGACY = 0,
6047ac9a364SKalle Valo 	CHANNEL_MODE_PURE_40 = 1,
6057ac9a364SKalle Valo 	CHANNEL_MODE_MIXED = 2,
6067ac9a364SKalle Valo 	CHANNEL_MODE_RESERVED = 3,
6077ac9a364SKalle Valo };
6087ac9a364SKalle Valo #define RXON_FLG_CHANNEL_MODE_LEGACY			\
6097ac9a364SKalle Valo 	cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
6107ac9a364SKalle Valo #define RXON_FLG_CHANNEL_MODE_PURE_40			\
6117ac9a364SKalle Valo 	cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
6127ac9a364SKalle Valo #define RXON_FLG_CHANNEL_MODE_MIXED			\
6137ac9a364SKalle Valo 	cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
6147ac9a364SKalle Valo 
6157ac9a364SKalle Valo /* CTS to self (if spec allows) flag */
6167ac9a364SKalle Valo #define RXON_FLG_SELF_CTS_EN			cpu_to_le32(0x1<<30)
6177ac9a364SKalle Valo 
6187ac9a364SKalle Valo /* rx_config filter flags */
6197ac9a364SKalle Valo /* accept all data frames */
6207ac9a364SKalle Valo #define RXON_FILTER_PROMISC_MSK         cpu_to_le32(1 << 0)
6217ac9a364SKalle Valo /* pass control & management to host */
6227ac9a364SKalle Valo #define RXON_FILTER_CTL2HOST_MSK        cpu_to_le32(1 << 1)
6237ac9a364SKalle Valo /* accept multi-cast */
6247ac9a364SKalle Valo #define RXON_FILTER_ACCEPT_GRP_MSK      cpu_to_le32(1 << 2)
6257ac9a364SKalle Valo /* don't decrypt uni-cast frames */
6267ac9a364SKalle Valo #define RXON_FILTER_DIS_DECRYPT_MSK     cpu_to_le32(1 << 3)
6277ac9a364SKalle Valo /* don't decrypt multi-cast frames */
6287ac9a364SKalle Valo #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
6297ac9a364SKalle Valo /* STA is associated */
6307ac9a364SKalle Valo #define RXON_FILTER_ASSOC_MSK           cpu_to_le32(1 << 5)
6317ac9a364SKalle Valo /* transfer to host non bssid beacons in associated state */
6327ac9a364SKalle Valo #define RXON_FILTER_BCON_AWARE_MSK      cpu_to_le32(1 << 6)
6337ac9a364SKalle Valo 
6347ac9a364SKalle Valo /**
6357ac9a364SKalle Valo  * C_RXON = 0x10 (command, has simple generic response)
6367ac9a364SKalle Valo  *
6377ac9a364SKalle Valo  * RXON tunes the radio tuner to a service channel, and sets up a number
6387ac9a364SKalle Valo  * of parameters that are used primarily for Rx, but also for Tx operations.
6397ac9a364SKalle Valo  *
6407ac9a364SKalle Valo  * NOTE:  When tuning to a new channel, driver must set the
6417ac9a364SKalle Valo  *        RXON_FILTER_ASSOC_MSK to 0.  This will clear station-dependent
6427ac9a364SKalle Valo  *        info within the device, including the station tables, tx retry
6437ac9a364SKalle Valo  *        rate tables, and txpower tables.  Driver must build a new station
6447ac9a364SKalle Valo  *        table and txpower table before transmitting anything on the RXON
6457ac9a364SKalle Valo  *        channel.
6467ac9a364SKalle Valo  *
6477ac9a364SKalle Valo  * NOTE:  All RXONs wipe clean the internal txpower table.  Driver must
6487ac9a364SKalle Valo  *        issue a new C_TX_PWR_TBL after each C_RXON (0x10),
6497ac9a364SKalle Valo  *        regardless of whether RXON_FILTER_ASSOC_MSK is set.
6507ac9a364SKalle Valo  */
6517ac9a364SKalle Valo 
6527ac9a364SKalle Valo struct il3945_rxon_cmd {
6537ac9a364SKalle Valo 	u8 node_addr[6];
6547ac9a364SKalle Valo 	__le16 reserved1;
6557ac9a364SKalle Valo 	u8 bssid_addr[6];
6567ac9a364SKalle Valo 	__le16 reserved2;
6577ac9a364SKalle Valo 	u8 wlap_bssid_addr[6];
6587ac9a364SKalle Valo 	__le16 reserved3;
6597ac9a364SKalle Valo 	u8 dev_type;
6607ac9a364SKalle Valo 	u8 air_propagation;
6617ac9a364SKalle Valo 	__le16 reserved4;
6627ac9a364SKalle Valo 	u8 ofdm_basic_rates;
6637ac9a364SKalle Valo 	u8 cck_basic_rates;
6647ac9a364SKalle Valo 	__le16 assoc_id;
6657ac9a364SKalle Valo 	__le32 flags;
6667ac9a364SKalle Valo 	__le32 filter_flags;
6677ac9a364SKalle Valo 	__le16 channel;
6687ac9a364SKalle Valo 	__le16 reserved5;
6697ac9a364SKalle Valo } __packed;
6707ac9a364SKalle Valo 
6717ac9a364SKalle Valo struct il4965_rxon_cmd {
6727ac9a364SKalle Valo 	u8 node_addr[6];
6737ac9a364SKalle Valo 	__le16 reserved1;
6747ac9a364SKalle Valo 	u8 bssid_addr[6];
6757ac9a364SKalle Valo 	__le16 reserved2;
6767ac9a364SKalle Valo 	u8 wlap_bssid_addr[6];
6777ac9a364SKalle Valo 	__le16 reserved3;
6787ac9a364SKalle Valo 	u8 dev_type;
6797ac9a364SKalle Valo 	u8 air_propagation;
6807ac9a364SKalle Valo 	__le16 rx_chain;
6817ac9a364SKalle Valo 	u8 ofdm_basic_rates;
6827ac9a364SKalle Valo 	u8 cck_basic_rates;
6837ac9a364SKalle Valo 	__le16 assoc_id;
6847ac9a364SKalle Valo 	__le32 flags;
6857ac9a364SKalle Valo 	__le32 filter_flags;
6867ac9a364SKalle Valo 	__le16 channel;
6877ac9a364SKalle Valo 	u8 ofdm_ht_single_stream_basic_rates;
6887ac9a364SKalle Valo 	u8 ofdm_ht_dual_stream_basic_rates;
6897ac9a364SKalle Valo } __packed;
6907ac9a364SKalle Valo 
6917ac9a364SKalle Valo /* Create a common rxon cmd which will be typecast into the 3945 or 4965
6927ac9a364SKalle Valo  * specific rxon cmd, depending on where it is called from.
6937ac9a364SKalle Valo  */
6947ac9a364SKalle Valo struct il_rxon_cmd {
6957ac9a364SKalle Valo 	u8 node_addr[6];
6967ac9a364SKalle Valo 	__le16 reserved1;
6977ac9a364SKalle Valo 	u8 bssid_addr[6];
6987ac9a364SKalle Valo 	__le16 reserved2;
6997ac9a364SKalle Valo 	u8 wlap_bssid_addr[6];
7007ac9a364SKalle Valo 	__le16 reserved3;
7017ac9a364SKalle Valo 	u8 dev_type;
7027ac9a364SKalle Valo 	u8 air_propagation;
7037ac9a364SKalle Valo 	__le16 rx_chain;
7047ac9a364SKalle Valo 	u8 ofdm_basic_rates;
7057ac9a364SKalle Valo 	u8 cck_basic_rates;
7067ac9a364SKalle Valo 	__le16 assoc_id;
7077ac9a364SKalle Valo 	__le32 flags;
7087ac9a364SKalle Valo 	__le32 filter_flags;
7097ac9a364SKalle Valo 	__le16 channel;
7107ac9a364SKalle Valo 	u8 ofdm_ht_single_stream_basic_rates;
7117ac9a364SKalle Valo 	u8 ofdm_ht_dual_stream_basic_rates;
7127ac9a364SKalle Valo 	u8 reserved4;
7137ac9a364SKalle Valo 	u8 reserved5;
7147ac9a364SKalle Valo } __packed;
7157ac9a364SKalle Valo 
7167ac9a364SKalle Valo /*
7177ac9a364SKalle Valo  * C_RXON_ASSOC = 0x11 (command, has simple generic response)
7187ac9a364SKalle Valo  */
7197ac9a364SKalle Valo struct il3945_rxon_assoc_cmd {
7207ac9a364SKalle Valo 	__le32 flags;
7217ac9a364SKalle Valo 	__le32 filter_flags;
7227ac9a364SKalle Valo 	u8 ofdm_basic_rates;
7237ac9a364SKalle Valo 	u8 cck_basic_rates;
7247ac9a364SKalle Valo 	__le16 reserved;
7257ac9a364SKalle Valo } __packed;
7267ac9a364SKalle Valo 
7277ac9a364SKalle Valo struct il4965_rxon_assoc_cmd {
7287ac9a364SKalle Valo 	__le32 flags;
7297ac9a364SKalle Valo 	__le32 filter_flags;
7307ac9a364SKalle Valo 	u8 ofdm_basic_rates;
7317ac9a364SKalle Valo 	u8 cck_basic_rates;
7327ac9a364SKalle Valo 	u8 ofdm_ht_single_stream_basic_rates;
7337ac9a364SKalle Valo 	u8 ofdm_ht_dual_stream_basic_rates;
7347ac9a364SKalle Valo 	__le16 rx_chain_select_flags;
7357ac9a364SKalle Valo 	__le16 reserved;
7367ac9a364SKalle Valo } __packed;
7377ac9a364SKalle Valo 
7387ac9a364SKalle Valo #define IL_CONN_MAX_LISTEN_INTERVAL	10
7397ac9a364SKalle Valo #define IL_MAX_UCODE_BEACON_INTERVAL	4	/* 4096 */
7407ac9a364SKalle Valo #define IL39_MAX_UCODE_BEACON_INTERVAL	1	/* 1024 */
7417ac9a364SKalle Valo 
7427ac9a364SKalle Valo /*
7437ac9a364SKalle Valo  * C_RXON_TIMING = 0x14 (command, has simple generic response)
7447ac9a364SKalle Valo  */
7457ac9a364SKalle Valo struct il_rxon_time_cmd {
7467ac9a364SKalle Valo 	__le64 timestamp;
7477ac9a364SKalle Valo 	__le16 beacon_interval;
7487ac9a364SKalle Valo 	__le16 atim_win;
7497ac9a364SKalle Valo 	__le32 beacon_init_val;
7507ac9a364SKalle Valo 	__le16 listen_interval;
7517ac9a364SKalle Valo 	u8 dtim_period;
7527ac9a364SKalle Valo 	u8 delta_cp_bss_tbtts;
7537ac9a364SKalle Valo } __packed;
7547ac9a364SKalle Valo 
7557ac9a364SKalle Valo /*
7567ac9a364SKalle Valo  * C_CHANNEL_SWITCH = 0x72 (command, has simple generic response)
7577ac9a364SKalle Valo  */
7587ac9a364SKalle Valo struct il3945_channel_switch_cmd {
7597ac9a364SKalle Valo 	u8 band;
7607ac9a364SKalle Valo 	u8 expect_beacon;
7617ac9a364SKalle Valo 	__le16 channel;
7627ac9a364SKalle Valo 	__le32 rxon_flags;
7637ac9a364SKalle Valo 	__le32 rxon_filter_flags;
7647ac9a364SKalle Valo 	__le32 switch_time;
7657ac9a364SKalle Valo 	struct il3945_power_per_rate power[IL_MAX_RATES];
7667ac9a364SKalle Valo } __packed;
7677ac9a364SKalle Valo 
7687ac9a364SKalle Valo struct il4965_channel_switch_cmd {
7697ac9a364SKalle Valo 	u8 band;
7707ac9a364SKalle Valo 	u8 expect_beacon;
7717ac9a364SKalle Valo 	__le16 channel;
7727ac9a364SKalle Valo 	__le32 rxon_flags;
7737ac9a364SKalle Valo 	__le32 rxon_filter_flags;
7747ac9a364SKalle Valo 	__le32 switch_time;
7757ac9a364SKalle Valo 	struct il4965_tx_power_db tx_power;
7767ac9a364SKalle Valo } __packed;
7777ac9a364SKalle Valo 
7787ac9a364SKalle Valo /*
7797ac9a364SKalle Valo  * N_CHANNEL_SWITCH = 0x73 (notification only, not a command)
7807ac9a364SKalle Valo  */
7817ac9a364SKalle Valo struct il_csa_notification {
7827ac9a364SKalle Valo 	__le16 band;
7837ac9a364SKalle Valo 	__le16 channel;
7847ac9a364SKalle Valo 	__le32 status;		/* 0 - OK, 1 - fail */
7857ac9a364SKalle Valo } __packed;
7867ac9a364SKalle Valo 
7877ac9a364SKalle Valo /******************************************************************************
7887ac9a364SKalle Valo  * (2)
7897ac9a364SKalle Valo  * Quality-of-Service (QOS) Commands & Responses:
7907ac9a364SKalle Valo  *
7917ac9a364SKalle Valo  *****************************************************************************/
7927ac9a364SKalle Valo 
7937ac9a364SKalle Valo /**
7947ac9a364SKalle Valo  * struct il_ac_qos -- QOS timing params for C_QOS_PARAM
7957ac9a364SKalle Valo  * One for each of 4 EDCA access categories in struct il_qosparam_cmd
7967ac9a364SKalle Valo  *
7977ac9a364SKalle Valo  * @cw_min: Contention win, start value in numbers of slots.
7987ac9a364SKalle Valo  *          Should be a power-of-2, minus 1.  Device's default is 0x0f.
7997ac9a364SKalle Valo  * @cw_max: Contention win, max value in numbers of slots.
8007ac9a364SKalle Valo  *          Should be a power-of-2, minus 1.  Device's default is 0x3f.
8017ac9a364SKalle Valo  * @aifsn:  Number of slots in Arbitration Interframe Space (before
8027ac9a364SKalle Valo  *          performing random backoff timing prior to Tx).  Device default 1.
8037ac9a364SKalle Valo  * @edca_txop:  Length of Tx opportunity, in uSecs.  Device default is 0.
8047ac9a364SKalle Valo  *
8057ac9a364SKalle Valo  * Device will automatically increase contention win by (2*CW) + 1 for each
8067ac9a364SKalle Valo  * transmission retry.  Device uses cw_max as a bit mask, ANDed with new CW
8077ac9a364SKalle Valo  * value, to cap the CW value.
8087ac9a364SKalle Valo  */
8097ac9a364SKalle Valo struct il_ac_qos {
8107ac9a364SKalle Valo 	__le16 cw_min;
8117ac9a364SKalle Valo 	__le16 cw_max;
8127ac9a364SKalle Valo 	u8 aifsn;
8137ac9a364SKalle Valo 	u8 reserved1;
8147ac9a364SKalle Valo 	__le16 edca_txop;
8157ac9a364SKalle Valo } __packed;
8167ac9a364SKalle Valo 
8177ac9a364SKalle Valo /* QoS flags defines */
8187ac9a364SKalle Valo #define QOS_PARAM_FLG_UPDATE_EDCA_MSK	cpu_to_le32(0x01)
8197ac9a364SKalle Valo #define QOS_PARAM_FLG_TGN_MSK		cpu_to_le32(0x02)
8207ac9a364SKalle Valo #define QOS_PARAM_FLG_TXOP_TYPE_MSK	cpu_to_le32(0x10)
8217ac9a364SKalle Valo 
8227ac9a364SKalle Valo /* Number of Access Categories (AC) (EDCA), queues 0..3 */
8237ac9a364SKalle Valo #define AC_NUM                4
8247ac9a364SKalle Valo 
8257ac9a364SKalle Valo /*
8267ac9a364SKalle Valo  * C_QOS_PARAM = 0x13 (command, has simple generic response)
8277ac9a364SKalle Valo  *
8287ac9a364SKalle Valo  * This command sets up timings for each of the 4 prioritized EDCA Tx FIFOs
8297ac9a364SKalle Valo  * 0: Background, 1: Best Effort, 2: Video, 3: Voice.
8307ac9a364SKalle Valo  */
8317ac9a364SKalle Valo struct il_qosparam_cmd {
8327ac9a364SKalle Valo 	__le32 qos_flags;
8337ac9a364SKalle Valo 	struct il_ac_qos ac[AC_NUM];
8347ac9a364SKalle Valo } __packed;
8357ac9a364SKalle Valo 
8367ac9a364SKalle Valo /******************************************************************************
8377ac9a364SKalle Valo  * (3)
8387ac9a364SKalle Valo  * Add/Modify Stations Commands & Responses:
8397ac9a364SKalle Valo  *
8407ac9a364SKalle Valo  *****************************************************************************/
8417ac9a364SKalle Valo /*
8427ac9a364SKalle Valo  * Multi station support
8437ac9a364SKalle Valo  */
8447ac9a364SKalle Valo 
8457ac9a364SKalle Valo /* Special, dedicated locations within device's station table */
8467ac9a364SKalle Valo #define	IL_AP_ID		0
8477ac9a364SKalle Valo #define	IL_STA_ID		2
8487ac9a364SKalle Valo #define	IL3945_BROADCAST_ID	24
8497ac9a364SKalle Valo #define IL3945_STATION_COUNT	25
8507ac9a364SKalle Valo #define IL4965_BROADCAST_ID	31
8517ac9a364SKalle Valo #define	IL4965_STATION_COUNT	32
8527ac9a364SKalle Valo 
8537ac9a364SKalle Valo #define	IL_STATION_COUNT	32	/* MAX(3945,4965) */
8547ac9a364SKalle Valo #define	IL_INVALID_STATION	255
8557ac9a364SKalle Valo 
8567ac9a364SKalle Valo #define STA_FLG_TX_RATE_MSK		cpu_to_le32(1 << 2)
8577ac9a364SKalle Valo #define STA_FLG_PWR_SAVE_MSK		cpu_to_le32(1 << 8)
8587ac9a364SKalle Valo #define STA_FLG_RTS_MIMO_PROT_MSK	cpu_to_le32(1 << 17)
8597ac9a364SKalle Valo #define STA_FLG_AGG_MPDU_8US_MSK	cpu_to_le32(1 << 18)
8607ac9a364SKalle Valo #define STA_FLG_MAX_AGG_SIZE_POS	(19)
8617ac9a364SKalle Valo #define STA_FLG_MAX_AGG_SIZE_MSK	cpu_to_le32(3 << 19)
8627ac9a364SKalle Valo #define STA_FLG_HT40_EN_MSK		cpu_to_le32(1 << 21)
8637ac9a364SKalle Valo #define STA_FLG_MIMO_DIS_MSK		cpu_to_le32(1 << 22)
8647ac9a364SKalle Valo #define STA_FLG_AGG_MPDU_DENSITY_POS	(23)
8657ac9a364SKalle Valo #define STA_FLG_AGG_MPDU_DENSITY_MSK	cpu_to_le32(7 << 23)
8667ac9a364SKalle Valo 
8677ac9a364SKalle Valo /* Use in mode field.  1: modify existing entry, 0: add new station entry */
8687ac9a364SKalle Valo #define STA_CONTROL_MODIFY_MSK		0x01
8697ac9a364SKalle Valo 
8707ac9a364SKalle Valo /* key flags __le16*/
8717ac9a364SKalle Valo #define STA_KEY_FLG_ENCRYPT_MSK	cpu_to_le16(0x0007)
8727ac9a364SKalle Valo #define STA_KEY_FLG_NO_ENC	cpu_to_le16(0x0000)
8737ac9a364SKalle Valo #define STA_KEY_FLG_WEP		cpu_to_le16(0x0001)
8747ac9a364SKalle Valo #define STA_KEY_FLG_CCMP	cpu_to_le16(0x0002)
8757ac9a364SKalle Valo #define STA_KEY_FLG_TKIP	cpu_to_le16(0x0003)
8767ac9a364SKalle Valo 
8777ac9a364SKalle Valo #define STA_KEY_FLG_KEYID_POS	8
8787ac9a364SKalle Valo #define STA_KEY_FLG_INVALID	cpu_to_le16(0x0800)
8797ac9a364SKalle Valo /* wep key is either from global key (0) or from station info array (1) */
8807ac9a364SKalle Valo #define STA_KEY_FLG_MAP_KEY_MSK	cpu_to_le16(0x0008)
8817ac9a364SKalle Valo 
8827ac9a364SKalle Valo /* wep key in STA: 5-bytes (0) or 13-bytes (1) */
8837ac9a364SKalle Valo #define STA_KEY_FLG_KEY_SIZE_MSK	cpu_to_le16(0x1000)
8847ac9a364SKalle Valo #define STA_KEY_MULTICAST_MSK		cpu_to_le16(0x4000)
8857ac9a364SKalle Valo #define STA_KEY_MAX_NUM		8
8867ac9a364SKalle Valo 
8877ac9a364SKalle Valo /* Flags indicate whether to modify vs. don't change various station params */
8887ac9a364SKalle Valo #define	STA_MODIFY_KEY_MASK		0x01
8897ac9a364SKalle Valo #define	STA_MODIFY_TID_DISABLE_TX	0x02
8907ac9a364SKalle Valo #define	STA_MODIFY_TX_RATE_MSK		0x04
8917ac9a364SKalle Valo #define STA_MODIFY_ADDBA_TID_MSK	0x08
8927ac9a364SKalle Valo #define STA_MODIFY_DELBA_TID_MSK	0x10
8937ac9a364SKalle Valo #define STA_MODIFY_SLEEP_TX_COUNT_MSK	0x20
8947ac9a364SKalle Valo 
8957ac9a364SKalle Valo /* Receiver address (actually, Rx station's idx into station table),
8967ac9a364SKalle Valo  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
8977ac9a364SKalle Valo #define BUILD_RAxTID(sta_id, tid)	(((sta_id) << 4) + (tid))
8987ac9a364SKalle Valo 
8997ac9a364SKalle Valo struct il4965_keyinfo {
9007ac9a364SKalle Valo 	__le16 key_flags;
9017ac9a364SKalle Valo 	u8 tkip_rx_tsc_byte2;	/* TSC[2] for key mix ph1 detection */
9027ac9a364SKalle Valo 	u8 reserved1;
9037ac9a364SKalle Valo 	__le16 tkip_rx_ttak[5];	/* 10-byte unicast TKIP TTAK */
9047ac9a364SKalle Valo 	u8 key_offset;
9057ac9a364SKalle Valo 	u8 reserved2;
9067ac9a364SKalle Valo 	u8 key[16];		/* 16-byte unicast decryption key */
9077ac9a364SKalle Valo } __packed;
9087ac9a364SKalle Valo 
9097ac9a364SKalle Valo /**
9107ac9a364SKalle Valo  * struct sta_id_modify
9117ac9a364SKalle Valo  * @addr[ETH_ALEN]: station's MAC address
9127ac9a364SKalle Valo  * @sta_id: idx of station in uCode's station table
9137ac9a364SKalle Valo  * @modify_mask: STA_MODIFY_*, 1: modify, 0: don't change
9147ac9a364SKalle Valo  *
9157ac9a364SKalle Valo  * Driver selects unused table idx when adding new station,
9167ac9a364SKalle Valo  * or the idx to a pre-existing station entry when modifying that station.
9177ac9a364SKalle Valo  * Some idxes have special purposes (IL_AP_ID, idx 0, is for AP).
9187ac9a364SKalle Valo  *
9197ac9a364SKalle Valo  * modify_mask flags select which parameters to modify vs. leave alone.
9207ac9a364SKalle Valo  */
9217ac9a364SKalle Valo struct sta_id_modify {
9227ac9a364SKalle Valo 	u8 addr[ETH_ALEN];
9237ac9a364SKalle Valo 	__le16 reserved1;
9247ac9a364SKalle Valo 	u8 sta_id;
9257ac9a364SKalle Valo 	u8 modify_mask;
9267ac9a364SKalle Valo 	__le16 reserved2;
9277ac9a364SKalle Valo } __packed;
9287ac9a364SKalle Valo 
9297ac9a364SKalle Valo /*
9307ac9a364SKalle Valo  * C_ADD_STA = 0x18 (command)
9317ac9a364SKalle Valo  *
9327ac9a364SKalle Valo  * The device contains an internal table of per-station information,
9337ac9a364SKalle Valo  * with info on security keys, aggregation parameters, and Tx rates for
9347ac9a364SKalle Valo  * initial Tx attempt and any retries (4965 devices uses
9357ac9a364SKalle Valo  * C_TX_LINK_QUALITY_CMD,
9367ac9a364SKalle Valo  * 3945 uses C_RATE_SCALE to set up rate tables).
9377ac9a364SKalle Valo  *
9387ac9a364SKalle Valo  * C_ADD_STA sets up the table entry for one station, either creating
9397ac9a364SKalle Valo  * a new entry, or modifying a pre-existing one.
9407ac9a364SKalle Valo  *
9417ac9a364SKalle Valo  * NOTE:  RXON command (without "associated" bit set) wipes the station table
9427ac9a364SKalle Valo  *        clean.  Moving into RF_KILL state does this also.  Driver must set up
9437ac9a364SKalle Valo  *        new station table before transmitting anything on the RXON channel
9447ac9a364SKalle Valo  *        (except active scans or active measurements; those commands carry
9457ac9a364SKalle Valo  *        their own txpower/rate setup data).
9467ac9a364SKalle Valo  *
9477ac9a364SKalle Valo  *        When getting started on a new channel, driver must set up the
9487ac9a364SKalle Valo  *        IL_BROADCAST_ID entry (last entry in the table).  For a client
9497ac9a364SKalle Valo  *        station in a BSS, once an AP is selected, driver sets up the AP STA
9507ac9a364SKalle Valo  *        in the IL_AP_ID entry (1st entry in the table).  BROADCAST and AP
9517ac9a364SKalle Valo  *        are all that are needed for a BSS client station.  If the device is
9527ac9a364SKalle Valo  *        used as AP, or in an IBSS network, driver must set up station table
9537ac9a364SKalle Valo  *        entries for all STAs in network, starting with idx IL_STA_ID.
9547ac9a364SKalle Valo  */
9557ac9a364SKalle Valo 
9567ac9a364SKalle Valo struct il3945_addsta_cmd {
9577ac9a364SKalle Valo 	u8 mode;		/* 1: modify existing, 0: add new station */
9587ac9a364SKalle Valo 	u8 reserved[3];
9597ac9a364SKalle Valo 	struct sta_id_modify sta;
9607ac9a364SKalle Valo 	struct il4965_keyinfo key;
9617ac9a364SKalle Valo 	__le32 station_flags;	/* STA_FLG_* */
9627ac9a364SKalle Valo 	__le32 station_flags_msk;	/* STA_FLG_* */
9637ac9a364SKalle Valo 
9647ac9a364SKalle Valo 	/* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
9657ac9a364SKalle Valo 	 * corresponding to bit (e.g. bit 5 controls TID 5).
9667ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
9677ac9a364SKalle Valo 	__le16 tid_disable_tx;
9687ac9a364SKalle Valo 
9697ac9a364SKalle Valo 	__le16 rate_n_flags;
9707ac9a364SKalle Valo 
9717ac9a364SKalle Valo 	/* TID for which to add block-ack support.
9727ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
9737ac9a364SKalle Valo 	u8 add_immediate_ba_tid;
9747ac9a364SKalle Valo 
9757ac9a364SKalle Valo 	/* TID for which to remove block-ack support.
9767ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
9777ac9a364SKalle Valo 	u8 remove_immediate_ba_tid;
9787ac9a364SKalle Valo 
9797ac9a364SKalle Valo 	/* Starting Sequence Number for added block-ack support.
9807ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
9817ac9a364SKalle Valo 	__le16 add_immediate_ba_ssn;
9827ac9a364SKalle Valo } __packed;
9837ac9a364SKalle Valo 
9847ac9a364SKalle Valo struct il4965_addsta_cmd {
9857ac9a364SKalle Valo 	u8 mode;		/* 1: modify existing, 0: add new station */
9867ac9a364SKalle Valo 	u8 reserved[3];
9877ac9a364SKalle Valo 	struct sta_id_modify sta;
9887ac9a364SKalle Valo 	struct il4965_keyinfo key;
9897ac9a364SKalle Valo 	__le32 station_flags;	/* STA_FLG_* */
9907ac9a364SKalle Valo 	__le32 station_flags_msk;	/* STA_FLG_* */
9917ac9a364SKalle Valo 
9927ac9a364SKalle Valo 	/* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
9937ac9a364SKalle Valo 	 * corresponding to bit (e.g. bit 5 controls TID 5).
9947ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
9957ac9a364SKalle Valo 	__le16 tid_disable_tx;
9967ac9a364SKalle Valo 
9977ac9a364SKalle Valo 	__le16 reserved1;
9987ac9a364SKalle Valo 
9997ac9a364SKalle Valo 	/* TID for which to add block-ack support.
10007ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
10017ac9a364SKalle Valo 	u8 add_immediate_ba_tid;
10027ac9a364SKalle Valo 
10037ac9a364SKalle Valo 	/* TID for which to remove block-ack support.
10047ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
10057ac9a364SKalle Valo 	u8 remove_immediate_ba_tid;
10067ac9a364SKalle Valo 
10077ac9a364SKalle Valo 	/* Starting Sequence Number for added block-ack support.
10087ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
10097ac9a364SKalle Valo 	__le16 add_immediate_ba_ssn;
10107ac9a364SKalle Valo 
10117ac9a364SKalle Valo 	/*
10127ac9a364SKalle Valo 	 * Number of packets OK to transmit to station even though
10137ac9a364SKalle Valo 	 * it is asleep -- used to synchronise PS-poll and u-APSD
10147ac9a364SKalle Valo 	 * responses while ucode keeps track of STA sleep state.
10157ac9a364SKalle Valo 	 */
10167ac9a364SKalle Valo 	__le16 sleep_tx_count;
10177ac9a364SKalle Valo 
10187ac9a364SKalle Valo 	__le16 reserved2;
10197ac9a364SKalle Valo } __packed;
10207ac9a364SKalle Valo 
10217ac9a364SKalle Valo /* Wrapper struct for 3945 and 4965 addsta_cmd structures */
10227ac9a364SKalle Valo struct il_addsta_cmd {
10237ac9a364SKalle Valo 	u8 mode;		/* 1: modify existing, 0: add new station */
10247ac9a364SKalle Valo 	u8 reserved[3];
10257ac9a364SKalle Valo 	struct sta_id_modify sta;
10267ac9a364SKalle Valo 	struct il4965_keyinfo key;
10277ac9a364SKalle Valo 	__le32 station_flags;	/* STA_FLG_* */
10287ac9a364SKalle Valo 	__le32 station_flags_msk;	/* STA_FLG_* */
10297ac9a364SKalle Valo 
10307ac9a364SKalle Valo 	/* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
10317ac9a364SKalle Valo 	 * corresponding to bit (e.g. bit 5 controls TID 5).
10327ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
10337ac9a364SKalle Valo 	__le16 tid_disable_tx;
10347ac9a364SKalle Valo 
10357ac9a364SKalle Valo 	__le16 rate_n_flags;	/* 3945 only */
10367ac9a364SKalle Valo 
10377ac9a364SKalle Valo 	/* TID for which to add block-ack support.
10387ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
10397ac9a364SKalle Valo 	u8 add_immediate_ba_tid;
10407ac9a364SKalle Valo 
10417ac9a364SKalle Valo 	/* TID for which to remove block-ack support.
10427ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
10437ac9a364SKalle Valo 	u8 remove_immediate_ba_tid;
10447ac9a364SKalle Valo 
10457ac9a364SKalle Valo 	/* Starting Sequence Number for added block-ack support.
10467ac9a364SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
10477ac9a364SKalle Valo 	__le16 add_immediate_ba_ssn;
10487ac9a364SKalle Valo 
10497ac9a364SKalle Valo 	/*
10507ac9a364SKalle Valo 	 * Number of packets OK to transmit to station even though
10517ac9a364SKalle Valo 	 * it is asleep -- used to synchronise PS-poll and u-APSD
10527ac9a364SKalle Valo 	 * responses while ucode keeps track of STA sleep state.
10537ac9a364SKalle Valo 	 */
10547ac9a364SKalle Valo 	__le16 sleep_tx_count;
10557ac9a364SKalle Valo 
10567ac9a364SKalle Valo 	__le16 reserved2;
10577ac9a364SKalle Valo } __packed;
10587ac9a364SKalle Valo 
10597ac9a364SKalle Valo #define ADD_STA_SUCCESS_MSK		0x1
10607ac9a364SKalle Valo #define ADD_STA_NO_ROOM_IN_TBL	0x2
10617ac9a364SKalle Valo #define ADD_STA_NO_BLOCK_ACK_RESOURCE	0x4
10627ac9a364SKalle Valo #define ADD_STA_MODIFY_NON_EXIST_STA	0x8
10637ac9a364SKalle Valo /*
10647ac9a364SKalle Valo  * C_ADD_STA = 0x18 (response)
10657ac9a364SKalle Valo  */
10667ac9a364SKalle Valo struct il_add_sta_resp {
10677ac9a364SKalle Valo 	u8 status;		/* ADD_STA_* */
10687ac9a364SKalle Valo } __packed;
10697ac9a364SKalle Valo 
10707ac9a364SKalle Valo #define REM_STA_SUCCESS_MSK              0x1
10717ac9a364SKalle Valo /*
10727ac9a364SKalle Valo  *  C_REM_STA = 0x19 (response)
10737ac9a364SKalle Valo  */
10747ac9a364SKalle Valo struct il_rem_sta_resp {
10757ac9a364SKalle Valo 	u8 status;
10767ac9a364SKalle Valo } __packed;
10777ac9a364SKalle Valo 
10787ac9a364SKalle Valo /*
10797ac9a364SKalle Valo  *  C_REM_STA = 0x19 (command)
10807ac9a364SKalle Valo  */
10817ac9a364SKalle Valo struct il_rem_sta_cmd {
10827ac9a364SKalle Valo 	u8 num_sta;		/* number of removed stations */
10837ac9a364SKalle Valo 	u8 reserved[3];
10847ac9a364SKalle Valo 	u8 addr[ETH_ALEN];	/* MAC addr of the first station */
10857ac9a364SKalle Valo 	u8 reserved2[2];
10867ac9a364SKalle Valo } __packed;
10877ac9a364SKalle Valo 
10887ac9a364SKalle Valo #define IL_TX_FIFO_BK_MSK		cpu_to_le32(BIT(0))
10897ac9a364SKalle Valo #define IL_TX_FIFO_BE_MSK		cpu_to_le32(BIT(1))
10907ac9a364SKalle Valo #define IL_TX_FIFO_VI_MSK		cpu_to_le32(BIT(2))
10917ac9a364SKalle Valo #define IL_TX_FIFO_VO_MSK		cpu_to_le32(BIT(3))
10927ac9a364SKalle Valo #define IL_AGG_TX_QUEUE_MSK		cpu_to_le32(0xffc00)
10937ac9a364SKalle Valo 
10947ac9a364SKalle Valo #define IL_DROP_SINGLE		0
10957ac9a364SKalle Valo #define IL_DROP_SELECTED	1
10967ac9a364SKalle Valo #define IL_DROP_ALL		2
10977ac9a364SKalle Valo 
10987ac9a364SKalle Valo /*
10997ac9a364SKalle Valo  * REPLY_WEP_KEY = 0x20
11007ac9a364SKalle Valo  */
11017ac9a364SKalle Valo struct il_wep_key {
11027ac9a364SKalle Valo 	u8 key_idx;
11037ac9a364SKalle Valo 	u8 key_offset;
11047ac9a364SKalle Valo 	u8 reserved1[2];
11057ac9a364SKalle Valo 	u8 key_size;
11067ac9a364SKalle Valo 	u8 reserved2[3];
11077ac9a364SKalle Valo 	u8 key[16];
11087ac9a364SKalle Valo } __packed;
11097ac9a364SKalle Valo 
11107ac9a364SKalle Valo struct il_wep_cmd {
11117ac9a364SKalle Valo 	u8 num_keys;
11127ac9a364SKalle Valo 	u8 global_key_type;
11137ac9a364SKalle Valo 	u8 flags;
11147ac9a364SKalle Valo 	u8 reserved;
11158863b121SGustavo A. R. Silva 	struct il_wep_key key[];
11167ac9a364SKalle Valo } __packed;
11177ac9a364SKalle Valo 
11187ac9a364SKalle Valo #define WEP_KEY_WEP_TYPE 1
11197ac9a364SKalle Valo #define WEP_KEYS_MAX 4
11207ac9a364SKalle Valo #define WEP_INVALID_OFFSET 0xff
11217ac9a364SKalle Valo #define WEP_KEY_LEN_64 5
11227ac9a364SKalle Valo #define WEP_KEY_LEN_128 13
11237ac9a364SKalle Valo 
11247ac9a364SKalle Valo /******************************************************************************
11257ac9a364SKalle Valo  * (4)
11267ac9a364SKalle Valo  * Rx Responses:
11277ac9a364SKalle Valo  *
11287ac9a364SKalle Valo  *****************************************************************************/
11297ac9a364SKalle Valo 
11307ac9a364SKalle Valo #define RX_RES_STATUS_NO_CRC32_ERROR	cpu_to_le32(1 << 0)
11317ac9a364SKalle Valo #define RX_RES_STATUS_NO_RXE_OVERFLOW	cpu_to_le32(1 << 1)
11327ac9a364SKalle Valo 
11337ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_BAND_24_MSK	cpu_to_le16(1 << 0)
11347ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_MOD_CCK_MSK		cpu_to_le16(1 << 1)
11357ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK	cpu_to_le16(1 << 2)
11367ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK	cpu_to_le16(1 << 3)
11377ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_ANTENNA_MSK		0x70
11387ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_ANTENNA_POS		4
11397ac9a364SKalle Valo #define RX_RES_PHY_FLAGS_AGG_MSK	cpu_to_le16(1 << 7)
11407ac9a364SKalle Valo 
11417ac9a364SKalle Valo #define RX_RES_STATUS_SEC_TYPE_MSK	(0x7 << 8)
11427ac9a364SKalle Valo #define RX_RES_STATUS_SEC_TYPE_NONE	(0x0 << 8)
11437ac9a364SKalle Valo #define RX_RES_STATUS_SEC_TYPE_WEP	(0x1 << 8)
11447ac9a364SKalle Valo #define RX_RES_STATUS_SEC_TYPE_CCMP	(0x2 << 8)
11457ac9a364SKalle Valo #define RX_RES_STATUS_SEC_TYPE_TKIP	(0x3 << 8)
11467ac9a364SKalle Valo #define	RX_RES_STATUS_SEC_TYPE_ERR	(0x7 << 8)
11477ac9a364SKalle Valo 
11487ac9a364SKalle Valo #define RX_RES_STATUS_STATION_FOUND	(1<<6)
11497ac9a364SKalle Valo #define RX_RES_STATUS_NO_STATION_INFO_MISMATCH	(1<<7)
11507ac9a364SKalle Valo 
11517ac9a364SKalle Valo #define RX_RES_STATUS_DECRYPT_TYPE_MSK	(0x3 << 11)
11527ac9a364SKalle Valo #define RX_RES_STATUS_NOT_DECRYPT	(0x0 << 11)
11537ac9a364SKalle Valo #define RX_RES_STATUS_DECRYPT_OK	(0x3 << 11)
11547ac9a364SKalle Valo #define RX_RES_STATUS_BAD_ICV_MIC	(0x1 << 11)
11557ac9a364SKalle Valo #define RX_RES_STATUS_BAD_KEY_TTAK	(0x2 << 11)
11567ac9a364SKalle Valo 
11577ac9a364SKalle Valo #define RX_MPDU_RES_STATUS_ICV_OK	(0x20)
11587ac9a364SKalle Valo #define RX_MPDU_RES_STATUS_MIC_OK	(0x40)
11597ac9a364SKalle Valo #define RX_MPDU_RES_STATUS_TTAK_OK	(1 << 7)
11607ac9a364SKalle Valo #define RX_MPDU_RES_STATUS_DEC_DONE_MSK	(0x800)
11617ac9a364SKalle Valo 
11627ac9a364SKalle Valo struct il3945_rx_frame_stats {
11637ac9a364SKalle Valo 	u8 phy_count;
11647ac9a364SKalle Valo 	u8 id;
11657ac9a364SKalle Valo 	u8 rssi;
11667ac9a364SKalle Valo 	u8 agc;
11677ac9a364SKalle Valo 	__le16 sig_avg;
11687ac9a364SKalle Valo 	__le16 noise_diff;
11698863b121SGustavo A. R. Silva 	u8 payload[];
11707ac9a364SKalle Valo } __packed;
11717ac9a364SKalle Valo 
11727ac9a364SKalle Valo struct il3945_rx_frame_hdr {
11737ac9a364SKalle Valo 	__le16 channel;
11747ac9a364SKalle Valo 	__le16 phy_flags;
11757ac9a364SKalle Valo 	u8 reserved1;
11767ac9a364SKalle Valo 	u8 rate;
11777ac9a364SKalle Valo 	__le16 len;
11788863b121SGustavo A. R. Silva 	u8 payload[];
11797ac9a364SKalle Valo } __packed;
11807ac9a364SKalle Valo 
11817ac9a364SKalle Valo struct il3945_rx_frame_end {
11827ac9a364SKalle Valo 	__le32 status;
11837ac9a364SKalle Valo 	__le64 timestamp;
11847ac9a364SKalle Valo 	__le32 beacon_timestamp;
11857ac9a364SKalle Valo } __packed;
11867ac9a364SKalle Valo 
11877ac9a364SKalle Valo /*
11887ac9a364SKalle Valo  * N_3945_RX = 0x1b (response only, not a command)
11897ac9a364SKalle Valo  *
11907ac9a364SKalle Valo  * NOTE:  DO NOT dereference from casts to this structure
11917ac9a364SKalle Valo  * It is provided only for calculating minimum data set size.
11927ac9a364SKalle Valo  * The actual offsets of the hdr and end are dynamic based on
11937ac9a364SKalle Valo  * stats.phy_count
11947ac9a364SKalle Valo  */
11957ac9a364SKalle Valo struct il3945_rx_frame {
11967ac9a364SKalle Valo 	struct il3945_rx_frame_stats stats;
11977ac9a364SKalle Valo 	struct il3945_rx_frame_hdr hdr;
11987ac9a364SKalle Valo 	struct il3945_rx_frame_end end;
11997ac9a364SKalle Valo } __packed;
12007ac9a364SKalle Valo 
12017ac9a364SKalle Valo #define IL39_RX_FRAME_SIZE	(4 + sizeof(struct il3945_rx_frame))
12027ac9a364SKalle Valo 
12037ac9a364SKalle Valo /* Fixed (non-configurable) rx data from phy */
12047ac9a364SKalle Valo 
12057ac9a364SKalle Valo #define IL49_RX_RES_PHY_CNT 14
12067ac9a364SKalle Valo #define IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET	(4)
12077ac9a364SKalle Valo #define IL49_RX_PHY_FLAGS_ANTENNAE_MASK	(0x70)
12087ac9a364SKalle Valo #define IL49_AGC_DB_MASK			(0x3f80)	/* MASK(7,13) */
12097ac9a364SKalle Valo #define IL49_AGC_DB_POS			(7)
12107ac9a364SKalle Valo struct il4965_rx_non_cfg_phy {
12117ac9a364SKalle Valo 	__le16 ant_selection;	/* ant A bit 4, ant B bit 5, ant C bit 6 */
12127ac9a364SKalle Valo 	__le16 agc_info;	/* agc code 0:6, agc dB 7:13, reserved 14:15 */
12137ac9a364SKalle Valo 	u8 rssi_info[6];	/* we use even entries, 0/2/4 for A/B/C rssi */
12148863b121SGustavo A. R. Silva 	u8 pad[];
12157ac9a364SKalle Valo } __packed;
12167ac9a364SKalle Valo 
12177ac9a364SKalle Valo /*
12187ac9a364SKalle Valo  * N_RX = 0xc3 (response only, not a command)
12197ac9a364SKalle Valo  * Used only for legacy (non 11n) frames.
12207ac9a364SKalle Valo  */
12217ac9a364SKalle Valo struct il_rx_phy_res {
12227ac9a364SKalle Valo 	u8 non_cfg_phy_cnt;	/* non configurable DSP phy data byte count */
12237ac9a364SKalle Valo 	u8 cfg_phy_cnt;		/* configurable DSP phy data byte count */
12247ac9a364SKalle Valo 	u8 stat_id;		/* configurable DSP phy data set ID */
12257ac9a364SKalle Valo 	u8 reserved1;
12267ac9a364SKalle Valo 	__le64 timestamp;	/* TSF at on air rise */
12277ac9a364SKalle Valo 	__le32 beacon_time_stamp;	/* beacon at on-air rise */
12287ac9a364SKalle Valo 	__le16 phy_flags;	/* general phy flags: band, modulation, ... */
12297ac9a364SKalle Valo 	__le16 channel;		/* channel number */
12307ac9a364SKalle Valo 	u8 non_cfg_phy_buf[32];	/* for various implementations of non_cfg_phy */
12317ac9a364SKalle Valo 	__le32 rate_n_flags;	/* RATE_MCS_* */
12327ac9a364SKalle Valo 	__le16 byte_count;	/* frame's byte-count */
12337ac9a364SKalle Valo 	__le16 frame_time;	/* frame's time on the air */
12347ac9a364SKalle Valo } __packed;
12357ac9a364SKalle Valo 
12367ac9a364SKalle Valo struct il_rx_mpdu_res_start {
12377ac9a364SKalle Valo 	__le16 byte_count;
12387ac9a364SKalle Valo 	__le16 reserved;
12397ac9a364SKalle Valo } __packed;
12407ac9a364SKalle Valo 
12417ac9a364SKalle Valo /******************************************************************************
12427ac9a364SKalle Valo  * (5)
12437ac9a364SKalle Valo  * Tx Commands & Responses:
12447ac9a364SKalle Valo  *
12457ac9a364SKalle Valo  * Driver must place each C_TX command into one of the prioritized Tx
12467ac9a364SKalle Valo  * queues in host DRAM, shared between driver and device (see comments for
12477ac9a364SKalle Valo  * SCD registers and Tx/Rx Queues).  When the device's Tx scheduler and uCode
12487ac9a364SKalle Valo  * are preparing to transmit, the device pulls the Tx command over the PCI
12497ac9a364SKalle Valo  * bus via one of the device's Tx DMA channels, to fill an internal FIFO
12507ac9a364SKalle Valo  * from which data will be transmitted.
12517ac9a364SKalle Valo  *
12527ac9a364SKalle Valo  * uCode handles all timing and protocol related to control frames
12537ac9a364SKalle Valo  * (RTS/CTS/ACK), based on flags in the Tx command.  uCode and Tx scheduler
12547ac9a364SKalle Valo  * handle reception of block-acks; uCode updates the host driver via
12557ac9a364SKalle Valo  * N_COMPRESSED_BA.
12567ac9a364SKalle Valo  *
12577ac9a364SKalle Valo  * uCode handles retrying Tx when an ACK is expected but not received.
12587ac9a364SKalle Valo  * This includes trying lower data rates than the one requested in the Tx
12597ac9a364SKalle Valo  * command, as set up by the C_RATE_SCALE (for 3945) or
12607ac9a364SKalle Valo  * C_TX_LINK_QUALITY_CMD (4965).
12617ac9a364SKalle Valo  *
12627ac9a364SKalle Valo  * Driver sets up transmit power for various rates via C_TX_PWR_TBL.
12637ac9a364SKalle Valo  * This command must be executed after every RXON command, before Tx can occur.
12647ac9a364SKalle Valo  *****************************************************************************/
12657ac9a364SKalle Valo 
12667ac9a364SKalle Valo /* C_TX Tx flags field */
12677ac9a364SKalle Valo 
12687ac9a364SKalle Valo /*
12697ac9a364SKalle Valo  * 1: Use Request-To-Send protocol before this frame.
12707ac9a364SKalle Valo  * Mutually exclusive vs. TX_CMD_FLG_CTS_MSK.
12717ac9a364SKalle Valo  */
12727ac9a364SKalle Valo #define TX_CMD_FLG_RTS_MSK cpu_to_le32(1 << 1)
12737ac9a364SKalle Valo 
12747ac9a364SKalle Valo /*
12757ac9a364SKalle Valo  * 1: Transmit Clear-To-Send to self before this frame.
12767ac9a364SKalle Valo  * Driver should set this for AUTH/DEAUTH/ASSOC-REQ/REASSOC mgmnt frames.
12777ac9a364SKalle Valo  * Mutually exclusive vs. TX_CMD_FLG_RTS_MSK.
12787ac9a364SKalle Valo  */
12797ac9a364SKalle Valo #define TX_CMD_FLG_CTS_MSK cpu_to_le32(1 << 2)
12807ac9a364SKalle Valo 
12817ac9a364SKalle Valo /* 1: Expect ACK from receiving station
12827ac9a364SKalle Valo  * 0: Don't expect ACK (MAC header's duration field s/b 0)
12837ac9a364SKalle Valo  * Set this for unicast frames, but not broadcast/multicast. */
12847ac9a364SKalle Valo #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
12857ac9a364SKalle Valo 
12867ac9a364SKalle Valo /* For 4965 devices:
12877ac9a364SKalle Valo  * 1: Use rate scale table (see C_TX_LINK_QUALITY_CMD).
12887ac9a364SKalle Valo  *    Tx command's initial_rate_idx indicates first rate to try;
12897ac9a364SKalle Valo  *    uCode walks through table for additional Tx attempts.
12907ac9a364SKalle Valo  * 0: Use Tx rate/MCS from Tx command's rate_n_flags field.
12917ac9a364SKalle Valo  *    This rate will be used for all Tx attempts; it will not be scaled. */
12927ac9a364SKalle Valo #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
12937ac9a364SKalle Valo 
12947ac9a364SKalle Valo /* 1: Expect immediate block-ack.
12957ac9a364SKalle Valo  * Set when Txing a block-ack request frame.  Also set TX_CMD_FLG_ACK_MSK. */
12967ac9a364SKalle Valo #define TX_CMD_FLG_IMM_BA_RSP_MASK  cpu_to_le32(1 << 6)
12977ac9a364SKalle Valo 
12987ac9a364SKalle Valo /*
12997ac9a364SKalle Valo  * 1: Frame requires full Tx-Op protection.
13007ac9a364SKalle Valo  * Set this if either RTS or CTS Tx Flag gets set.
13017ac9a364SKalle Valo  */
13027ac9a364SKalle Valo #define TX_CMD_FLG_FULL_TXOP_PROT_MSK cpu_to_le32(1 << 7)
13037ac9a364SKalle Valo 
13047ac9a364SKalle Valo /* Tx antenna selection field; used only for 3945, reserved (0) for 4965 devices.
13057ac9a364SKalle Valo  * Set field to "0" to allow 3945 uCode to select antenna (normal usage). */
13067ac9a364SKalle Valo #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
13077ac9a364SKalle Valo #define TX_CMD_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
13087ac9a364SKalle Valo #define TX_CMD_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
13097ac9a364SKalle Valo 
13107ac9a364SKalle Valo /* 1: uCode overrides sequence control field in MAC header.
13117ac9a364SKalle Valo  * 0: Driver provides sequence control field in MAC header.
13127ac9a364SKalle Valo  * Set this for management frames, non-QOS data frames, non-unicast frames,
13137ac9a364SKalle Valo  * and also in Tx command embedded in C_SCAN for active scans. */
13147ac9a364SKalle Valo #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
13157ac9a364SKalle Valo 
13167ac9a364SKalle Valo /* 1: This frame is non-last MPDU; more fragments are coming.
13177ac9a364SKalle Valo  * 0: Last fragment, or not using fragmentation. */
13187ac9a364SKalle Valo #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
13197ac9a364SKalle Valo 
13207ac9a364SKalle Valo /* 1: uCode calculates and inserts Timestamp Function (TSF) in outgoing frame.
13217ac9a364SKalle Valo  * 0: No TSF required in outgoing frame.
13227ac9a364SKalle Valo  * Set this for transmitting beacons and probe responses. */
13237ac9a364SKalle Valo #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
13247ac9a364SKalle Valo 
13257ac9a364SKalle Valo /* 1: Driver inserted 2 bytes pad after the MAC header, for (required) dword
13267ac9a364SKalle Valo  *    alignment of frame's payload data field.
13277ac9a364SKalle Valo  * 0: No pad
13287ac9a364SKalle Valo  * Set this for MAC headers with 26 or 30 bytes, i.e. those with QOS or ADDR4
13297ac9a364SKalle Valo  * field (but not both).  Driver must align frame data (i.e. data following
13307ac9a364SKalle Valo  * MAC header) to DWORD boundary. */
13317ac9a364SKalle Valo #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
13327ac9a364SKalle Valo 
13337ac9a364SKalle Valo /* accelerate aggregation support
13347ac9a364SKalle Valo  * 0 - no CCMP encryption; 1 - CCMP encryption */
13357ac9a364SKalle Valo #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
13367ac9a364SKalle Valo 
13377ac9a364SKalle Valo /* HCCA-AP - disable duration overwriting. */
13387ac9a364SKalle Valo #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
13397ac9a364SKalle Valo 
13407ac9a364SKalle Valo /*
13417ac9a364SKalle Valo  * TX command security control
13427ac9a364SKalle Valo  */
13437ac9a364SKalle Valo #define TX_CMD_SEC_WEP		0x01
13447ac9a364SKalle Valo #define TX_CMD_SEC_CCM		0x02
13457ac9a364SKalle Valo #define TX_CMD_SEC_TKIP		0x03
13467ac9a364SKalle Valo #define TX_CMD_SEC_MSK		0x03
13477ac9a364SKalle Valo #define TX_CMD_SEC_SHIFT	6
13487ac9a364SKalle Valo #define TX_CMD_SEC_KEY128	0x08
13497ac9a364SKalle Valo 
13507ac9a364SKalle Valo /*
13517ac9a364SKalle Valo  * C_TX = 0x1c (command)
13527ac9a364SKalle Valo  */
13537ac9a364SKalle Valo 
13547ac9a364SKalle Valo struct il3945_tx_cmd {
13557ac9a364SKalle Valo 	/*
13567ac9a364SKalle Valo 	 * MPDU byte count:
13577ac9a364SKalle Valo 	 * MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size,
13587ac9a364SKalle Valo 	 * + 8 byte IV for CCM or TKIP (not used for WEP)
13597ac9a364SKalle Valo 	 * + Data payload
13607ac9a364SKalle Valo 	 * + 8-byte MIC (not used for CCM/WEP)
13617ac9a364SKalle Valo 	 * NOTE:  Does not include Tx command bytes, post-MAC pad bytes,
13627ac9a364SKalle Valo 	 *        MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.i
13637ac9a364SKalle Valo 	 * Range: 14-2342 bytes.
13647ac9a364SKalle Valo 	 */
13657ac9a364SKalle Valo 	__le16 len;
13667ac9a364SKalle Valo 
13677ac9a364SKalle Valo 	/*
13687ac9a364SKalle Valo 	 * MPDU or MSDU byte count for next frame.
13697ac9a364SKalle Valo 	 * Used for fragmentation and bursting, but not 11n aggregation.
13707ac9a364SKalle Valo 	 * Same as "len", but for next frame.  Set to 0 if not applicable.
13717ac9a364SKalle Valo 	 */
13727ac9a364SKalle Valo 	__le16 next_frame_len;
13737ac9a364SKalle Valo 
13747ac9a364SKalle Valo 	__le32 tx_flags;	/* TX_CMD_FLG_* */
13757ac9a364SKalle Valo 
13767ac9a364SKalle Valo 	u8 rate;
13777ac9a364SKalle Valo 
13787ac9a364SKalle Valo 	/* Index of recipient station in uCode's station table */
13797ac9a364SKalle Valo 	u8 sta_id;
13807ac9a364SKalle Valo 	u8 tid_tspec;
13817ac9a364SKalle Valo 	u8 sec_ctl;
13827ac9a364SKalle Valo 	u8 key[16];
13837ac9a364SKalle Valo 	union {
13847ac9a364SKalle Valo 		u8 byte[8];
13857ac9a364SKalle Valo 		__le16 word[4];
13867ac9a364SKalle Valo 		__le32 dw[2];
13877ac9a364SKalle Valo 	} tkip_mic;
13887ac9a364SKalle Valo 	__le32 next_frame_info;
13897ac9a364SKalle Valo 	union {
13907ac9a364SKalle Valo 		__le32 life_time;
13917ac9a364SKalle Valo 		__le32 attempt;
13927ac9a364SKalle Valo 	} stop_time;
13937ac9a364SKalle Valo 	u8 supp_rates[2];
13947ac9a364SKalle Valo 	u8 rts_retry_limit;	/*byte 50 */
13957ac9a364SKalle Valo 	u8 data_retry_limit;	/*byte 51 */
13967ac9a364SKalle Valo 	union {
13977ac9a364SKalle Valo 		__le16 pm_frame_timeout;
13987ac9a364SKalle Valo 		__le16 attempt_duration;
13997ac9a364SKalle Valo 	} timeout;
14007ac9a364SKalle Valo 
14017ac9a364SKalle Valo 	/*
14027ac9a364SKalle Valo 	 * Duration of EDCA burst Tx Opportunity, in 32-usec units.
14037ac9a364SKalle Valo 	 * Set this if txop time is not specified by HCCA protocol (e.g. by AP).
14047ac9a364SKalle Valo 	 */
14057ac9a364SKalle Valo 	__le16 driver_txop;
14067ac9a364SKalle Valo 
14077ac9a364SKalle Valo 	/*
14087ac9a364SKalle Valo 	 * MAC header goes here, followed by 2 bytes padding if MAC header
14097ac9a364SKalle Valo 	 * length is 26 or 30 bytes, followed by payload data
14107ac9a364SKalle Valo 	 */
1411fa7845cfSKees Cook 	union {
1412fa7845cfSKees Cook 		DECLARE_FLEX_ARRAY(u8, payload);
1413fa7845cfSKees Cook 		DECLARE_FLEX_ARRAY(struct ieee80211_hdr, hdr);
1414fa7845cfSKees Cook 	};
14157ac9a364SKalle Valo } __packed;
14167ac9a364SKalle Valo 
14177ac9a364SKalle Valo /*
14187ac9a364SKalle Valo  * C_TX = 0x1c (response)
14197ac9a364SKalle Valo  */
14207ac9a364SKalle Valo struct il3945_tx_resp {
14217ac9a364SKalle Valo 	u8 failure_rts;
14227ac9a364SKalle Valo 	u8 failure_frame;
14237ac9a364SKalle Valo 	u8 bt_kill_count;
14247ac9a364SKalle Valo 	u8 rate;
14257ac9a364SKalle Valo 	__le32 wireless_media_time;
14267ac9a364SKalle Valo 	__le32 status;		/* TX status */
14277ac9a364SKalle Valo } __packed;
14287ac9a364SKalle Valo 
14297ac9a364SKalle Valo /*
14307ac9a364SKalle Valo  * 4965 uCode updates these Tx attempt count values in host DRAM.
14317ac9a364SKalle Valo  * Used for managing Tx retries when expecting block-acks.
14327ac9a364SKalle Valo  * Driver should set these fields to 0.
14337ac9a364SKalle Valo  */
14347ac9a364SKalle Valo struct il_dram_scratch {
14357ac9a364SKalle Valo 	u8 try_cnt;		/* Tx attempts */
14367ac9a364SKalle Valo 	u8 bt_kill_cnt;		/* Tx attempts blocked by Bluetooth device */
14377ac9a364SKalle Valo 	__le16 reserved;
14387ac9a364SKalle Valo } __packed;
14397ac9a364SKalle Valo 
14407ac9a364SKalle Valo struct il_tx_cmd {
14417ac9a364SKalle Valo 	/*
14427ac9a364SKalle Valo 	 * MPDU byte count:
14437ac9a364SKalle Valo 	 * MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size,
14447ac9a364SKalle Valo 	 * + 8 byte IV for CCM or TKIP (not used for WEP)
14457ac9a364SKalle Valo 	 * + Data payload
14467ac9a364SKalle Valo 	 * + 8-byte MIC (not used for CCM/WEP)
14477ac9a364SKalle Valo 	 * NOTE:  Does not include Tx command bytes, post-MAC pad bytes,
14487ac9a364SKalle Valo 	 *        MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.i
14497ac9a364SKalle Valo 	 * Range: 14-2342 bytes.
14507ac9a364SKalle Valo 	 */
14517ac9a364SKalle Valo 	__le16 len;
14527ac9a364SKalle Valo 
14537ac9a364SKalle Valo 	/*
14547ac9a364SKalle Valo 	 * MPDU or MSDU byte count for next frame.
14557ac9a364SKalle Valo 	 * Used for fragmentation and bursting, but not 11n aggregation.
14567ac9a364SKalle Valo 	 * Same as "len", but for next frame.  Set to 0 if not applicable.
14577ac9a364SKalle Valo 	 */
14587ac9a364SKalle Valo 	__le16 next_frame_len;
14597ac9a364SKalle Valo 
14607ac9a364SKalle Valo 	__le32 tx_flags;	/* TX_CMD_FLG_* */
14617ac9a364SKalle Valo 
14627ac9a364SKalle Valo 	/* uCode may modify this field of the Tx command (in host DRAM!).
14637ac9a364SKalle Valo 	 * Driver must also set dram_lsb_ptr and dram_msb_ptr in this cmd. */
14647ac9a364SKalle Valo 	struct il_dram_scratch scratch;
14657ac9a364SKalle Valo 
14667ac9a364SKalle Valo 	/* Rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is cleared. */
14677ac9a364SKalle Valo 	__le32 rate_n_flags;	/* RATE_MCS_* */
14687ac9a364SKalle Valo 
14697ac9a364SKalle Valo 	/* Index of destination station in uCode's station table */
14707ac9a364SKalle Valo 	u8 sta_id;
14717ac9a364SKalle Valo 
14727ac9a364SKalle Valo 	/* Type of security encryption:  CCM or TKIP */
14737ac9a364SKalle Valo 	u8 sec_ctl;		/* TX_CMD_SEC_* */
14747ac9a364SKalle Valo 
14757ac9a364SKalle Valo 	/*
14767ac9a364SKalle Valo 	 * Index into rate table (see C_TX_LINK_QUALITY_CMD) for initial
14777ac9a364SKalle Valo 	 * Tx attempt, if TX_CMD_FLG_STA_RATE_MSK is set.  Normally "0" for
14787ac9a364SKalle Valo 	 * data frames, this field may be used to selectively reduce initial
14797ac9a364SKalle Valo 	 * rate (via non-0 value) for special frames (e.g. management), while
14807ac9a364SKalle Valo 	 * still supporting rate scaling for all frames.
14817ac9a364SKalle Valo 	 */
14827ac9a364SKalle Valo 	u8 initial_rate_idx;
14837ac9a364SKalle Valo 	u8 reserved;
14847ac9a364SKalle Valo 	u8 key[16];
14857ac9a364SKalle Valo 	__le16 next_frame_flags;
14867ac9a364SKalle Valo 	__le16 reserved2;
14877ac9a364SKalle Valo 	union {
14887ac9a364SKalle Valo 		__le32 life_time;
14897ac9a364SKalle Valo 		__le32 attempt;
14907ac9a364SKalle Valo 	} stop_time;
14917ac9a364SKalle Valo 
14927ac9a364SKalle Valo 	/* Host DRAM physical address pointer to "scratch" in this command.
14937ac9a364SKalle Valo 	 * Must be dword aligned.  "0" in dram_lsb_ptr disables usage. */
14947ac9a364SKalle Valo 	__le32 dram_lsb_ptr;
14957ac9a364SKalle Valo 	u8 dram_msb_ptr;
14967ac9a364SKalle Valo 
14977ac9a364SKalle Valo 	u8 rts_retry_limit;	/*byte 50 */
14987ac9a364SKalle Valo 	u8 data_retry_limit;	/*byte 51 */
14997ac9a364SKalle Valo 	u8 tid_tspec;
15007ac9a364SKalle Valo 	union {
15017ac9a364SKalle Valo 		__le16 pm_frame_timeout;
15027ac9a364SKalle Valo 		__le16 attempt_duration;
15037ac9a364SKalle Valo 	} timeout;
15047ac9a364SKalle Valo 
15057ac9a364SKalle Valo 	/*
15067ac9a364SKalle Valo 	 * Duration of EDCA burst Tx Opportunity, in 32-usec units.
15077ac9a364SKalle Valo 	 * Set this if txop time is not specified by HCCA protocol (e.g. by AP).
15087ac9a364SKalle Valo 	 */
15097ac9a364SKalle Valo 	__le16 driver_txop;
15107ac9a364SKalle Valo 
15117ac9a364SKalle Valo 	/*
15127ac9a364SKalle Valo 	 * MAC header goes here, followed by 2 bytes padding if MAC header
15137ac9a364SKalle Valo 	 * length is 26 or 30 bytes, followed by payload data
15147ac9a364SKalle Valo 	 */
15157ac9a364SKalle Valo 	u8 payload[0];
15168863b121SGustavo A. R. Silva 	struct ieee80211_hdr hdr[];
15177ac9a364SKalle Valo } __packed;
15187ac9a364SKalle Valo 
15197ac9a364SKalle Valo /* TX command response is sent after *3945* transmission attempts.
15207ac9a364SKalle Valo  *
15217ac9a364SKalle Valo  * NOTES:
15227ac9a364SKalle Valo  *
15237ac9a364SKalle Valo  * TX_STATUS_FAIL_NEXT_FRAG
15247ac9a364SKalle Valo  *
15257ac9a364SKalle Valo  * If the fragment flag in the MAC header for the frame being transmitted
15267ac9a364SKalle Valo  * is set and there is insufficient time to transmit the next frame, the
15277ac9a364SKalle Valo  * TX status will be returned with 'TX_STATUS_FAIL_NEXT_FRAG'.
15287ac9a364SKalle Valo  *
15297ac9a364SKalle Valo  * TX_STATUS_FIFO_UNDERRUN
15307ac9a364SKalle Valo  *
15317ac9a364SKalle Valo  * Indicates the host did not provide bytes to the FIFO fast enough while
15327ac9a364SKalle Valo  * a TX was in progress.
15337ac9a364SKalle Valo  *
15347ac9a364SKalle Valo  * TX_STATUS_FAIL_MGMNT_ABORT
15357ac9a364SKalle Valo  *
15367ac9a364SKalle Valo  * This status is only possible if the ABORT ON MGMT RX parameter was
15377ac9a364SKalle Valo  * set to true with the TX command.
15387ac9a364SKalle Valo  *
15397ac9a364SKalle Valo  * If the MSB of the status parameter is set then an abort sequence is
15407ac9a364SKalle Valo  * required.  This sequence consists of the host activating the TX Abort
15417ac9a364SKalle Valo  * control line, and then waiting for the TX Abort command response.  This
15427ac9a364SKalle Valo  * indicates that a the device is no longer in a transmit state, and that the
15437ac9a364SKalle Valo  * command FIFO has been cleared.  The host must then deactivate the TX Abort
15447ac9a364SKalle Valo  * control line.  Receiving is still allowed in this case.
15457ac9a364SKalle Valo  */
15467ac9a364SKalle Valo enum {
15477ac9a364SKalle Valo 	TX_3945_STATUS_SUCCESS = 0x01,
15487ac9a364SKalle Valo 	TX_3945_STATUS_DIRECT_DONE = 0x02,
15497ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_SHORT_LIMIT = 0x82,
15507ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_LONG_LIMIT = 0x83,
15517ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
15527ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_MGMNT_ABORT = 0x85,
15537ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_NEXT_FRAG = 0x86,
15547ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_LIFE_EXPIRE = 0x87,
15557ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_DEST_PS = 0x88,
15567ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_ABORTED = 0x89,
15577ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_BT_RETRY = 0x8a,
15587ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_STA_INVALID = 0x8b,
15597ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_FRAG_DROPPED = 0x8c,
15607ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_TID_DISABLE = 0x8d,
15617ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_FRAME_FLUSHED = 0x8e,
15627ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
15637ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_TX_LOCKED = 0x90,
15647ac9a364SKalle Valo 	TX_3945_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
15657ac9a364SKalle Valo };
15667ac9a364SKalle Valo 
15677ac9a364SKalle Valo /*
15687ac9a364SKalle Valo  * TX command response is sent after *4965* transmission attempts.
15697ac9a364SKalle Valo  *
15707ac9a364SKalle Valo  * both postpone and abort status are expected behavior from uCode. there is
15717ac9a364SKalle Valo  * no special operation required from driver; except for RFKILL_FLUSH,
15727ac9a364SKalle Valo  * which required tx flush host command to flush all the tx frames in queues
15737ac9a364SKalle Valo  */
15747ac9a364SKalle Valo enum {
15757ac9a364SKalle Valo 	TX_STATUS_SUCCESS = 0x01,
15767ac9a364SKalle Valo 	TX_STATUS_DIRECT_DONE = 0x02,
15777ac9a364SKalle Valo 	/* postpone TX */
15787ac9a364SKalle Valo 	TX_STATUS_POSTPONE_DELAY = 0x40,
15797ac9a364SKalle Valo 	TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
15807ac9a364SKalle Valo 	TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
15817ac9a364SKalle Valo 	TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
15827ac9a364SKalle Valo 	/* abort TX */
15837ac9a364SKalle Valo 	TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
15847ac9a364SKalle Valo 	TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
15857ac9a364SKalle Valo 	TX_STATUS_FAIL_LONG_LIMIT = 0x83,
15867ac9a364SKalle Valo 	TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
15877ac9a364SKalle Valo 	TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
15887ac9a364SKalle Valo 	TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
15897ac9a364SKalle Valo 	TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
15907ac9a364SKalle Valo 	TX_STATUS_FAIL_DEST_PS = 0x88,
15917ac9a364SKalle Valo 	TX_STATUS_FAIL_HOST_ABORTED = 0x89,
15927ac9a364SKalle Valo 	TX_STATUS_FAIL_BT_RETRY = 0x8a,
15937ac9a364SKalle Valo 	TX_STATUS_FAIL_STA_INVALID = 0x8b,
15947ac9a364SKalle Valo 	TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
15957ac9a364SKalle Valo 	TX_STATUS_FAIL_TID_DISABLE = 0x8d,
15967ac9a364SKalle Valo 	TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
15977ac9a364SKalle Valo 	TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
15987ac9a364SKalle Valo 	TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
15997ac9a364SKalle Valo 	TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
16007ac9a364SKalle Valo };
16017ac9a364SKalle Valo 
16027ac9a364SKalle Valo #define	TX_PACKET_MODE_REGULAR		0x0000
16037ac9a364SKalle Valo #define	TX_PACKET_MODE_BURST_SEQ	0x0100
16047ac9a364SKalle Valo #define	TX_PACKET_MODE_BURST_FIRST	0x0200
16057ac9a364SKalle Valo 
16067ac9a364SKalle Valo enum {
16077ac9a364SKalle Valo 	TX_POWER_PA_NOT_ACTIVE = 0x0,
16087ac9a364SKalle Valo };
16097ac9a364SKalle Valo 
16107ac9a364SKalle Valo enum {
16117ac9a364SKalle Valo 	TX_STATUS_MSK = 0x000000ff,	/* bits 0:7 */
16127ac9a364SKalle Valo 	TX_STATUS_DELAY_MSK = 0x00000040,
16137ac9a364SKalle Valo 	TX_STATUS_ABORT_MSK = 0x00000080,
16147ac9a364SKalle Valo 	TX_PACKET_MODE_MSK = 0x0000ff00,	/* bits 8:15 */
16157ac9a364SKalle Valo 	TX_FIFO_NUMBER_MSK = 0x00070000,	/* bits 16:18 */
16167ac9a364SKalle Valo 	TX_RESERVED = 0x00780000,	/* bits 19:22 */
16177ac9a364SKalle Valo 	TX_POWER_PA_DETECT_MSK = 0x7f800000,	/* bits 23:30 */
16187ac9a364SKalle Valo 	TX_ABORT_REQUIRED_MSK = 0x80000000,	/* bits 31:31 */
16197ac9a364SKalle Valo };
16207ac9a364SKalle Valo 
16217ac9a364SKalle Valo /* *******************************
16227ac9a364SKalle Valo  * TX aggregation status
16237ac9a364SKalle Valo  ******************************* */
16247ac9a364SKalle Valo 
16257ac9a364SKalle Valo enum {
16267ac9a364SKalle Valo 	AGG_TX_STATE_TRANSMITTED = 0x00,
16277ac9a364SKalle Valo 	AGG_TX_STATE_UNDERRUN_MSK = 0x01,
16287ac9a364SKalle Valo 	AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
16297ac9a364SKalle Valo 	AGG_TX_STATE_ABORT_MSK = 0x08,
16307ac9a364SKalle Valo 	AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
16317ac9a364SKalle Valo 	AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
16327ac9a364SKalle Valo 	AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
16337ac9a364SKalle Valo 	AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
16347ac9a364SKalle Valo 	AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
16357ac9a364SKalle Valo 	AGG_TX_STATE_DUMP_TX_MSK = 0x200,
16367ac9a364SKalle Valo 	AGG_TX_STATE_DELAY_TX_MSK = 0x400
16377ac9a364SKalle Valo };
16387ac9a364SKalle Valo 
16397ac9a364SKalle Valo #define AGG_TX_STATUS_MSK	0x00000fff	/* bits 0:11 */
16407ac9a364SKalle Valo #define AGG_TX_TRY_MSK		0x0000f000	/* bits 12:15 */
16417ac9a364SKalle Valo 
16427ac9a364SKalle Valo #define AGG_TX_STATE_LAST_SENT_MSK  (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
16437ac9a364SKalle Valo 				     AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK)
16447ac9a364SKalle Valo 
16457ac9a364SKalle Valo /* # tx attempts for first frame in aggregation */
16467ac9a364SKalle Valo #define AGG_TX_STATE_TRY_CNT_POS 12
16477ac9a364SKalle Valo #define AGG_TX_STATE_TRY_CNT_MSK 0xf000
16487ac9a364SKalle Valo 
16497ac9a364SKalle Valo /* Command ID and sequence number of Tx command for this frame */
16507ac9a364SKalle Valo #define AGG_TX_STATE_SEQ_NUM_POS 16
16517ac9a364SKalle Valo #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
16527ac9a364SKalle Valo 
16537ac9a364SKalle Valo /*
16547ac9a364SKalle Valo  * C_TX = 0x1c (response)
16557ac9a364SKalle Valo  *
16567ac9a364SKalle Valo  * This response may be in one of two slightly different formats, indicated
16577ac9a364SKalle Valo  * by the frame_count field:
16587ac9a364SKalle Valo  *
16597ac9a364SKalle Valo  * 1)  No aggregation (frame_count == 1).  This reports Tx results for
16607ac9a364SKalle Valo  *     a single frame.  Multiple attempts, at various bit rates, may have
16617ac9a364SKalle Valo  *     been made for this frame.
16627ac9a364SKalle Valo  *
16637ac9a364SKalle Valo  * 2)  Aggregation (frame_count > 1).  This reports Tx results for
16647ac9a364SKalle Valo  *     2 or more frames that used block-acknowledge.  All frames were
16657ac9a364SKalle Valo  *     transmitted at same rate.  Rate scaling may have been used if first
16667ac9a364SKalle Valo  *     frame in this new agg block failed in previous agg block(s).
16677ac9a364SKalle Valo  *
16687ac9a364SKalle Valo  *     Note that, for aggregation, ACK (block-ack) status is not delivered here;
16697ac9a364SKalle Valo  *     block-ack has not been received by the time the 4965 device records
16707ac9a364SKalle Valo  *     this status.
16717ac9a364SKalle Valo  *     This status relates to reasons the tx might have been blocked or aborted
16727ac9a364SKalle Valo  *     within the sending station (this 4965 device), rather than whether it was
16737ac9a364SKalle Valo  *     received successfully by the destination station.
16747ac9a364SKalle Valo  */
16757ac9a364SKalle Valo struct agg_tx_status {
16767ac9a364SKalle Valo 	__le16 status;
16777ac9a364SKalle Valo 	__le16 sequence;
16787ac9a364SKalle Valo } __packed;
16797ac9a364SKalle Valo 
16807ac9a364SKalle Valo struct il4965_tx_resp {
16817ac9a364SKalle Valo 	u8 frame_count;		/* 1 no aggregation, >1 aggregation */
16827ac9a364SKalle Valo 	u8 bt_kill_count;	/* # blocked by bluetooth (unused for agg) */
16837ac9a364SKalle Valo 	u8 failure_rts;		/* # failures due to unsuccessful RTS */
16847ac9a364SKalle Valo 	u8 failure_frame;	/* # failures due to no ACK (unused for agg) */
16857ac9a364SKalle Valo 
16867ac9a364SKalle Valo 	/* For non-agg:  Rate at which frame was successful.
16877ac9a364SKalle Valo 	 * For agg:  Rate at which all frames were transmitted. */
16887ac9a364SKalle Valo 	__le32 rate_n_flags;	/* RATE_MCS_*  */
16897ac9a364SKalle Valo 
16907ac9a364SKalle Valo 	/* For non-agg:  RTS + CTS + frame tx attempts time + ACK.
16917ac9a364SKalle Valo 	 * For agg:  RTS + CTS + aggregation tx time + block-ack time. */
16927ac9a364SKalle Valo 	__le16 wireless_media_time;	/* uSecs */
16937ac9a364SKalle Valo 
16947ac9a364SKalle Valo 	__le16 reserved;
16957ac9a364SKalle Valo 	__le32 pa_power1;	/* RF power amplifier measurement (not used) */
16967ac9a364SKalle Valo 	__le32 pa_power2;
16977ac9a364SKalle Valo 
16987ac9a364SKalle Valo 	/*
16997ac9a364SKalle Valo 	 * For non-agg:  frame status TX_STATUS_*
17007ac9a364SKalle Valo 	 * For agg:  status of 1st frame, AGG_TX_STATE_*; other frame status
17017ac9a364SKalle Valo 	 *           fields follow this one, up to frame_count.
17027ac9a364SKalle Valo 	 *           Bit fields:
17037ac9a364SKalle Valo 	 *           11- 0:  AGG_TX_STATE_* status code
17047ac9a364SKalle Valo 	 *           15-12:  Retry count for 1st frame in aggregation (retries
17057ac9a364SKalle Valo 	 *                   occur if tx failed for this frame when it was a
17067ac9a364SKalle Valo 	 *                   member of a previous aggregation block).  If rate
17077ac9a364SKalle Valo 	 *                   scaling is used, retry count indicates the rate
17087ac9a364SKalle Valo 	 *                   table entry used for all frames in the new agg.
17097ac9a364SKalle Valo 	 *           31-16:  Sequence # for this frame's Tx cmd (not SSN!)
17107ac9a364SKalle Valo 	 */
17117ac9a364SKalle Valo 	union {
17127ac9a364SKalle Valo 		__le32 status;
1713*56df3d40SGustavo A. R. Silva 		DECLARE_FLEX_ARRAY(struct agg_tx_status, agg_status);	/* for each agg frame */
17147ac9a364SKalle Valo 	} u;
17157ac9a364SKalle Valo } __packed;
17167ac9a364SKalle Valo 
17177ac9a364SKalle Valo /*
17187ac9a364SKalle Valo  * N_COMPRESSED_BA = 0xc5 (response only, not a command)
17197ac9a364SKalle Valo  *
17207ac9a364SKalle Valo  * Reports Block-Acknowledge from recipient station
17217ac9a364SKalle Valo  */
17227ac9a364SKalle Valo struct il_compressed_ba_resp {
17237ac9a364SKalle Valo 	__le32 sta_addr_lo32;
17247ac9a364SKalle Valo 	__le16 sta_addr_hi16;
17257ac9a364SKalle Valo 	__le16 reserved;
17267ac9a364SKalle Valo 
17277ac9a364SKalle Valo 	/* Index of recipient (BA-sending) station in uCode's station table */
17287ac9a364SKalle Valo 	u8 sta_id;
17297ac9a364SKalle Valo 	u8 tid;
17307ac9a364SKalle Valo 	__le16 seq_ctl;
17317ac9a364SKalle Valo 	__le64 bitmap;
17327ac9a364SKalle Valo 	__le16 scd_flow;
17337ac9a364SKalle Valo 	__le16 scd_ssn;
17347ac9a364SKalle Valo } __packed;
17357ac9a364SKalle Valo 
17367ac9a364SKalle Valo /*
17377ac9a364SKalle Valo  * C_TX_PWR_TBL = 0x97 (command, has simple generic response)
17387ac9a364SKalle Valo  *
17397ac9a364SKalle Valo  * See details under "TXPOWER" in 4965.h.
17407ac9a364SKalle Valo  */
17417ac9a364SKalle Valo 
17427ac9a364SKalle Valo struct il3945_txpowertable_cmd {
17437ac9a364SKalle Valo 	u8 band;		/* 0: 5 GHz, 1: 2.4 GHz */
17447ac9a364SKalle Valo 	u8 reserved;
17457ac9a364SKalle Valo 	__le16 channel;
17467ac9a364SKalle Valo 	struct il3945_power_per_rate power[IL_MAX_RATES];
17477ac9a364SKalle Valo } __packed;
17487ac9a364SKalle Valo 
17497ac9a364SKalle Valo struct il4965_txpowertable_cmd {
17507ac9a364SKalle Valo 	u8 band;		/* 0: 5 GHz, 1: 2.4 GHz */
17517ac9a364SKalle Valo 	u8 reserved;
17527ac9a364SKalle Valo 	__le16 channel;
17537ac9a364SKalle Valo 	struct il4965_tx_power_db tx_power;
17547ac9a364SKalle Valo } __packed;
17557ac9a364SKalle Valo 
17567ac9a364SKalle Valo /**
17577ac9a364SKalle Valo  * struct il3945_rate_scaling_cmd - Rate Scaling Command & Response
17587ac9a364SKalle Valo  *
17597ac9a364SKalle Valo  * C_RATE_SCALE = 0x47 (command, has simple generic response)
17607ac9a364SKalle Valo  *
17617ac9a364SKalle Valo  * NOTE: The table of rates passed to the uCode via the
17627ac9a364SKalle Valo  * RATE_SCALE command sets up the corresponding order of
17637ac9a364SKalle Valo  * rates used for all related commands, including rate
17647ac9a364SKalle Valo  * masks, etc.
17657ac9a364SKalle Valo  *
17667ac9a364SKalle Valo  * For example, if you set 9MB (PLCP 0x0f) as the first
17677ac9a364SKalle Valo  * rate in the rate table, the bit mask for that rate
17687ac9a364SKalle Valo  * when passed through ofdm_basic_rates on the C_RXON
17697ac9a364SKalle Valo  * command would be bit 0 (1 << 0)
17707ac9a364SKalle Valo  */
17717ac9a364SKalle Valo struct il3945_rate_scaling_info {
17727ac9a364SKalle Valo 	__le16 rate_n_flags;
17737ac9a364SKalle Valo 	u8 try_cnt;
17747ac9a364SKalle Valo 	u8 next_rate_idx;
17757ac9a364SKalle Valo } __packed;
17767ac9a364SKalle Valo 
17777ac9a364SKalle Valo struct il3945_rate_scaling_cmd {
17787ac9a364SKalle Valo 	u8 table_id;
17797ac9a364SKalle Valo 	u8 reserved[3];
17807ac9a364SKalle Valo 	struct il3945_rate_scaling_info table[IL_MAX_RATES];
17817ac9a364SKalle Valo } __packed;
17827ac9a364SKalle Valo 
17837ac9a364SKalle Valo /*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */
17847ac9a364SKalle Valo #define  LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK	(1 << 0)
17857ac9a364SKalle Valo 
17867ac9a364SKalle Valo /* # of EDCA prioritized tx fifos */
17877ac9a364SKalle Valo #define  LINK_QUAL_AC_NUM AC_NUM
17887ac9a364SKalle Valo 
17897ac9a364SKalle Valo /* # entries in rate scale table to support Tx retries */
17907ac9a364SKalle Valo #define  LINK_QUAL_MAX_RETRY_NUM 16
17917ac9a364SKalle Valo 
17927ac9a364SKalle Valo /* Tx antenna selection values */
17937ac9a364SKalle Valo #define  LINK_QUAL_ANT_A_MSK (1 << 0)
17947ac9a364SKalle Valo #define  LINK_QUAL_ANT_B_MSK (1 << 1)
17957ac9a364SKalle Valo #define  LINK_QUAL_ANT_MSK   (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
17967ac9a364SKalle Valo 
17977ac9a364SKalle Valo /**
17987ac9a364SKalle Valo  * struct il_link_qual_general_params
17997ac9a364SKalle Valo  *
18007ac9a364SKalle Valo  * Used in C_TX_LINK_QUALITY_CMD
18017ac9a364SKalle Valo  */
18027ac9a364SKalle Valo struct il_link_qual_general_params {
18037ac9a364SKalle Valo 	u8 flags;
18047ac9a364SKalle Valo 
18057ac9a364SKalle Valo 	/* No entries at or above this (driver chosen) idx contain MIMO */
18067ac9a364SKalle Valo 	u8 mimo_delimiter;
18077ac9a364SKalle Valo 
18087ac9a364SKalle Valo 	/* Best single antenna to use for single stream (legacy, SISO). */
18097ac9a364SKalle Valo 	u8 single_stream_ant_msk;	/* LINK_QUAL_ANT_* */
18107ac9a364SKalle Valo 
18117ac9a364SKalle Valo 	/* Best antennas to use for MIMO (unused for 4965, assumes both). */
18127ac9a364SKalle Valo 	u8 dual_stream_ant_msk;	/* LINK_QUAL_ANT_* */
18137ac9a364SKalle Valo 
18147ac9a364SKalle Valo 	/*
18157ac9a364SKalle Valo 	 * If driver needs to use different initial rates for different
18167ac9a364SKalle Valo 	 * EDCA QOS access categories (as implemented by tx fifos 0-3),
18177ac9a364SKalle Valo 	 * this table will set that up, by indicating the idxes in the
18187ac9a364SKalle Valo 	 * rs_table[LINK_QUAL_MAX_RETRY_NUM] rate table at which to start.
18197ac9a364SKalle Valo 	 * Otherwise, driver should set all entries to 0.
18207ac9a364SKalle Valo 	 *
18217ac9a364SKalle Valo 	 * Entry usage:
18227ac9a364SKalle Valo 	 * 0 = Background, 1 = Best Effort (normal), 2 = Video, 3 = Voice
18237ac9a364SKalle Valo 	 * TX FIFOs above 3 use same value (typically 0) as TX FIFO 3.
18247ac9a364SKalle Valo 	 */
18257ac9a364SKalle Valo 	u8 start_rate_idx[LINK_QUAL_AC_NUM];
18267ac9a364SKalle Valo } __packed;
18277ac9a364SKalle Valo 
18287ac9a364SKalle Valo #define LINK_QUAL_AGG_TIME_LIMIT_DEF	(4000)	/* 4 milliseconds */
18297ac9a364SKalle Valo #define LINK_QUAL_AGG_TIME_LIMIT_MAX	(8000)
18307ac9a364SKalle Valo #define LINK_QUAL_AGG_TIME_LIMIT_MIN	(100)
18317ac9a364SKalle Valo 
18327ac9a364SKalle Valo #define LINK_QUAL_AGG_DISABLE_START_DEF	(3)
18337ac9a364SKalle Valo #define LINK_QUAL_AGG_DISABLE_START_MAX	(255)
18347ac9a364SKalle Valo #define LINK_QUAL_AGG_DISABLE_START_MIN	(0)
18357ac9a364SKalle Valo 
18367ac9a364SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_DEF	(31)
18377ac9a364SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_MAX	(63)
18387ac9a364SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_MIN	(0)
18397ac9a364SKalle Valo 
18407ac9a364SKalle Valo /**
18417ac9a364SKalle Valo  * struct il_link_qual_agg_params
18427ac9a364SKalle Valo  *
18437ac9a364SKalle Valo  * Used in C_TX_LINK_QUALITY_CMD
18447ac9a364SKalle Valo  */
18457ac9a364SKalle Valo struct il_link_qual_agg_params {
18467ac9a364SKalle Valo 
18477ac9a364SKalle Valo 	/*
18487ac9a364SKalle Valo 	 *Maximum number of uSec in aggregation.
18497ac9a364SKalle Valo 	 * default set to 4000 (4 milliseconds) if not configured in .cfg
18507ac9a364SKalle Valo 	 */
18517ac9a364SKalle Valo 	__le16 agg_time_limit;
18527ac9a364SKalle Valo 
18537ac9a364SKalle Valo 	/*
18547ac9a364SKalle Valo 	 * Number of Tx retries allowed for a frame, before that frame will
18557ac9a364SKalle Valo 	 * no longer be considered for the start of an aggregation sequence
18567ac9a364SKalle Valo 	 * (scheduler will then try to tx it as single frame).
18577ac9a364SKalle Valo 	 * Driver should set this to 3.
18587ac9a364SKalle Valo 	 */
18597ac9a364SKalle Valo 	u8 agg_dis_start_th;
18607ac9a364SKalle Valo 
18617ac9a364SKalle Valo 	/*
18627ac9a364SKalle Valo 	 * Maximum number of frames in aggregation.
18637ac9a364SKalle Valo 	 * 0 = no limit (default).  1 = no aggregation.
18647ac9a364SKalle Valo 	 * Other values = max # frames in aggregation.
18657ac9a364SKalle Valo 	 */
18667ac9a364SKalle Valo 	u8 agg_frame_cnt_limit;
18677ac9a364SKalle Valo 
18687ac9a364SKalle Valo 	__le32 reserved;
18697ac9a364SKalle Valo } __packed;
18707ac9a364SKalle Valo 
18717ac9a364SKalle Valo /*
18727ac9a364SKalle Valo  * C_TX_LINK_QUALITY_CMD = 0x4e (command, has simple generic response)
18737ac9a364SKalle Valo  *
18747ac9a364SKalle Valo  * For 4965 devices only; 3945 uses C_RATE_SCALE.
18757ac9a364SKalle Valo  *
18767ac9a364SKalle Valo  * Each station in the 4965 device's internal station table has its own table
18777ac9a364SKalle Valo  * of 16
18787ac9a364SKalle Valo  * Tx rates and modulation modes (e.g. legacy/SISO/MIMO) for retrying Tx when
18797ac9a364SKalle Valo  * an ACK is not received.  This command replaces the entire table for
18807ac9a364SKalle Valo  * one station.
18817ac9a364SKalle Valo  *
18827ac9a364SKalle Valo  * NOTE:  Station must already be in 4965 device's station table.
18837ac9a364SKalle Valo  *	  Use C_ADD_STA.
18847ac9a364SKalle Valo  *
18857ac9a364SKalle Valo  * The rate scaling procedures described below work well.  Of course, other
18867ac9a364SKalle Valo  * procedures are possible, and may work better for particular environments.
18877ac9a364SKalle Valo  *
18887ac9a364SKalle Valo  *
18897ac9a364SKalle Valo  * FILLING THE RATE TBL
18907ac9a364SKalle Valo  *
18917ac9a364SKalle Valo  * Given a particular initial rate and mode, as determined by the rate
18927ac9a364SKalle Valo  * scaling algorithm described below, the Linux driver uses the following
18937ac9a364SKalle Valo  * formula to fill the rs_table[LINK_QUAL_MAX_RETRY_NUM] rate table in the
18947ac9a364SKalle Valo  * Link Quality command:
18957ac9a364SKalle Valo  *
18967ac9a364SKalle Valo  *
18977ac9a364SKalle Valo  * 1)  If using High-throughput (HT) (SISO or MIMO) initial rate:
18987ac9a364SKalle Valo  *     a) Use this same initial rate for first 3 entries.
18997ac9a364SKalle Valo  *     b) Find next lower available rate using same mode (SISO or MIMO),
19007ac9a364SKalle Valo  *        use for next 3 entries.  If no lower rate available, switch to
19017ac9a364SKalle Valo  *        legacy mode (no HT40 channel, no MIMO, no short guard interval).
19027ac9a364SKalle Valo  *     c) If using MIMO, set command's mimo_delimiter to number of entries
19037ac9a364SKalle Valo  *        using MIMO (3 or 6).
19047ac9a364SKalle Valo  *     d) After trying 2 HT rates, switch to legacy mode (no HT40 channel,
19057ac9a364SKalle Valo  *        no MIMO, no short guard interval), at the next lower bit rate
19067ac9a364SKalle Valo  *        (e.g. if second HT bit rate was 54, try 48 legacy), and follow
19077ac9a364SKalle Valo  *        legacy procedure for remaining table entries.
19087ac9a364SKalle Valo  *
19097ac9a364SKalle Valo  * 2)  If using legacy initial rate:
19107ac9a364SKalle Valo  *     a) Use the initial rate for only one entry.
19117ac9a364SKalle Valo  *     b) For each following entry, reduce the rate to next lower available
19127ac9a364SKalle Valo  *        rate, until reaching the lowest available rate.
19137ac9a364SKalle Valo  *     c) When reducing rate, also switch antenna selection.
19147ac9a364SKalle Valo  *     d) Once lowest available rate is reached, repeat this rate until
19157ac9a364SKalle Valo  *        rate table is filled (16 entries), switching antenna each entry.
19167ac9a364SKalle Valo  *
19177ac9a364SKalle Valo  *
19187ac9a364SKalle Valo  * ACCUMULATING HISTORY
19197ac9a364SKalle Valo  *
19207ac9a364SKalle Valo  * The rate scaling algorithm for 4965 devices, as implemented in Linux driver,
19217ac9a364SKalle Valo  * uses two sets of frame Tx success history:  One for the current/active
19227ac9a364SKalle Valo  * modulation mode, and one for a speculative/search mode that is being
19237ac9a364SKalle Valo  * attempted. If the speculative mode turns out to be more effective (i.e.
19247ac9a364SKalle Valo  * actual transfer rate is better), then the driver continues to use the
19257ac9a364SKalle Valo  * speculative mode as the new current active mode.
19267ac9a364SKalle Valo  *
19277ac9a364SKalle Valo  * Each history set contains, separately for each possible rate, data for a
19287ac9a364SKalle Valo  * sliding win of the 62 most recent tx attempts at that rate.  The data
19297ac9a364SKalle Valo  * includes a shifting bitmap of success(1)/failure(0), and sums of successful
19307ac9a364SKalle Valo  * and attempted frames, from which the driver can additionally calculate a
19317ac9a364SKalle Valo  * success ratio (success / attempted) and number of failures
19327ac9a364SKalle Valo  * (attempted - success), and control the size of the win (attempted).
19337ac9a364SKalle Valo  * The driver uses the bit map to remove successes from the success sum, as
19347ac9a364SKalle Valo  * the oldest tx attempts fall out of the win.
19357ac9a364SKalle Valo  *
19367ac9a364SKalle Valo  * When the 4965 device makes multiple tx attempts for a given frame, each
19377ac9a364SKalle Valo  * attempt might be at a different rate, and have different modulation
19387ac9a364SKalle Valo  * characteristics (e.g. antenna, fat channel, short guard interval), as set
19397ac9a364SKalle Valo  * up in the rate scaling table in the Link Quality command.  The driver must
19407ac9a364SKalle Valo  * determine which rate table entry was used for each tx attempt, to determine
19417ac9a364SKalle Valo  * which rate-specific history to update, and record only those attempts that
19427ac9a364SKalle Valo  * match the modulation characteristics of the history set.
19437ac9a364SKalle Valo  *
19447ac9a364SKalle Valo  * When using block-ack (aggregation), all frames are transmitted at the same
19457ac9a364SKalle Valo  * rate, since there is no per-attempt acknowledgment from the destination
19467ac9a364SKalle Valo  * station.  The Tx response struct il_tx_resp indicates the Tx rate in
19477ac9a364SKalle Valo  * rate_n_flags field.  After receiving a block-ack, the driver can update
19487ac9a364SKalle Valo  * history for the entire block all at once.
19497ac9a364SKalle Valo  *
19507ac9a364SKalle Valo  *
19517ac9a364SKalle Valo  * FINDING BEST STARTING RATE:
19527ac9a364SKalle Valo  *
19537ac9a364SKalle Valo  * When working with a selected initial modulation mode (see below), the
19547ac9a364SKalle Valo  * driver attempts to find a best initial rate.  The initial rate is the
19557ac9a364SKalle Valo  * first entry in the Link Quality command's rate table.
19567ac9a364SKalle Valo  *
19577ac9a364SKalle Valo  * 1)  Calculate actual throughput (success ratio * expected throughput, see
19587ac9a364SKalle Valo  *     table below) for current initial rate.  Do this only if enough frames
19597ac9a364SKalle Valo  *     have been attempted to make the value meaningful:  at least 6 failed
19607ac9a364SKalle Valo  *     tx attempts, or at least 8 successes.  If not enough, don't try rate
19617ac9a364SKalle Valo  *     scaling yet.
19627ac9a364SKalle Valo  *
19637ac9a364SKalle Valo  * 2)  Find available rates adjacent to current initial rate.  Available means:
19647ac9a364SKalle Valo  *     a)  supported by hardware &&
19657ac9a364SKalle Valo  *     b)  supported by association &&
19667ac9a364SKalle Valo  *     c)  within any constraints selected by user
19677ac9a364SKalle Valo  *
19687ac9a364SKalle Valo  * 3)  Gather measured throughputs for adjacent rates.  These might not have
19697ac9a364SKalle Valo  *     enough history to calculate a throughput.  That's okay, we might try
19707ac9a364SKalle Valo  *     using one of them anyway!
19717ac9a364SKalle Valo  *
19727ac9a364SKalle Valo  * 4)  Try decreasing rate if, for current rate:
19737ac9a364SKalle Valo  *     a)  success ratio is < 15% ||
19747ac9a364SKalle Valo  *     b)  lower adjacent rate has better measured throughput ||
19757ac9a364SKalle Valo  *     c)  higher adjacent rate has worse throughput, and lower is unmeasured
19767ac9a364SKalle Valo  *
19777ac9a364SKalle Valo  *     As a sanity check, if decrease was determined above, leave rate
19787ac9a364SKalle Valo  *     unchanged if:
19797ac9a364SKalle Valo  *     a)  lower rate unavailable
19807ac9a364SKalle Valo  *     b)  success ratio at current rate > 85% (very good)
19817ac9a364SKalle Valo  *     c)  current measured throughput is better than expected throughput
19827ac9a364SKalle Valo  *         of lower rate (under perfect 100% tx conditions, see table below)
19837ac9a364SKalle Valo  *
19847ac9a364SKalle Valo  * 5)  Try increasing rate if, for current rate:
19857ac9a364SKalle Valo  *     a)  success ratio is < 15% ||
19867ac9a364SKalle Valo  *     b)  both adjacent rates' throughputs are unmeasured (try it!) ||
19877ac9a364SKalle Valo  *     b)  higher adjacent rate has better measured throughput ||
19887ac9a364SKalle Valo  *     c)  lower adjacent rate has worse throughput, and higher is unmeasured
19897ac9a364SKalle Valo  *
19907ac9a364SKalle Valo  *     As a sanity check, if increase was determined above, leave rate
19917ac9a364SKalle Valo  *     unchanged if:
19927ac9a364SKalle Valo  *     a)  success ratio at current rate < 70%.  This is not particularly
19937ac9a364SKalle Valo  *         good performance; higher rate is sure to have poorer success.
19947ac9a364SKalle Valo  *
19957ac9a364SKalle Valo  * 6)  Re-evaluate the rate after each tx frame.  If working with block-
19967ac9a364SKalle Valo  *     acknowledge, history and stats may be calculated for the entire
19977ac9a364SKalle Valo  *     block (including prior history that fits within the history wins),
19987ac9a364SKalle Valo  *     before re-evaluation.
19997ac9a364SKalle Valo  *
20007ac9a364SKalle Valo  * FINDING BEST STARTING MODULATION MODE:
20017ac9a364SKalle Valo  *
20027ac9a364SKalle Valo  * After working with a modulation mode for a "while" (and doing rate scaling),
20037ac9a364SKalle Valo  * the driver searches for a new initial mode in an attempt to improve
20047ac9a364SKalle Valo  * throughput.  The "while" is measured by numbers of attempted frames:
20057ac9a364SKalle Valo  *
20067ac9a364SKalle Valo  * For legacy mode, search for new mode after:
20077ac9a364SKalle Valo  *   480 successful frames, or 160 failed frames
20087ac9a364SKalle Valo  * For high-throughput modes (SISO or MIMO), search for new mode after:
20097ac9a364SKalle Valo  *   4500 successful frames, or 400 failed frames
20107ac9a364SKalle Valo  *
20117ac9a364SKalle Valo  * Mode switch possibilities are (3 for each mode):
20127ac9a364SKalle Valo  *
20137ac9a364SKalle Valo  * For legacy:
20147ac9a364SKalle Valo  *   Change antenna, try SISO (if HT association), try MIMO (if HT association)
20157ac9a364SKalle Valo  * For SISO:
20167ac9a364SKalle Valo  *   Change antenna, try MIMO, try shortened guard interval (SGI)
20177ac9a364SKalle Valo  * For MIMO:
20187ac9a364SKalle Valo  *   Try SISO antenna A, SISO antenna B, try shortened guard interval (SGI)
20197ac9a364SKalle Valo  *
20207ac9a364SKalle Valo  * When trying a new mode, use the same bit rate as the old/current mode when
20217ac9a364SKalle Valo  * trying antenna switches and shortened guard interval.  When switching to
20227ac9a364SKalle Valo  * SISO from MIMO or legacy, or to MIMO from SISO or legacy, use a rate
20237ac9a364SKalle Valo  * for which the expected throughput (under perfect conditions) is about the
20247ac9a364SKalle Valo  * same or slightly better than the actual measured throughput delivered by
20257ac9a364SKalle Valo  * the old/current mode.
20267ac9a364SKalle Valo  *
20277ac9a364SKalle Valo  * Actual throughput can be estimated by multiplying the expected throughput
20287ac9a364SKalle Valo  * by the success ratio (successful / attempted tx frames).  Frame size is
20297ac9a364SKalle Valo  * not considered in this calculation; it assumes that frame size will average
20307ac9a364SKalle Valo  * out to be fairly consistent over several samples.  The following are
20317ac9a364SKalle Valo  * metric values for expected throughput assuming 100% success ratio.
20327ac9a364SKalle Valo  * Only G band has support for CCK rates:
20337ac9a364SKalle Valo  *
20347ac9a364SKalle Valo  *           RATE:  1    2    5   11    6   9   12   18   24   36   48   54   60
20357ac9a364SKalle Valo  *
20367ac9a364SKalle Valo  *              G:  7   13   35   58   40  57   72   98  121  154  177  186  186
20377ac9a364SKalle Valo  *              A:  0    0    0    0   40  57   72   98  121  154  177  186  186
20387ac9a364SKalle Valo  *     SISO 20MHz:  0    0    0    0   42  42   76  102  124  159  183  193  202
20397ac9a364SKalle Valo  * SGI SISO 20MHz:  0    0    0    0   46  46   82  110  132  168  192  202  211
20407ac9a364SKalle Valo  *     MIMO 20MHz:  0    0    0    0   74  74  123  155  179  214  236  244  251
20417ac9a364SKalle Valo  * SGI MIMO 20MHz:  0    0    0    0   81  81  131  164  188  222  243  251  257
20427ac9a364SKalle Valo  *     SISO 40MHz:  0    0    0    0   77  77  127  160  184  220  242  250  257
20437ac9a364SKalle Valo  * SGI SISO 40MHz:  0    0    0    0   83  83  135  169  193  229  250  257  264
20447ac9a364SKalle Valo  *     MIMO 40MHz:  0    0    0    0  123 123  182  214  235  264  279  285  289
20457ac9a364SKalle Valo  * SGI MIMO 40MHz:  0    0    0    0  131 131  191  222  242  270  284  289  293
20467ac9a364SKalle Valo  *
20477ac9a364SKalle Valo  * After the new mode has been tried for a short while (minimum of 6 failed
20487ac9a364SKalle Valo  * frames or 8 successful frames), compare success ratio and actual throughput
20497ac9a364SKalle Valo  * estimate of the new mode with the old.  If either is better with the new
20507ac9a364SKalle Valo  * mode, continue to use the new mode.
20517ac9a364SKalle Valo  *
20527ac9a364SKalle Valo  * Continue comparing modes until all 3 possibilities have been tried.
20537ac9a364SKalle Valo  * If moving from legacy to HT, try all 3 possibilities from the new HT
20547ac9a364SKalle Valo  * mode.  After trying all 3, a best mode is found.  Continue to use this mode
20557ac9a364SKalle Valo  * for the longer "while" described above (e.g. 480 successful frames for
20567ac9a364SKalle Valo  * legacy), and then repeat the search process.
20577ac9a364SKalle Valo  *
20587ac9a364SKalle Valo  */
20597ac9a364SKalle Valo struct il_link_quality_cmd {
20607ac9a364SKalle Valo 
20617ac9a364SKalle Valo 	/* Index of destination/recipient station in uCode's station table */
20627ac9a364SKalle Valo 	u8 sta_id;
20637ac9a364SKalle Valo 	u8 reserved1;
20647ac9a364SKalle Valo 	__le16 control;		/* not used */
20657ac9a364SKalle Valo 	struct il_link_qual_general_params general_params;
20667ac9a364SKalle Valo 	struct il_link_qual_agg_params agg_params;
20677ac9a364SKalle Valo 
20687ac9a364SKalle Valo 	/*
20697ac9a364SKalle Valo 	 * Rate info; when using rate-scaling, Tx command's initial_rate_idx
20707ac9a364SKalle Valo 	 * specifies 1st Tx rate attempted, via idx into this table.
20717ac9a364SKalle Valo 	 * 4965 devices works its way through table when retrying Tx.
20727ac9a364SKalle Valo 	 */
20737ac9a364SKalle Valo 	struct {
20747ac9a364SKalle Valo 		__le32 rate_n_flags;	/* RATE_MCS_*, RATE_* */
20757ac9a364SKalle Valo 	} rs_table[LINK_QUAL_MAX_RETRY_NUM];
20767ac9a364SKalle Valo 	__le32 reserved2;
20777ac9a364SKalle Valo } __packed;
20787ac9a364SKalle Valo 
20797ac9a364SKalle Valo /*
20807ac9a364SKalle Valo  * BT configuration enable flags:
20817ac9a364SKalle Valo  *   bit 0 - 1: BT channel announcement enabled
20827ac9a364SKalle Valo  *           0: disable
20837ac9a364SKalle Valo  *   bit 1 - 1: priority of BT device enabled
20847ac9a364SKalle Valo  *           0: disable
20857ac9a364SKalle Valo  */
20867ac9a364SKalle Valo #define BT_COEX_DISABLE (0x0)
20877ac9a364SKalle Valo #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
20887ac9a364SKalle Valo #define BT_ENABLE_PRIORITY	   BIT(1)
20897ac9a364SKalle Valo 
20907ac9a364SKalle Valo #define BT_COEX_ENABLE  (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
20917ac9a364SKalle Valo 
20927ac9a364SKalle Valo #define BT_LEAD_TIME_DEF (0x1E)
20937ac9a364SKalle Valo 
20947ac9a364SKalle Valo #define BT_MAX_KILL_DEF (0x5)
20957ac9a364SKalle Valo 
20967ac9a364SKalle Valo /*
20977ac9a364SKalle Valo  * C_BT_CONFIG = 0x9b (command, has simple generic response)
20987ac9a364SKalle Valo  *
20997ac9a364SKalle Valo  * 3945 and 4965 devices support hardware handshake with Bluetooth device on
21007ac9a364SKalle Valo  * same platform.  Bluetooth device alerts wireless device when it will Tx;
21017ac9a364SKalle Valo  * wireless device can delay or kill its own Tx to accommodate.
21027ac9a364SKalle Valo  */
21037ac9a364SKalle Valo struct il_bt_cmd {
21047ac9a364SKalle Valo 	u8 flags;
21057ac9a364SKalle Valo 	u8 lead_time;
21067ac9a364SKalle Valo 	u8 max_kill;
21077ac9a364SKalle Valo 	u8 reserved;
21087ac9a364SKalle Valo 	__le32 kill_ack_mask;
21097ac9a364SKalle Valo 	__le32 kill_cts_mask;
21107ac9a364SKalle Valo } __packed;
21117ac9a364SKalle Valo 
21127ac9a364SKalle Valo /******************************************************************************
21137ac9a364SKalle Valo  * (6)
21147ac9a364SKalle Valo  * Spectrum Management (802.11h) Commands, Responses, Notifications:
21157ac9a364SKalle Valo  *
21167ac9a364SKalle Valo  *****************************************************************************/
21177ac9a364SKalle Valo 
21187ac9a364SKalle Valo /*
21197ac9a364SKalle Valo  * Spectrum Management
21207ac9a364SKalle Valo  */
21217ac9a364SKalle Valo #define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK         | \
21227ac9a364SKalle Valo 				 RXON_FILTER_CTL2HOST_MSK        | \
21237ac9a364SKalle Valo 				 RXON_FILTER_ACCEPT_GRP_MSK      | \
21247ac9a364SKalle Valo 				 RXON_FILTER_DIS_DECRYPT_MSK     | \
21257ac9a364SKalle Valo 				 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
21267ac9a364SKalle Valo 				 RXON_FILTER_ASSOC_MSK           | \
21277ac9a364SKalle Valo 				 RXON_FILTER_BCON_AWARE_MSK)
21287ac9a364SKalle Valo 
21297ac9a364SKalle Valo struct il_measure_channel {
21307ac9a364SKalle Valo 	__le32 duration;	/* measurement duration in extended beacon
21317ac9a364SKalle Valo 				 * format */
21327ac9a364SKalle Valo 	u8 channel;		/* channel to measure */
21337ac9a364SKalle Valo 	u8 type;		/* see enum il_measure_type */
21347ac9a364SKalle Valo 	__le16 reserved;
21357ac9a364SKalle Valo } __packed;
21367ac9a364SKalle Valo 
21377ac9a364SKalle Valo /*
21387ac9a364SKalle Valo  * C_SPECTRUM_MEASUREMENT = 0x74 (command)
21397ac9a364SKalle Valo  */
21407ac9a364SKalle Valo struct il_spectrum_cmd {
21417ac9a364SKalle Valo 	__le16 len;		/* number of bytes starting from token */
21427ac9a364SKalle Valo 	u8 token;		/* token id */
21437ac9a364SKalle Valo 	u8 id;			/* measurement id -- 0 or 1 */
21447ac9a364SKalle Valo 	u8 origin;		/* 0 = TGh, 1 = other, 2 = TGk */
21457ac9a364SKalle Valo 	u8 periodic;		/* 1 = periodic */
21467ac9a364SKalle Valo 	__le16 path_loss_timeout;
21477ac9a364SKalle Valo 	__le32 start_time;	/* start time in extended beacon format */
21487ac9a364SKalle Valo 	__le32 reserved2;
21497ac9a364SKalle Valo 	__le32 flags;		/* rxon flags */
21507ac9a364SKalle Valo 	__le32 filter_flags;	/* rxon filter flags */
21517ac9a364SKalle Valo 	__le16 channel_count;	/* minimum 1, maximum 10 */
21527ac9a364SKalle Valo 	__le16 reserved3;
21537ac9a364SKalle Valo 	struct il_measure_channel channels[10];
21547ac9a364SKalle Valo } __packed;
21557ac9a364SKalle Valo 
21567ac9a364SKalle Valo /*
21577ac9a364SKalle Valo  * C_SPECTRUM_MEASUREMENT = 0x74 (response)
21587ac9a364SKalle Valo  */
21597ac9a364SKalle Valo struct il_spectrum_resp {
21607ac9a364SKalle Valo 	u8 token;
21617ac9a364SKalle Valo 	u8 id;			/* id of the prior command replaced, or 0xff */
21627ac9a364SKalle Valo 	__le16 status;		/* 0 - command will be handled
21637ac9a364SKalle Valo 				 * 1 - cannot handle (conflicts with another
21647ac9a364SKalle Valo 				 *     measurement) */
21657ac9a364SKalle Valo } __packed;
21667ac9a364SKalle Valo 
21677ac9a364SKalle Valo enum il_measurement_state {
21687ac9a364SKalle Valo 	IL_MEASUREMENT_START = 0,
21697ac9a364SKalle Valo 	IL_MEASUREMENT_STOP = 1,
21707ac9a364SKalle Valo };
21717ac9a364SKalle Valo 
21727ac9a364SKalle Valo enum il_measurement_status {
21737ac9a364SKalle Valo 	IL_MEASUREMENT_OK = 0,
21747ac9a364SKalle Valo 	IL_MEASUREMENT_CONCURRENT = 1,
21757ac9a364SKalle Valo 	IL_MEASUREMENT_CSA_CONFLICT = 2,
21767ac9a364SKalle Valo 	IL_MEASUREMENT_TGH_CONFLICT = 3,
21777ac9a364SKalle Valo 	/* 4-5 reserved */
21787ac9a364SKalle Valo 	IL_MEASUREMENT_STOPPED = 6,
21797ac9a364SKalle Valo 	IL_MEASUREMENT_TIMEOUT = 7,
21807ac9a364SKalle Valo 	IL_MEASUREMENT_PERIODIC_FAILED = 8,
21817ac9a364SKalle Valo };
21827ac9a364SKalle Valo 
21837ac9a364SKalle Valo #define NUM_ELEMENTS_IN_HISTOGRAM 8
21847ac9a364SKalle Valo 
21857ac9a364SKalle Valo struct il_measurement_histogram {
21867ac9a364SKalle Valo 	__le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];	/* in 0.8usec counts */
21877ac9a364SKalle Valo 	__le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];	/* in 1usec counts */
21887ac9a364SKalle Valo } __packed;
21897ac9a364SKalle Valo 
21907ac9a364SKalle Valo /* clear channel availability counters */
21917ac9a364SKalle Valo struct il_measurement_cca_counters {
21927ac9a364SKalle Valo 	__le32 ofdm;
21937ac9a364SKalle Valo 	__le32 cck;
21947ac9a364SKalle Valo } __packed;
21957ac9a364SKalle Valo 
21967ac9a364SKalle Valo enum il_measure_type {
21977ac9a364SKalle Valo 	IL_MEASURE_BASIC = (1 << 0),
21987ac9a364SKalle Valo 	IL_MEASURE_CHANNEL_LOAD = (1 << 1),
21997ac9a364SKalle Valo 	IL_MEASURE_HISTOGRAM_RPI = (1 << 2),
22007ac9a364SKalle Valo 	IL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
22017ac9a364SKalle Valo 	IL_MEASURE_FRAME = (1 << 4),
22027ac9a364SKalle Valo 	/* bits 5:6 are reserved */
22037ac9a364SKalle Valo 	IL_MEASURE_IDLE = (1 << 7),
22047ac9a364SKalle Valo };
22057ac9a364SKalle Valo 
22067ac9a364SKalle Valo /*
22077ac9a364SKalle Valo  * N_SPECTRUM_MEASUREMENT = 0x75 (notification only, not a command)
22087ac9a364SKalle Valo  */
22097ac9a364SKalle Valo struct il_spectrum_notification {
22107ac9a364SKalle Valo 	u8 id;			/* measurement id -- 0 or 1 */
22117ac9a364SKalle Valo 	u8 token;
22127ac9a364SKalle Valo 	u8 channel_idx;		/* idx in measurement channel list */
22137ac9a364SKalle Valo 	u8 state;		/* 0 - start, 1 - stop */
22147ac9a364SKalle Valo 	__le32 start_time;	/* lower 32-bits of TSF */
22157ac9a364SKalle Valo 	u8 band;		/* 0 - 5.2GHz, 1 - 2.4GHz */
22167ac9a364SKalle Valo 	u8 channel;
22177ac9a364SKalle Valo 	u8 type;		/* see enum il_measurement_type */
22187ac9a364SKalle Valo 	u8 reserved1;
22197ac9a364SKalle Valo 	/* NOTE:  cca_ofdm, cca_cck, basic_type, and histogram are only only
22207ac9a364SKalle Valo 	 * valid if applicable for measurement type requested. */
22217ac9a364SKalle Valo 	__le32 cca_ofdm;	/* cca fraction time in 40Mhz clock periods */
22227ac9a364SKalle Valo 	__le32 cca_cck;		/* cca fraction time in 44Mhz clock periods */
22237ac9a364SKalle Valo 	__le32 cca_time;	/* channel load time in usecs */
22247ac9a364SKalle Valo 	u8 basic_type;		/* 0 - bss, 1 - ofdm preamble, 2 -
22257ac9a364SKalle Valo 				 * unidentified */
22267ac9a364SKalle Valo 	u8 reserved2[3];
22277ac9a364SKalle Valo 	struct il_measurement_histogram histogram;
22287ac9a364SKalle Valo 	__le32 stop_time;	/* lower 32-bits of TSF */
22297ac9a364SKalle Valo 	__le32 status;		/* see il_measurement_status */
22307ac9a364SKalle Valo } __packed;
22317ac9a364SKalle Valo 
22327ac9a364SKalle Valo /******************************************************************************
22337ac9a364SKalle Valo  * (7)
22347ac9a364SKalle Valo  * Power Management Commands, Responses, Notifications:
22357ac9a364SKalle Valo  *
22367ac9a364SKalle Valo  *****************************************************************************/
22377ac9a364SKalle Valo 
22387ac9a364SKalle Valo /**
22397ac9a364SKalle Valo  * struct il_powertable_cmd - Power Table Command
22407ac9a364SKalle Valo  * @flags: See below:
22417ac9a364SKalle Valo  *
22427ac9a364SKalle Valo  * C_POWER_TBL = 0x77 (command, has simple generic response)
22437ac9a364SKalle Valo  *
22447ac9a364SKalle Valo  * PM allow:
22457ac9a364SKalle Valo  *   bit 0 - '0' Driver not allow power management
22467ac9a364SKalle Valo  *           '1' Driver allow PM (use rest of parameters)
22477ac9a364SKalle Valo  *
22487ac9a364SKalle Valo  * uCode send sleep notifications:
22497ac9a364SKalle Valo  *   bit 1 - '0' Don't send sleep notification
22507ac9a364SKalle Valo  *           '1' send sleep notification (SEND_PM_NOTIFICATION)
22517ac9a364SKalle Valo  *
22527ac9a364SKalle Valo  * Sleep over DTIM
22537ac9a364SKalle Valo  *   bit 2 - '0' PM have to walk up every DTIM
22547ac9a364SKalle Valo  *           '1' PM could sleep over DTIM till listen Interval.
22557ac9a364SKalle Valo  *
22567ac9a364SKalle Valo  * PCI power managed
22577ac9a364SKalle Valo  *   bit 3 - '0' (PCI_CFG_LINK_CTRL & 0x1)
22587ac9a364SKalle Valo  *           '1' !(PCI_CFG_LINK_CTRL & 0x1)
22597ac9a364SKalle Valo  *
22607ac9a364SKalle Valo  * Fast PD
22617ac9a364SKalle Valo  *   bit 4 - '1' Put radio to sleep when receiving frame for others
22627ac9a364SKalle Valo  *
22637ac9a364SKalle Valo  * Force sleep Modes
22647ac9a364SKalle Valo  *   bit 31/30- '00' use both mac/xtal sleeps
22657ac9a364SKalle Valo  *              '01' force Mac sleep
22667ac9a364SKalle Valo  *              '10' force xtal sleep
22677ac9a364SKalle Valo  *              '11' Illegal set
22687ac9a364SKalle Valo  *
22697ac9a364SKalle Valo  * NOTE: if sleep_interval[SLEEP_INTRVL_TBL_SIZE-1] > DTIM period then
22707ac9a364SKalle Valo  * ucode assume sleep over DTIM is allowed and we don't need to wake up
22717ac9a364SKalle Valo  * for every DTIM.
22727ac9a364SKalle Valo  */
22737ac9a364SKalle Valo #define IL_POWER_VEC_SIZE 5
22747ac9a364SKalle Valo 
22757ac9a364SKalle Valo #define IL_POWER_DRIVER_ALLOW_SLEEP_MSK		cpu_to_le16(BIT(0))
22767ac9a364SKalle Valo #define IL_POWER_SLEEP_OVER_DTIM_MSK		cpu_to_le16(BIT(2))
22777ac9a364SKalle Valo #define IL_POWER_PCI_PM_MSK			cpu_to_le16(BIT(3))
22787ac9a364SKalle Valo 
22797ac9a364SKalle Valo struct il3945_powertable_cmd {
22807ac9a364SKalle Valo 	__le16 flags;
22817ac9a364SKalle Valo 	u8 reserved[2];
22827ac9a364SKalle Valo 	__le32 rx_data_timeout;
22837ac9a364SKalle Valo 	__le32 tx_data_timeout;
22847ac9a364SKalle Valo 	__le32 sleep_interval[IL_POWER_VEC_SIZE];
22857ac9a364SKalle Valo } __packed;
22867ac9a364SKalle Valo 
22877ac9a364SKalle Valo struct il_powertable_cmd {
22887ac9a364SKalle Valo 	__le16 flags;
22897ac9a364SKalle Valo 	u8 keep_alive_seconds;	/* 3945 reserved */
22907ac9a364SKalle Valo 	u8 debug_flags;		/* 3945 reserved */
22917ac9a364SKalle Valo 	__le32 rx_data_timeout;
22927ac9a364SKalle Valo 	__le32 tx_data_timeout;
22937ac9a364SKalle Valo 	__le32 sleep_interval[IL_POWER_VEC_SIZE];
22947ac9a364SKalle Valo 	__le32 keep_alive_beacons;
22957ac9a364SKalle Valo } __packed;
22967ac9a364SKalle Valo 
22977ac9a364SKalle Valo /*
22987ac9a364SKalle Valo  * N_PM_SLEEP = 0x7A (notification only, not a command)
22997ac9a364SKalle Valo  * all devices identical.
23007ac9a364SKalle Valo  */
23017ac9a364SKalle Valo struct il_sleep_notification {
23027ac9a364SKalle Valo 	u8 pm_sleep_mode;
23037ac9a364SKalle Valo 	u8 pm_wakeup_src;
23047ac9a364SKalle Valo 	__le16 reserved;
23057ac9a364SKalle Valo 	__le32 sleep_time;
23067ac9a364SKalle Valo 	__le32 tsf_low;
23077ac9a364SKalle Valo 	__le32 bcon_timer;
23087ac9a364SKalle Valo } __packed;
23097ac9a364SKalle Valo 
23107ac9a364SKalle Valo /* Sleep states.  all devices identical. */
23117ac9a364SKalle Valo enum {
23127ac9a364SKalle Valo 	IL_PM_NO_SLEEP = 0,
23137ac9a364SKalle Valo 	IL_PM_SLP_MAC = 1,
23147ac9a364SKalle Valo 	IL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
23157ac9a364SKalle Valo 	IL_PM_SLP_FULL_MAC_CARD_STATE = 3,
23167ac9a364SKalle Valo 	IL_PM_SLP_PHY = 4,
23177ac9a364SKalle Valo 	IL_PM_SLP_REPENT = 5,
23187ac9a364SKalle Valo 	IL_PM_WAKEUP_BY_TIMER = 6,
23197ac9a364SKalle Valo 	IL_PM_WAKEUP_BY_DRIVER = 7,
23207ac9a364SKalle Valo 	IL_PM_WAKEUP_BY_RFKILL = 8,
23217ac9a364SKalle Valo 	/* 3 reserved */
23227ac9a364SKalle Valo 	IL_PM_NUM_OF_MODES = 12,
23237ac9a364SKalle Valo };
23247ac9a364SKalle Valo 
23257ac9a364SKalle Valo /*
23267ac9a364SKalle Valo  * N_CARD_STATE = 0xa1 (notification only, not a command)
23277ac9a364SKalle Valo  */
23287ac9a364SKalle Valo struct il_card_state_notif {
23297ac9a364SKalle Valo 	__le32 flags;
23307ac9a364SKalle Valo } __packed;
23317ac9a364SKalle Valo 
23327ac9a364SKalle Valo #define HW_CARD_DISABLED   0x01
23337ac9a364SKalle Valo #define SW_CARD_DISABLED   0x02
23347ac9a364SKalle Valo #define CT_CARD_DISABLED   0x04
23357ac9a364SKalle Valo #define RXON_CARD_DISABLED 0x10
23367ac9a364SKalle Valo 
23377ac9a364SKalle Valo struct il_ct_kill_config {
23387ac9a364SKalle Valo 	__le32 reserved;
23397ac9a364SKalle Valo 	__le32 critical_temperature_M;
23407ac9a364SKalle Valo 	__le32 critical_temperature_R;
23417ac9a364SKalle Valo } __packed;
23427ac9a364SKalle Valo 
23437ac9a364SKalle Valo /******************************************************************************
23447ac9a364SKalle Valo  * (8)
23457ac9a364SKalle Valo  * Scan Commands, Responses, Notifications:
23467ac9a364SKalle Valo  *
23477ac9a364SKalle Valo  *****************************************************************************/
23487ac9a364SKalle Valo 
23497ac9a364SKalle Valo #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
23507ac9a364SKalle Valo #define SCAN_CHANNEL_TYPE_ACTIVE  cpu_to_le32(1)
23517ac9a364SKalle Valo 
23527ac9a364SKalle Valo /**
23537ac9a364SKalle Valo  * struct il_scan_channel - entry in C_SCAN channel table
23547ac9a364SKalle Valo  *
23557ac9a364SKalle Valo  * One for each channel in the scan list.
23567ac9a364SKalle Valo  * Each channel can independently select:
23577ac9a364SKalle Valo  * 1)  SSID for directed active scans
23587ac9a364SKalle Valo  * 2)  Txpower setting (for rate specified within Tx command)
23597ac9a364SKalle Valo  * 3)  How long to stay on-channel (behavior may be modified by quiet_time,
23607ac9a364SKalle Valo  *     quiet_plcp_th, good_CRC_th)
23617ac9a364SKalle Valo  *
23627ac9a364SKalle Valo  * To avoid uCode errors, make sure the following are true (see comments
23637ac9a364SKalle Valo  * under struct il_scan_cmd about max_out_time and quiet_time):
23647ac9a364SKalle Valo  * 1)  If using passive_dwell (i.e. passive_dwell != 0):
23657ac9a364SKalle Valo  *     active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
23667ac9a364SKalle Valo  * 2)  quiet_time <= active_dwell
23677ac9a364SKalle Valo  * 3)  If restricting off-channel time (i.e. max_out_time !=0):
23687ac9a364SKalle Valo  *     passive_dwell < max_out_time
23697ac9a364SKalle Valo  *     active_dwell < max_out_time
23707ac9a364SKalle Valo  */
23717ac9a364SKalle Valo struct il3945_scan_channel {
23727ac9a364SKalle Valo 	/*
23737ac9a364SKalle Valo 	 * type is defined as:
23747ac9a364SKalle Valo 	 * 0:0 1 = active, 0 = passive
23757ac9a364SKalle Valo 	 * 1:4 SSID direct bit map; if a bit is set, then corresponding
23767ac9a364SKalle Valo 	 *     SSID IE is transmitted in probe request.
23777ac9a364SKalle Valo 	 * 5:7 reserved
23787ac9a364SKalle Valo 	 */
23797ac9a364SKalle Valo 	u8 type;
23807ac9a364SKalle Valo 	u8 channel;		/* band is selected by il3945_scan_cmd "flags" field */
23817ac9a364SKalle Valo 	struct il3945_tx_power tpc;
23827ac9a364SKalle Valo 	__le16 active_dwell;	/* in 1024-uSec TU (time units), typ 5-50 */
23837ac9a364SKalle Valo 	__le16 passive_dwell;	/* in 1024-uSec TU (time units), typ 20-500 */
23847ac9a364SKalle Valo } __packed;
23857ac9a364SKalle Valo 
23867ac9a364SKalle Valo /* set number of direct probes u8 type */
23877ac9a364SKalle Valo #define IL39_SCAN_PROBE_MASK(n) ((BIT(n) | (BIT(n) - BIT(1))))
23887ac9a364SKalle Valo 
23897ac9a364SKalle Valo struct il_scan_channel {
23907ac9a364SKalle Valo 	/*
23917ac9a364SKalle Valo 	 * type is defined as:
23927ac9a364SKalle Valo 	 * 0:0 1 = active, 0 = passive
23937ac9a364SKalle Valo 	 * 1:20 SSID direct bit map; if a bit is set, then corresponding
23947ac9a364SKalle Valo 	 *     SSID IE is transmitted in probe request.
23957ac9a364SKalle Valo 	 * 21:31 reserved
23967ac9a364SKalle Valo 	 */
23977ac9a364SKalle Valo 	__le32 type;
23987ac9a364SKalle Valo 	__le16 channel;		/* band is selected by il_scan_cmd "flags" field */
23997ac9a364SKalle Valo 	u8 tx_gain;		/* gain for analog radio */
24007ac9a364SKalle Valo 	u8 dsp_atten;		/* gain for DSP */
24017ac9a364SKalle Valo 	__le16 active_dwell;	/* in 1024-uSec TU (time units), typ 5-50 */
24027ac9a364SKalle Valo 	__le16 passive_dwell;	/* in 1024-uSec TU (time units), typ 20-500 */
24037ac9a364SKalle Valo } __packed;
24047ac9a364SKalle Valo 
24057ac9a364SKalle Valo /* set number of direct probes __le32 type */
24067ac9a364SKalle Valo #define IL_SCAN_PROBE_MASK(n)	cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
24077ac9a364SKalle Valo 
24087ac9a364SKalle Valo /**
24097ac9a364SKalle Valo  * struct il_ssid_ie - directed scan network information element
24107ac9a364SKalle Valo  *
24117ac9a364SKalle Valo  * Up to 20 of these may appear in C_SCAN (Note: Only 4 are in
24127ac9a364SKalle Valo  * 3945 SCAN api), selected by "type" bit field in struct il_scan_channel;
24137ac9a364SKalle Valo  * each channel may select different ssids from among the 20 (4) entries.
24147ac9a364SKalle Valo  * SSID IEs get transmitted in reverse order of entry.
24157ac9a364SKalle Valo  */
24167ac9a364SKalle Valo struct il_ssid_ie {
24177ac9a364SKalle Valo 	u8 id;
24187ac9a364SKalle Valo 	u8 len;
24197ac9a364SKalle Valo 	u8 ssid[32];
24207ac9a364SKalle Valo } __packed;
24217ac9a364SKalle Valo 
24227ac9a364SKalle Valo #define PROBE_OPTION_MAX_3945		4
24237ac9a364SKalle Valo #define PROBE_OPTION_MAX		20
24247ac9a364SKalle Valo #define TX_CMD_LIFE_TIME_INFINITE	cpu_to_le32(0xFFFFFFFF)
24257ac9a364SKalle Valo #define IL_GOOD_CRC_TH_DISABLED	0
24267ac9a364SKalle Valo #define IL_GOOD_CRC_TH_DEFAULT		cpu_to_le16(1)
24277ac9a364SKalle Valo #define IL_GOOD_CRC_TH_NEVER		cpu_to_le16(0xffff)
24287ac9a364SKalle Valo #define IL_MAX_SCAN_SIZE 1024
24297ac9a364SKalle Valo #define IL_MAX_CMD_SIZE 4096
24307ac9a364SKalle Valo 
24317ac9a364SKalle Valo /*
24327ac9a364SKalle Valo  * C_SCAN = 0x80 (command)
24337ac9a364SKalle Valo  *
24347ac9a364SKalle Valo  * The hardware scan command is very powerful; the driver can set it up to
24357ac9a364SKalle Valo  * maintain (relatively) normal network traffic while doing a scan in the
24367ac9a364SKalle Valo  * background.  The max_out_time and suspend_time control the ratio of how
24377ac9a364SKalle Valo  * long the device stays on an associated network channel ("service channel")
24387ac9a364SKalle Valo  * vs. how long it's away from the service channel, i.e. tuned to other channels
24397ac9a364SKalle Valo  * for scanning.
24407ac9a364SKalle Valo  *
24417ac9a364SKalle Valo  * max_out_time is the max time off-channel (in usec), and suspend_time
24427ac9a364SKalle Valo  * is how long (in "extended beacon" format) that the scan is "suspended"
24437ac9a364SKalle Valo  * after returning to the service channel.  That is, suspend_time is the
24447ac9a364SKalle Valo  * time that we stay on the service channel, doing normal work, between
24457ac9a364SKalle Valo  * scan segments.  The driver may set these parameters differently to support
24467ac9a364SKalle Valo  * scanning when associated vs. not associated, and light vs. heavy traffic
24477ac9a364SKalle Valo  * loads when associated.
24487ac9a364SKalle Valo  *
24497ac9a364SKalle Valo  * After receiving this command, the device's scan engine does the following;
24507ac9a364SKalle Valo  *
24517ac9a364SKalle Valo  * 1)  Sends SCAN_START notification to driver
24527ac9a364SKalle Valo  * 2)  Checks to see if it has time to do scan for one channel
24537ac9a364SKalle Valo  * 3)  Sends NULL packet, with power-save (PS) bit set to 1,
24547ac9a364SKalle Valo  *     to tell AP that we're going off-channel
24557ac9a364SKalle Valo  * 4)  Tunes to first channel in scan list, does active or passive scan
24567ac9a364SKalle Valo  * 5)  Sends SCAN_RESULT notification to driver
24577ac9a364SKalle Valo  * 6)  Checks to see if it has time to do scan on *next* channel in list
24587ac9a364SKalle Valo  * 7)  Repeats 4-6 until it no longer has time to scan the next channel
24597ac9a364SKalle Valo  *     before max_out_time expires
24607ac9a364SKalle Valo  * 8)  Returns to service channel
24617ac9a364SKalle Valo  * 9)  Sends NULL packet with PS=0 to tell AP that we're back
24627ac9a364SKalle Valo  * 10) Stays on service channel until suspend_time expires
24637ac9a364SKalle Valo  * 11) Repeats entire process 2-10 until list is complete
24647ac9a364SKalle Valo  * 12) Sends SCAN_COMPLETE notification
24657ac9a364SKalle Valo  *
24667ac9a364SKalle Valo  * For fast, efficient scans, the scan command also has support for staying on
24677ac9a364SKalle Valo  * a channel for just a short time, if doing active scanning and getting no
24687ac9a364SKalle Valo  * responses to the transmitted probe request.  This time is controlled by
24697ac9a364SKalle Valo  * quiet_time, and the number of received packets below which a channel is
24707ac9a364SKalle Valo  * considered "quiet" is controlled by quiet_plcp_threshold.
24717ac9a364SKalle Valo  *
24727ac9a364SKalle Valo  * For active scanning on channels that have regulatory restrictions against
24737ac9a364SKalle Valo  * blindly transmitting, the scan can listen before transmitting, to make sure
24747ac9a364SKalle Valo  * that there is already legitimate activity on the channel.  If enough
24757ac9a364SKalle Valo  * packets are cleanly received on the channel (controlled by good_CRC_th,
24767ac9a364SKalle Valo  * typical value 1), the scan engine starts transmitting probe requests.
24777ac9a364SKalle Valo  *
24787ac9a364SKalle Valo  * Driver must use separate scan commands for 2.4 vs. 5 GHz bands.
24797ac9a364SKalle Valo  *
24807ac9a364SKalle Valo  * To avoid uCode errors, see timing restrictions described under
24817ac9a364SKalle Valo  * struct il_scan_channel.
24827ac9a364SKalle Valo  */
24837ac9a364SKalle Valo 
24847ac9a364SKalle Valo struct il3945_scan_cmd {
24857ac9a364SKalle Valo 	__le16 len;
24867ac9a364SKalle Valo 	u8 reserved0;
24877ac9a364SKalle Valo 	u8 channel_count;	/* # channels in channel list */
24887ac9a364SKalle Valo 	__le16 quiet_time;	/* dwell only this # millisecs on quiet channel
24897ac9a364SKalle Valo 				 * (only for active scan) */
24907ac9a364SKalle Valo 	__le16 quiet_plcp_th;	/* quiet chnl is < this # pkts (typ. 1) */
24917ac9a364SKalle Valo 	__le16 good_CRC_th;	/* passive -> active promotion threshold */
24927ac9a364SKalle Valo 	__le16 reserved1;
24937ac9a364SKalle Valo 	__le32 max_out_time;	/* max usec to be away from associated (service)
24947ac9a364SKalle Valo 				 * channel */
24957ac9a364SKalle Valo 	__le32 suspend_time;	/* pause scan this long (in "extended beacon
24967ac9a364SKalle Valo 				 * format") when returning to service channel:
24977ac9a364SKalle Valo 				 * 3945; 31:24 # beacons, 19:0 additional usec,
24987ac9a364SKalle Valo 				 * 4965; 31:22 # beacons, 21:0 additional usec.
24997ac9a364SKalle Valo 				 */
25007ac9a364SKalle Valo 	__le32 flags;		/* RXON_FLG_* */
25017ac9a364SKalle Valo 	__le32 filter_flags;	/* RXON_FILTER_* */
25027ac9a364SKalle Valo 
25037ac9a364SKalle Valo 	/* For active scans (set to all-0s for passive scans).
25047ac9a364SKalle Valo 	 * Does not include payload.  Must specify Tx rate; no rate scaling. */
25057ac9a364SKalle Valo 	struct il3945_tx_cmd tx_cmd;
25067ac9a364SKalle Valo 
25077ac9a364SKalle Valo 	/* For directed active scans (set to all-0s otherwise) */
25087ac9a364SKalle Valo 	struct il_ssid_ie direct_scan[PROBE_OPTION_MAX_3945];
25097ac9a364SKalle Valo 
25107ac9a364SKalle Valo 	/*
25117ac9a364SKalle Valo 	 * Probe request frame, followed by channel list.
25127ac9a364SKalle Valo 	 *
25137ac9a364SKalle Valo 	 * Size of probe request frame is specified by byte count in tx_cmd.
25147ac9a364SKalle Valo 	 * Channel list follows immediately after probe request frame.
25157ac9a364SKalle Valo 	 * Number of channels in list is specified by channel_count.
25167ac9a364SKalle Valo 	 * Each channel in list is of type:
25177ac9a364SKalle Valo 	 *
25187ac9a364SKalle Valo 	 * struct il3945_scan_channel channels[0];
25197ac9a364SKalle Valo 	 *
25207ac9a364SKalle Valo 	 * NOTE:  Only one band of channels can be scanned per pass.  You
25217ac9a364SKalle Valo 	 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
25227ac9a364SKalle Valo 	 * for one scan to complete (i.e. receive N_SCAN_COMPLETE)
25237ac9a364SKalle Valo 	 * before requesting another scan.
25247ac9a364SKalle Valo 	 */
25258863b121SGustavo A. R. Silva 	u8 data[];
25267ac9a364SKalle Valo } __packed;
25277ac9a364SKalle Valo 
25287ac9a364SKalle Valo struct il_scan_cmd {
25297ac9a364SKalle Valo 	__le16 len;
25307ac9a364SKalle Valo 	u8 reserved0;
25317ac9a364SKalle Valo 	u8 channel_count;	/* # channels in channel list */
25327ac9a364SKalle Valo 	__le16 quiet_time;	/* dwell only this # millisecs on quiet channel
25337ac9a364SKalle Valo 				 * (only for active scan) */
25347ac9a364SKalle Valo 	__le16 quiet_plcp_th;	/* quiet chnl is < this # pkts (typ. 1) */
25357ac9a364SKalle Valo 	__le16 good_CRC_th;	/* passive -> active promotion threshold */
25367ac9a364SKalle Valo 	__le16 rx_chain;	/* RXON_RX_CHAIN_* */
25377ac9a364SKalle Valo 	__le32 max_out_time;	/* max usec to be away from associated (service)
25387ac9a364SKalle Valo 				 * channel */
25397ac9a364SKalle Valo 	__le32 suspend_time;	/* pause scan this long (in "extended beacon
25407ac9a364SKalle Valo 				 * format") when returning to service chnl:
25417ac9a364SKalle Valo 				 * 3945; 31:24 # beacons, 19:0 additional usec,
25427ac9a364SKalle Valo 				 * 4965; 31:22 # beacons, 21:0 additional usec.
25437ac9a364SKalle Valo 				 */
25447ac9a364SKalle Valo 	__le32 flags;		/* RXON_FLG_* */
25457ac9a364SKalle Valo 	__le32 filter_flags;	/* RXON_FILTER_* */
25467ac9a364SKalle Valo 
25477ac9a364SKalle Valo 	/* For active scans (set to all-0s for passive scans).
25487ac9a364SKalle Valo 	 * Does not include payload.  Must specify Tx rate; no rate scaling. */
25497ac9a364SKalle Valo 	struct il_tx_cmd tx_cmd;
25507ac9a364SKalle Valo 
25517ac9a364SKalle Valo 	/* For directed active scans (set to all-0s otherwise) */
25527ac9a364SKalle Valo 	struct il_ssid_ie direct_scan[PROBE_OPTION_MAX];
25537ac9a364SKalle Valo 
25547ac9a364SKalle Valo 	/*
25557ac9a364SKalle Valo 	 * Probe request frame, followed by channel list.
25567ac9a364SKalle Valo 	 *
25577ac9a364SKalle Valo 	 * Size of probe request frame is specified by byte count in tx_cmd.
25587ac9a364SKalle Valo 	 * Channel list follows immediately after probe request frame.
25597ac9a364SKalle Valo 	 * Number of channels in list is specified by channel_count.
25607ac9a364SKalle Valo 	 * Each channel in list is of type:
25617ac9a364SKalle Valo 	 *
25627ac9a364SKalle Valo 	 * struct il_scan_channel channels[0];
25637ac9a364SKalle Valo 	 *
25647ac9a364SKalle Valo 	 * NOTE:  Only one band of channels can be scanned per pass.  You
25657ac9a364SKalle Valo 	 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
25667ac9a364SKalle Valo 	 * for one scan to complete (i.e. receive N_SCAN_COMPLETE)
25677ac9a364SKalle Valo 	 * before requesting another scan.
25687ac9a364SKalle Valo 	 */
25698863b121SGustavo A. R. Silva 	u8 data[];
25707ac9a364SKalle Valo } __packed;
25717ac9a364SKalle Valo 
25727ac9a364SKalle Valo /* Can abort will notify by complete notification with abort status. */
25737ac9a364SKalle Valo #define CAN_ABORT_STATUS	cpu_to_le32(0x1)
25747ac9a364SKalle Valo /* complete notification statuses */
25757ac9a364SKalle Valo #define ABORT_STATUS            0x2
25767ac9a364SKalle Valo 
25777ac9a364SKalle Valo /*
25787ac9a364SKalle Valo  * C_SCAN = 0x80 (response)
25797ac9a364SKalle Valo  */
25807ac9a364SKalle Valo struct il_scanreq_notification {
25817ac9a364SKalle Valo 	__le32 status;		/* 1: okay, 2: cannot fulfill request */
25827ac9a364SKalle Valo } __packed;
25837ac9a364SKalle Valo 
25847ac9a364SKalle Valo /*
25857ac9a364SKalle Valo  * N_SCAN_START = 0x82 (notification only, not a command)
25867ac9a364SKalle Valo  */
25877ac9a364SKalle Valo struct il_scanstart_notification {
25887ac9a364SKalle Valo 	__le32 tsf_low;
25897ac9a364SKalle Valo 	__le32 tsf_high;
25907ac9a364SKalle Valo 	__le32 beacon_timer;
25917ac9a364SKalle Valo 	u8 channel;
25927ac9a364SKalle Valo 	u8 band;
25937ac9a364SKalle Valo 	u8 reserved[2];
25947ac9a364SKalle Valo 	__le32 status;
25957ac9a364SKalle Valo } __packed;
25967ac9a364SKalle Valo 
25977ac9a364SKalle Valo #define  SCAN_OWNER_STATUS 0x1
25987ac9a364SKalle Valo #define  MEASURE_OWNER_STATUS 0x2
25997ac9a364SKalle Valo 
26007ac9a364SKalle Valo #define IL_PROBE_STATUS_OK		0
26017ac9a364SKalle Valo #define IL_PROBE_STATUS_TX_FAILED	BIT(0)
26027ac9a364SKalle Valo /* error statuses combined with TX_FAILED */
26037ac9a364SKalle Valo #define IL_PROBE_STATUS_FAIL_TTL	BIT(1)
26047ac9a364SKalle Valo #define IL_PROBE_STATUS_FAIL_BT	BIT(2)
26057ac9a364SKalle Valo 
26067ac9a364SKalle Valo #define NUMBER_OF_STATS 1	/* first __le32 is good CRC */
26077ac9a364SKalle Valo /*
26087ac9a364SKalle Valo  * N_SCAN_RESULTS = 0x83 (notification only, not a command)
26097ac9a364SKalle Valo  */
26107ac9a364SKalle Valo struct il_scanresults_notification {
26117ac9a364SKalle Valo 	u8 channel;
26127ac9a364SKalle Valo 	u8 band;
26137ac9a364SKalle Valo 	u8 probe_status;
26147ac9a364SKalle Valo 	u8 num_probe_not_sent;	/* not enough time to send */
26157ac9a364SKalle Valo 	__le32 tsf_low;
26167ac9a364SKalle Valo 	__le32 tsf_high;
26177ac9a364SKalle Valo 	__le32 stats[NUMBER_OF_STATS];
26187ac9a364SKalle Valo } __packed;
26197ac9a364SKalle Valo 
26207ac9a364SKalle Valo /*
26217ac9a364SKalle Valo  * N_SCAN_COMPLETE = 0x84 (notification only, not a command)
26227ac9a364SKalle Valo  */
26237ac9a364SKalle Valo struct il_scancomplete_notification {
26247ac9a364SKalle Valo 	u8 scanned_channels;
26257ac9a364SKalle Valo 	u8 status;
26267ac9a364SKalle Valo 	u8 last_channel;
26277ac9a364SKalle Valo 	__le32 tsf_low;
26287ac9a364SKalle Valo 	__le32 tsf_high;
26297ac9a364SKalle Valo } __packed;
26307ac9a364SKalle Valo 
26317ac9a364SKalle Valo /******************************************************************************
26327ac9a364SKalle Valo  * (9)
26337ac9a364SKalle Valo  * IBSS/AP Commands and Notifications:
26347ac9a364SKalle Valo  *
26357ac9a364SKalle Valo  *****************************************************************************/
26367ac9a364SKalle Valo 
26377ac9a364SKalle Valo enum il_ibss_manager {
26387ac9a364SKalle Valo 	IL_NOT_IBSS_MANAGER = 0,
26397ac9a364SKalle Valo 	IL_IBSS_MANAGER = 1,
26407ac9a364SKalle Valo };
26417ac9a364SKalle Valo 
26427ac9a364SKalle Valo /*
26437ac9a364SKalle Valo  * N_BEACON = 0x90 (notification only, not a command)
26447ac9a364SKalle Valo  */
26457ac9a364SKalle Valo 
26467ac9a364SKalle Valo struct il3945_beacon_notif {
26477ac9a364SKalle Valo 	struct il3945_tx_resp beacon_notify_hdr;
26487ac9a364SKalle Valo 	__le32 low_tsf;
26497ac9a364SKalle Valo 	__le32 high_tsf;
26507ac9a364SKalle Valo 	__le32 ibss_mgr_status;
26517ac9a364SKalle Valo } __packed;
26527ac9a364SKalle Valo 
26537ac9a364SKalle Valo struct il4965_beacon_notif {
26547ac9a364SKalle Valo 	struct il4965_tx_resp beacon_notify_hdr;
26557ac9a364SKalle Valo 	__le32 low_tsf;
26567ac9a364SKalle Valo 	__le32 high_tsf;
26577ac9a364SKalle Valo 	__le32 ibss_mgr_status;
26587ac9a364SKalle Valo } __packed;
26597ac9a364SKalle Valo 
26607ac9a364SKalle Valo /*
26617ac9a364SKalle Valo  * C_TX_BEACON= 0x91 (command, has simple generic response)
26627ac9a364SKalle Valo  */
26637ac9a364SKalle Valo 
26647ac9a364SKalle Valo struct il3945_tx_beacon_cmd {
26657ac9a364SKalle Valo 	struct il3945_tx_cmd tx;
26667ac9a364SKalle Valo 	__le16 tim_idx;
26677ac9a364SKalle Valo 	u8 tim_size;
26687ac9a364SKalle Valo 	u8 reserved1;
26698863b121SGustavo A. R. Silva 	struct ieee80211_hdr frame[];	/* beacon frame */
26707ac9a364SKalle Valo } __packed;
26717ac9a364SKalle Valo 
26727ac9a364SKalle Valo struct il_tx_beacon_cmd {
26737ac9a364SKalle Valo 	struct il_tx_cmd tx;
26747ac9a364SKalle Valo 	__le16 tim_idx;
26757ac9a364SKalle Valo 	u8 tim_size;
26767ac9a364SKalle Valo 	u8 reserved1;
26778863b121SGustavo A. R. Silva 	struct ieee80211_hdr frame[];	/* beacon frame */
26787ac9a364SKalle Valo } __packed;
26797ac9a364SKalle Valo 
26807ac9a364SKalle Valo /******************************************************************************
26817ac9a364SKalle Valo  * (10)
26827ac9a364SKalle Valo  * Statistics Commands and Notifications:
26837ac9a364SKalle Valo  *
26847ac9a364SKalle Valo  *****************************************************************************/
26857ac9a364SKalle Valo 
26867ac9a364SKalle Valo #define IL_TEMP_CONVERT 260
26877ac9a364SKalle Valo 
26887ac9a364SKalle Valo #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
26897ac9a364SKalle Valo #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
26907ac9a364SKalle Valo #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
26917ac9a364SKalle Valo 
26927ac9a364SKalle Valo /* Used for passing to driver number of successes and failures per rate */
26937ac9a364SKalle Valo struct rate_histogram {
26947ac9a364SKalle Valo 	union {
26957ac9a364SKalle Valo 		__le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
26967ac9a364SKalle Valo 		__le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
26977ac9a364SKalle Valo 		__le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
26987ac9a364SKalle Valo 	} success;
26997ac9a364SKalle Valo 	union {
27007ac9a364SKalle Valo 		__le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
27017ac9a364SKalle Valo 		__le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
27027ac9a364SKalle Valo 		__le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
27037ac9a364SKalle Valo 	} failed;
27047ac9a364SKalle Valo } __packed;
27057ac9a364SKalle Valo 
27067ac9a364SKalle Valo /* stats command response */
27077ac9a364SKalle Valo 
27087ac9a364SKalle Valo struct iwl39_stats_rx_phy {
27097ac9a364SKalle Valo 	__le32 ina_cnt;
27107ac9a364SKalle Valo 	__le32 fina_cnt;
27117ac9a364SKalle Valo 	__le32 plcp_err;
27127ac9a364SKalle Valo 	__le32 crc32_err;
27137ac9a364SKalle Valo 	__le32 overrun_err;
27147ac9a364SKalle Valo 	__le32 early_overrun_err;
27157ac9a364SKalle Valo 	__le32 crc32_good;
27167ac9a364SKalle Valo 	__le32 false_alarm_cnt;
27177ac9a364SKalle Valo 	__le32 fina_sync_err_cnt;
27187ac9a364SKalle Valo 	__le32 sfd_timeout;
27197ac9a364SKalle Valo 	__le32 fina_timeout;
27207ac9a364SKalle Valo 	__le32 unresponded_rts;
27217ac9a364SKalle Valo 	__le32 rxe_frame_limit_overrun;
27227ac9a364SKalle Valo 	__le32 sent_ack_cnt;
27237ac9a364SKalle Valo 	__le32 sent_cts_cnt;
27247ac9a364SKalle Valo } __packed;
27257ac9a364SKalle Valo 
27267ac9a364SKalle Valo struct iwl39_stats_rx_non_phy {
27277ac9a364SKalle Valo 	__le32 bogus_cts;	/* CTS received when not expecting CTS */
27287ac9a364SKalle Valo 	__le32 bogus_ack;	/* ACK received when not expecting ACK */
27297ac9a364SKalle Valo 	__le32 non_bssid_frames;	/* number of frames with BSSID that
27307ac9a364SKalle Valo 					 * doesn't belong to the STA BSSID */
27317ac9a364SKalle Valo 	__le32 filtered_frames;	/* count frames that were dumped in the
27327ac9a364SKalle Valo 				 * filtering process */
27337ac9a364SKalle Valo 	__le32 non_channel_beacons;	/* beacons with our bss id but not on
27347ac9a364SKalle Valo 					 * our serving channel */
27357ac9a364SKalle Valo } __packed;
27367ac9a364SKalle Valo 
27377ac9a364SKalle Valo struct iwl39_stats_rx {
27387ac9a364SKalle Valo 	struct iwl39_stats_rx_phy ofdm;
27397ac9a364SKalle Valo 	struct iwl39_stats_rx_phy cck;
27407ac9a364SKalle Valo 	struct iwl39_stats_rx_non_phy general;
27417ac9a364SKalle Valo } __packed;
27427ac9a364SKalle Valo 
27437ac9a364SKalle Valo struct iwl39_stats_tx {
27447ac9a364SKalle Valo 	__le32 preamble_cnt;
27457ac9a364SKalle Valo 	__le32 rx_detected_cnt;
27467ac9a364SKalle Valo 	__le32 bt_prio_defer_cnt;
27477ac9a364SKalle Valo 	__le32 bt_prio_kill_cnt;
27487ac9a364SKalle Valo 	__le32 few_bytes_cnt;
27497ac9a364SKalle Valo 	__le32 cts_timeout;
27507ac9a364SKalle Valo 	__le32 ack_timeout;
27517ac9a364SKalle Valo 	__le32 expected_ack_cnt;
27527ac9a364SKalle Valo 	__le32 actual_ack_cnt;
27537ac9a364SKalle Valo } __packed;
27547ac9a364SKalle Valo 
27557ac9a364SKalle Valo struct stats_dbg {
27567ac9a364SKalle Valo 	__le32 burst_check;
27577ac9a364SKalle Valo 	__le32 burst_count;
27587ac9a364SKalle Valo 	__le32 wait_for_silence_timeout_cnt;
27597ac9a364SKalle Valo 	__le32 reserved[3];
27607ac9a364SKalle Valo } __packed;
27617ac9a364SKalle Valo 
27627ac9a364SKalle Valo struct iwl39_stats_div {
27637ac9a364SKalle Valo 	__le32 tx_on_a;
27647ac9a364SKalle Valo 	__le32 tx_on_b;
27657ac9a364SKalle Valo 	__le32 exec_time;
27667ac9a364SKalle Valo 	__le32 probe_time;
27677ac9a364SKalle Valo } __packed;
27687ac9a364SKalle Valo 
27697ac9a364SKalle Valo struct iwl39_stats_general {
27707ac9a364SKalle Valo 	__le32 temperature;
27717ac9a364SKalle Valo 	struct stats_dbg dbg;
27727ac9a364SKalle Valo 	__le32 sleep_time;
27737ac9a364SKalle Valo 	__le32 slots_out;
27747ac9a364SKalle Valo 	__le32 slots_idle;
27757ac9a364SKalle Valo 	__le32 ttl_timestamp;
27767ac9a364SKalle Valo 	struct iwl39_stats_div div;
27777ac9a364SKalle Valo } __packed;
27787ac9a364SKalle Valo 
27797ac9a364SKalle Valo struct stats_rx_phy {
27807ac9a364SKalle Valo 	__le32 ina_cnt;
27817ac9a364SKalle Valo 	__le32 fina_cnt;
27827ac9a364SKalle Valo 	__le32 plcp_err;
27837ac9a364SKalle Valo 	__le32 crc32_err;
27847ac9a364SKalle Valo 	__le32 overrun_err;
27857ac9a364SKalle Valo 	__le32 early_overrun_err;
27867ac9a364SKalle Valo 	__le32 crc32_good;
27877ac9a364SKalle Valo 	__le32 false_alarm_cnt;
27887ac9a364SKalle Valo 	__le32 fina_sync_err_cnt;
27897ac9a364SKalle Valo 	__le32 sfd_timeout;
27907ac9a364SKalle Valo 	__le32 fina_timeout;
27917ac9a364SKalle Valo 	__le32 unresponded_rts;
27927ac9a364SKalle Valo 	__le32 rxe_frame_limit_overrun;
27937ac9a364SKalle Valo 	__le32 sent_ack_cnt;
27947ac9a364SKalle Valo 	__le32 sent_cts_cnt;
27957ac9a364SKalle Valo 	__le32 sent_ba_rsp_cnt;
27967ac9a364SKalle Valo 	__le32 dsp_self_kill;
27977ac9a364SKalle Valo 	__le32 mh_format_err;
27987ac9a364SKalle Valo 	__le32 re_acq_main_rssi_sum;
27997ac9a364SKalle Valo 	__le32 reserved3;
28007ac9a364SKalle Valo } __packed;
28017ac9a364SKalle Valo 
28027ac9a364SKalle Valo struct stats_rx_ht_phy {
28037ac9a364SKalle Valo 	__le32 plcp_err;
28047ac9a364SKalle Valo 	__le32 overrun_err;
28057ac9a364SKalle Valo 	__le32 early_overrun_err;
28067ac9a364SKalle Valo 	__le32 crc32_good;
28077ac9a364SKalle Valo 	__le32 crc32_err;
28087ac9a364SKalle Valo 	__le32 mh_format_err;
28097ac9a364SKalle Valo 	__le32 agg_crc32_good;
28107ac9a364SKalle Valo 	__le32 agg_mpdu_cnt;
28117ac9a364SKalle Valo 	__le32 agg_cnt;
28127ac9a364SKalle Valo 	__le32 unsupport_mcs;
28137ac9a364SKalle Valo } __packed;
28147ac9a364SKalle Valo 
28157ac9a364SKalle Valo #define INTERFERENCE_DATA_AVAILABLE      cpu_to_le32(1)
28167ac9a364SKalle Valo 
28177ac9a364SKalle Valo struct stats_rx_non_phy {
28187ac9a364SKalle Valo 	__le32 bogus_cts;	/* CTS received when not expecting CTS */
28197ac9a364SKalle Valo 	__le32 bogus_ack;	/* ACK received when not expecting ACK */
28207ac9a364SKalle Valo 	__le32 non_bssid_frames;	/* number of frames with BSSID that
28217ac9a364SKalle Valo 					 * doesn't belong to the STA BSSID */
28227ac9a364SKalle Valo 	__le32 filtered_frames;	/* count frames that were dumped in the
28237ac9a364SKalle Valo 				 * filtering process */
28247ac9a364SKalle Valo 	__le32 non_channel_beacons;	/* beacons with our bss id but not on
28257ac9a364SKalle Valo 					 * our serving channel */
28267ac9a364SKalle Valo 	__le32 channel_beacons;	/* beacons with our bss id and in our
28277ac9a364SKalle Valo 				 * serving channel */
28287ac9a364SKalle Valo 	__le32 num_missed_bcon;	/* number of missed beacons */
28297ac9a364SKalle Valo 	__le32 adc_rx_saturation_time;	/* count in 0.8us units the time the
28307ac9a364SKalle Valo 					 * ADC was in saturation */
28317ac9a364SKalle Valo 	__le32 ina_detection_search_time;	/* total time (in 0.8us) searched
28327ac9a364SKalle Valo 						 * for INA */
28337ac9a364SKalle Valo 	__le32 beacon_silence_rssi_a;	/* RSSI silence after beacon frame */
28347ac9a364SKalle Valo 	__le32 beacon_silence_rssi_b;	/* RSSI silence after beacon frame */
28357ac9a364SKalle Valo 	__le32 beacon_silence_rssi_c;	/* RSSI silence after beacon frame */
28367ac9a364SKalle Valo 	__le32 interference_data_flag;	/* flag for interference data
28377ac9a364SKalle Valo 					 * availability. 1 when data is
28387ac9a364SKalle Valo 					 * available. */
28397ac9a364SKalle Valo 	__le32 channel_load;	/* counts RX Enable time in uSec */
28407ac9a364SKalle Valo 	__le32 dsp_false_alarms;	/* DSP false alarm (both OFDM
28417ac9a364SKalle Valo 					 * and CCK) counter */
28427ac9a364SKalle Valo 	__le32 beacon_rssi_a;
28437ac9a364SKalle Valo 	__le32 beacon_rssi_b;
28447ac9a364SKalle Valo 	__le32 beacon_rssi_c;
28457ac9a364SKalle Valo 	__le32 beacon_energy_a;
28467ac9a364SKalle Valo 	__le32 beacon_energy_b;
28477ac9a364SKalle Valo 	__le32 beacon_energy_c;
28487ac9a364SKalle Valo } __packed;
28497ac9a364SKalle Valo 
28507ac9a364SKalle Valo struct stats_rx {
28517ac9a364SKalle Valo 	struct stats_rx_phy ofdm;
28527ac9a364SKalle Valo 	struct stats_rx_phy cck;
28537ac9a364SKalle Valo 	struct stats_rx_non_phy general;
28547ac9a364SKalle Valo 	struct stats_rx_ht_phy ofdm_ht;
28557ac9a364SKalle Valo } __packed;
28567ac9a364SKalle Valo 
28577ac9a364SKalle Valo /**
28587ac9a364SKalle Valo  * struct stats_tx_power - current tx power
28597ac9a364SKalle Valo  *
28607ac9a364SKalle Valo  * @ant_a: current tx power on chain a in 1/2 dB step
28617ac9a364SKalle Valo  * @ant_b: current tx power on chain b in 1/2 dB step
28627ac9a364SKalle Valo  * @ant_c: current tx power on chain c in 1/2 dB step
28637ac9a364SKalle Valo  */
28647ac9a364SKalle Valo struct stats_tx_power {
28657ac9a364SKalle Valo 	u8 ant_a;
28667ac9a364SKalle Valo 	u8 ant_b;
28677ac9a364SKalle Valo 	u8 ant_c;
28687ac9a364SKalle Valo 	u8 reserved;
28697ac9a364SKalle Valo } __packed;
28707ac9a364SKalle Valo 
28717ac9a364SKalle Valo struct stats_tx_non_phy_agg {
28727ac9a364SKalle Valo 	__le32 ba_timeout;
28737ac9a364SKalle Valo 	__le32 ba_reschedule_frames;
28747ac9a364SKalle Valo 	__le32 scd_query_agg_frame_cnt;
28757ac9a364SKalle Valo 	__le32 scd_query_no_agg;
28767ac9a364SKalle Valo 	__le32 scd_query_agg;
28777ac9a364SKalle Valo 	__le32 scd_query_mismatch;
28787ac9a364SKalle Valo 	__le32 frame_not_ready;
28797ac9a364SKalle Valo 	__le32 underrun;
28807ac9a364SKalle Valo 	__le32 bt_prio_kill;
28817ac9a364SKalle Valo 	__le32 rx_ba_rsp_cnt;
28827ac9a364SKalle Valo } __packed;
28837ac9a364SKalle Valo 
28847ac9a364SKalle Valo struct stats_tx {
28857ac9a364SKalle Valo 	__le32 preamble_cnt;
28867ac9a364SKalle Valo 	__le32 rx_detected_cnt;
28877ac9a364SKalle Valo 	__le32 bt_prio_defer_cnt;
28887ac9a364SKalle Valo 	__le32 bt_prio_kill_cnt;
28897ac9a364SKalle Valo 	__le32 few_bytes_cnt;
28907ac9a364SKalle Valo 	__le32 cts_timeout;
28917ac9a364SKalle Valo 	__le32 ack_timeout;
28927ac9a364SKalle Valo 	__le32 expected_ack_cnt;
28937ac9a364SKalle Valo 	__le32 actual_ack_cnt;
28947ac9a364SKalle Valo 	__le32 dump_msdu_cnt;
28957ac9a364SKalle Valo 	__le32 burst_abort_next_frame_mismatch_cnt;
28967ac9a364SKalle Valo 	__le32 burst_abort_missing_next_frame_cnt;
28977ac9a364SKalle Valo 	__le32 cts_timeout_collision;
28987ac9a364SKalle Valo 	__le32 ack_or_ba_timeout_collision;
28997ac9a364SKalle Valo 	struct stats_tx_non_phy_agg agg;
29007ac9a364SKalle Valo 
29017ac9a364SKalle Valo 	__le32 reserved1;
29027ac9a364SKalle Valo } __packed;
29037ac9a364SKalle Valo 
29047ac9a364SKalle Valo struct stats_div {
29057ac9a364SKalle Valo 	__le32 tx_on_a;
29067ac9a364SKalle Valo 	__le32 tx_on_b;
29077ac9a364SKalle Valo 	__le32 exec_time;
29087ac9a364SKalle Valo 	__le32 probe_time;
29097ac9a364SKalle Valo 	__le32 reserved1;
29107ac9a364SKalle Valo 	__le32 reserved2;
29117ac9a364SKalle Valo } __packed;
29127ac9a364SKalle Valo 
29137ac9a364SKalle Valo struct stats_general_common {
29147ac9a364SKalle Valo 	__le32 temperature;	/* radio temperature */
29157ac9a364SKalle Valo 	struct stats_dbg dbg;
29167ac9a364SKalle Valo 	__le32 sleep_time;
29177ac9a364SKalle Valo 	__le32 slots_out;
29187ac9a364SKalle Valo 	__le32 slots_idle;
29197ac9a364SKalle Valo 	__le32 ttl_timestamp;
29207ac9a364SKalle Valo 	struct stats_div div;
29217ac9a364SKalle Valo 	__le32 rx_enable_counter;
29227ac9a364SKalle Valo 	/*
29237ac9a364SKalle Valo 	 * num_of_sos_states:
29247ac9a364SKalle Valo 	 *  count the number of times we have to re-tune
29257ac9a364SKalle Valo 	 *  in order to get out of bad PHY status
29267ac9a364SKalle Valo 	 */
29277ac9a364SKalle Valo 	__le32 num_of_sos_states;
29287ac9a364SKalle Valo } __packed;
29297ac9a364SKalle Valo 
29307ac9a364SKalle Valo struct stats_general {
29317ac9a364SKalle Valo 	struct stats_general_common common;
29327ac9a364SKalle Valo 	__le32 reserved2;
29337ac9a364SKalle Valo 	__le32 reserved3;
29347ac9a364SKalle Valo } __packed;
29357ac9a364SKalle Valo 
29367ac9a364SKalle Valo #define UCODE_STATS_CLEAR_MSK		(0x1 << 0)
29377ac9a364SKalle Valo #define UCODE_STATS_FREQUENCY_MSK		(0x1 << 1)
29387ac9a364SKalle Valo #define UCODE_STATS_NARROW_BAND_MSK	(0x1 << 2)
29397ac9a364SKalle Valo 
29407ac9a364SKalle Valo /*
29417ac9a364SKalle Valo  * C_STATS = 0x9c,
29427ac9a364SKalle Valo  * all devices identical.
29437ac9a364SKalle Valo  *
29447ac9a364SKalle Valo  * This command triggers an immediate response containing uCode stats.
29457ac9a364SKalle Valo  * The response is in the same format as N_STATS 0x9d, below.
29467ac9a364SKalle Valo  *
29477ac9a364SKalle Valo  * If the CLEAR_STATS configuration flag is set, uCode will clear its
29487ac9a364SKalle Valo  * internal copy of the stats (counters) after issuing the response.
29497ac9a364SKalle Valo  * This flag does not affect N_STATSs after beacons (see below).
29507ac9a364SKalle Valo  *
29517ac9a364SKalle Valo  * If the DISABLE_NOTIF configuration flag is set, uCode will not issue
29527ac9a364SKalle Valo  * N_STATSs after received beacons (see below).  This flag
29537ac9a364SKalle Valo  * does not affect the response to the C_STATS 0x9c itself.
29547ac9a364SKalle Valo  */
29557ac9a364SKalle Valo #define IL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)	/* see above */
29567ac9a364SKalle Valo #define IL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)	/* see above */
29577ac9a364SKalle Valo struct il_stats_cmd {
29587ac9a364SKalle Valo 	__le32 configuration_flags;	/* IL_STATS_CONF_* */
29597ac9a364SKalle Valo } __packed;
29607ac9a364SKalle Valo 
29617ac9a364SKalle Valo /*
29627ac9a364SKalle Valo  * N_STATS = 0x9d (notification only, not a command)
29637ac9a364SKalle Valo  *
29647ac9a364SKalle Valo  * By default, uCode issues this notification after receiving a beacon
29657ac9a364SKalle Valo  * while associated.  To disable this behavior, set DISABLE_NOTIF flag in the
29667ac9a364SKalle Valo  * C_STATS 0x9c, above.
29677ac9a364SKalle Valo  *
29687ac9a364SKalle Valo  * Statistics counters continue to increment beacon after beacon, but are
29697ac9a364SKalle Valo  * cleared when changing channels or when driver issues C_STATS
29707ac9a364SKalle Valo  * 0x9c with CLEAR_STATS bit set (see above).
29717ac9a364SKalle Valo  *
29727ac9a364SKalle Valo  * uCode also issues this notification during scans.  uCode clears stats
29737ac9a364SKalle Valo  * appropriately so that each notification contains stats for only the
29747ac9a364SKalle Valo  * one channel that has just been scanned.
29757ac9a364SKalle Valo  */
29767ac9a364SKalle Valo #define STATS_REPLY_FLG_BAND_24G_MSK         cpu_to_le32(0x2)
29777ac9a364SKalle Valo #define STATS_REPLY_FLG_HT40_MODE_MSK        cpu_to_le32(0x8)
29787ac9a364SKalle Valo 
29797ac9a364SKalle Valo struct il3945_notif_stats {
29807ac9a364SKalle Valo 	__le32 flag;
29817ac9a364SKalle Valo 	struct iwl39_stats_rx rx;
29827ac9a364SKalle Valo 	struct iwl39_stats_tx tx;
29837ac9a364SKalle Valo 	struct iwl39_stats_general general;
29847ac9a364SKalle Valo } __packed;
29857ac9a364SKalle Valo 
29867ac9a364SKalle Valo struct il_notif_stats {
29877ac9a364SKalle Valo 	__le32 flag;
29887ac9a364SKalle Valo 	struct stats_rx rx;
29897ac9a364SKalle Valo 	struct stats_tx tx;
29907ac9a364SKalle Valo 	struct stats_general general;
29917ac9a364SKalle Valo } __packed;
29927ac9a364SKalle Valo 
29937ac9a364SKalle Valo /*
29947ac9a364SKalle Valo  * N_MISSED_BEACONS = 0xa2 (notification only, not a command)
29957ac9a364SKalle Valo  *
29967ac9a364SKalle Valo  * uCode send N_MISSED_BEACONS to driver when detect beacon missed
29977ac9a364SKalle Valo  * in regardless of how many missed beacons, which mean when driver receive the
29987ac9a364SKalle Valo  * notification, inside the command, it can find all the beacons information
29997ac9a364SKalle Valo  * which include number of total missed beacons, number of consecutive missed
30007ac9a364SKalle Valo  * beacons, number of beacons received and number of beacons expected to
30017ac9a364SKalle Valo  * receive.
30027ac9a364SKalle Valo  *
30037ac9a364SKalle Valo  * If uCode detected consecutive_missed_beacons > 5, it will reset the radio
30047ac9a364SKalle Valo  * in order to bring the radio/PHY back to working state; which has no relation
30057ac9a364SKalle Valo  * to when driver will perform sensitivity calibration.
30067ac9a364SKalle Valo  *
30077ac9a364SKalle Valo  * Driver should set it own missed_beacon_threshold to decide when to perform
30087ac9a364SKalle Valo  * sensitivity calibration based on number of consecutive missed beacons in
30097ac9a364SKalle Valo  * order to improve overall performance, especially in noisy environment.
30107ac9a364SKalle Valo  *
30117ac9a364SKalle Valo  */
30127ac9a364SKalle Valo 
30137ac9a364SKalle Valo #define IL_MISSED_BEACON_THRESHOLD_MIN	(1)
30147ac9a364SKalle Valo #define IL_MISSED_BEACON_THRESHOLD_DEF	(5)
30157ac9a364SKalle Valo #define IL_MISSED_BEACON_THRESHOLD_MAX	IL_MISSED_BEACON_THRESHOLD_DEF
30167ac9a364SKalle Valo 
30177ac9a364SKalle Valo struct il_missed_beacon_notif {
30187ac9a364SKalle Valo 	__le32 consecutive_missed_beacons;
30197ac9a364SKalle Valo 	__le32 total_missed_becons;
30207ac9a364SKalle Valo 	__le32 num_expected_beacons;
30217ac9a364SKalle Valo 	__le32 num_recvd_beacons;
30227ac9a364SKalle Valo } __packed;
30237ac9a364SKalle Valo 
30247ac9a364SKalle Valo /******************************************************************************
30257ac9a364SKalle Valo  * (11)
30267ac9a364SKalle Valo  * Rx Calibration Commands:
30277ac9a364SKalle Valo  *
30287ac9a364SKalle Valo  * With the uCode used for open source drivers, most Tx calibration (except
30297ac9a364SKalle Valo  * for Tx Power) and most Rx calibration is done by uCode during the
30307ac9a364SKalle Valo  * "initialize" phase of uCode boot.  Driver must calibrate only:
30317ac9a364SKalle Valo  *
30327ac9a364SKalle Valo  * 1)  Tx power (depends on temperature), described elsewhere
30337ac9a364SKalle Valo  * 2)  Receiver gain balance (optimize MIMO, and detect disconnected antennas)
30347ac9a364SKalle Valo  * 3)  Receiver sensitivity (to optimize signal detection)
30357ac9a364SKalle Valo  *
30367ac9a364SKalle Valo  *****************************************************************************/
30377ac9a364SKalle Valo 
30387ac9a364SKalle Valo /**
30397ac9a364SKalle Valo  * C_SENSITIVITY = 0xa8 (command, has simple generic response)
30407ac9a364SKalle Valo  *
30417ac9a364SKalle Valo  * This command sets up the Rx signal detector for a sensitivity level that
30427ac9a364SKalle Valo  * is high enough to lock onto all signals within the associated network,
30437ac9a364SKalle Valo  * but low enough to ignore signals that are below a certain threshold, so as
30447ac9a364SKalle Valo  * not to have too many "false alarms".  False alarms are signals that the
30457ac9a364SKalle Valo  * Rx DSP tries to lock onto, but then discards after determining that they
30467ac9a364SKalle Valo  * are noise.
30477ac9a364SKalle Valo  *
30487ac9a364SKalle Valo  * The optimum number of false alarms is between 5 and 50 per 200 TUs
30497ac9a364SKalle Valo  * (200 * 1024 uSecs, i.e. 204.8 milliseconds) of actual Rx time (i.e.
30507ac9a364SKalle Valo  * time listening, not transmitting).  Driver must adjust sensitivity so that
30517ac9a364SKalle Valo  * the ratio of actual false alarms to actual Rx time falls within this range.
30527ac9a364SKalle Valo  *
30537ac9a364SKalle Valo  * While associated, uCode delivers N_STATSs after each
30547ac9a364SKalle Valo  * received beacon.  These provide information to the driver to analyze the
30557ac9a364SKalle Valo  * sensitivity.  Don't analyze stats that come in from scanning, or any
30567ac9a364SKalle Valo  * other non-associated-network source.  Pertinent stats include:
30577ac9a364SKalle Valo  *
30587ac9a364SKalle Valo  * From "general" stats (struct stats_rx_non_phy):
30597ac9a364SKalle Valo  *
30607ac9a364SKalle Valo  * (beacon_energy_[abc] & 0x0FF00) >> 8 (unsigned, higher value is lower level)
30617ac9a364SKalle Valo  *   Measure of energy of desired signal.  Used for establishing a level
30627ac9a364SKalle Valo  *   below which the device does not detect signals.
30637ac9a364SKalle Valo  *
30647ac9a364SKalle Valo  * (beacon_silence_rssi_[abc] & 0x0FF00) >> 8 (unsigned, units in dB)
30657ac9a364SKalle Valo  *   Measure of background noise in silent period after beacon.
30667ac9a364SKalle Valo  *
30677ac9a364SKalle Valo  * channel_load
30687ac9a364SKalle Valo  *   uSecs of actual Rx time during beacon period (varies according to
30697ac9a364SKalle Valo  *   how much time was spent transmitting).
30707ac9a364SKalle Valo  *
30717ac9a364SKalle Valo  * From "cck" and "ofdm" stats (struct stats_rx_phy), separately:
30727ac9a364SKalle Valo  *
30737ac9a364SKalle Valo  * false_alarm_cnt
30747ac9a364SKalle Valo  *   Signal locks abandoned early (before phy-level header).
30757ac9a364SKalle Valo  *
30767ac9a364SKalle Valo  * plcp_err
30777ac9a364SKalle Valo  *   Signal locks abandoned late (during phy-level header).
30787ac9a364SKalle Valo  *
30797ac9a364SKalle Valo  * NOTE:  Both false_alarm_cnt and plcp_err increment monotonically from
30807ac9a364SKalle Valo  *        beacon to beacon, i.e. each value is an accumulation of all errors
30817ac9a364SKalle Valo  *        before and including the latest beacon.  Values will wrap around to 0
30827ac9a364SKalle Valo  *        after counting up to 2^32 - 1.  Driver must differentiate vs.
30837ac9a364SKalle Valo  *        previous beacon's values to determine # false alarms in the current
30847ac9a364SKalle Valo  *        beacon period.
30857ac9a364SKalle Valo  *
30867ac9a364SKalle Valo  * Total number of false alarms = false_alarms + plcp_errs
30877ac9a364SKalle Valo  *
30887ac9a364SKalle Valo  * For OFDM, adjust the following table entries in struct il_sensitivity_cmd
30897ac9a364SKalle Valo  * (notice that the start points for OFDM are at or close to settings for
30907ac9a364SKalle Valo  * maximum sensitivity):
30917ac9a364SKalle Valo  *
30927ac9a364SKalle Valo  *                                             START  /  MIN  /  MAX
30937ac9a364SKalle Valo  *   HD_AUTO_CORR32_X1_TH_ADD_MIN_IDX          90   /   85  /  120
30947ac9a364SKalle Valo  *   HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_IDX     170   /  170  /  210
30957ac9a364SKalle Valo  *   HD_AUTO_CORR32_X4_TH_ADD_MIN_IDX         105   /  105  /  140
30967ac9a364SKalle Valo  *   HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_IDX     220   /  220  /  270
30977ac9a364SKalle Valo  *
30987ac9a364SKalle Valo  *   If actual rate of OFDM false alarms (+ plcp_errors) is too high
30997ac9a364SKalle Valo  *   (greater than 50 for each 204.8 msecs listening), reduce sensitivity
31007ac9a364SKalle Valo  *   by *adding* 1 to all 4 of the table entries above, up to the max for
31017ac9a364SKalle Valo  *   each entry.  Conversely, if false alarm rate is too low (less than 5
31027ac9a364SKalle Valo  *   for each 204.8 msecs listening), *subtract* 1 from each entry to
31037ac9a364SKalle Valo  *   increase sensitivity.
31047ac9a364SKalle Valo  *
31057ac9a364SKalle Valo  * For CCK sensitivity, keep track of the following:
31067ac9a364SKalle Valo  *
31077ac9a364SKalle Valo  *   1).  20-beacon history of maximum background noise, indicated by
31087ac9a364SKalle Valo  *        (beacon_silence_rssi_[abc] & 0x0FF00), units in dB, across the
31097ac9a364SKalle Valo  *        3 receivers.  For any given beacon, the "silence reference" is
31107ac9a364SKalle Valo  *        the maximum of last 60 samples (20 beacons * 3 receivers).
31117ac9a364SKalle Valo  *
31127ac9a364SKalle Valo  *   2).  10-beacon history of strongest signal level, as indicated
31137ac9a364SKalle Valo  *        by (beacon_energy_[abc] & 0x0FF00) >> 8, across the 3 receivers,
31147ac9a364SKalle Valo  *        i.e. the strength of the signal through the best receiver at the
31157ac9a364SKalle Valo  *        moment.  These measurements are "upside down", with lower values
31167ac9a364SKalle Valo  *        for stronger signals, so max energy will be *minimum* value.
31177ac9a364SKalle Valo  *
31187ac9a364SKalle Valo  *        Then for any given beacon, the driver must determine the *weakest*
31197ac9a364SKalle Valo  *        of the strongest signals; this is the minimum level that needs to be
31207ac9a364SKalle Valo  *        successfully detected, when using the best receiver at the moment.
31217ac9a364SKalle Valo  *        "Max cck energy" is the maximum (higher value means lower energy!)
31227ac9a364SKalle Valo  *        of the last 10 minima.  Once this is determined, driver must add
31237ac9a364SKalle Valo  *        a little margin by adding "6" to it.
31247ac9a364SKalle Valo  *
31257ac9a364SKalle Valo  *   3).  Number of consecutive beacon periods with too few false alarms.
31267ac9a364SKalle Valo  *        Reset this to 0 at the first beacon period that falls within the
31277ac9a364SKalle Valo  *        "good" range (5 to 50 false alarms per 204.8 milliseconds rx).
31287ac9a364SKalle Valo  *
31297ac9a364SKalle Valo  * Then, adjust the following CCK table entries in struct il_sensitivity_cmd
31307ac9a364SKalle Valo  * (notice that the start points for CCK are at maximum sensitivity):
31317ac9a364SKalle Valo  *
31327ac9a364SKalle Valo  *                                             START  /  MIN  /  MAX
31337ac9a364SKalle Valo  *   HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX         125   /  125  /  200
31347ac9a364SKalle Valo  *   HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX     200   /  200  /  400
31357ac9a364SKalle Valo  *   HD_MIN_ENERGY_CCK_DET_IDX                100   /    0  /  100
31367ac9a364SKalle Valo  *
31377ac9a364SKalle Valo  *   If actual rate of CCK false alarms (+ plcp_errors) is too high
31387ac9a364SKalle Valo  *   (greater than 50 for each 204.8 msecs listening), method for reducing
31397ac9a364SKalle Valo  *   sensitivity is:
31407ac9a364SKalle Valo  *
31417ac9a364SKalle Valo  *   1)  *Add* 3 to value in HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX,
31427ac9a364SKalle Valo  *       up to max 400.
31437ac9a364SKalle Valo  *
31447ac9a364SKalle Valo  *   2)  If current value in HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX is < 160,
31457ac9a364SKalle Valo  *       sensitivity has been reduced a significant amount; bring it up to
31467ac9a364SKalle Valo  *       a moderate 161.  Otherwise, *add* 3, up to max 200.
31477ac9a364SKalle Valo  *
31487ac9a364SKalle Valo  *   3)  a)  If current value in HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX is > 160,
31497ac9a364SKalle Valo  *       sensitivity has been reduced only a moderate or small amount;
31507ac9a364SKalle Valo  *       *subtract* 2 from value in HD_MIN_ENERGY_CCK_DET_IDX,
31517ac9a364SKalle Valo  *       down to min 0.  Otherwise (if gain has been significantly reduced),
31527ac9a364SKalle Valo  *       don't change the HD_MIN_ENERGY_CCK_DET_IDX value.
31537ac9a364SKalle Valo  *
31547ac9a364SKalle Valo  *       b)  Save a snapshot of the "silence reference".
31557ac9a364SKalle Valo  *
31567ac9a364SKalle Valo  *   If actual rate of CCK false alarms (+ plcp_errors) is too low
31577ac9a364SKalle Valo  *   (less than 5 for each 204.8 msecs listening), method for increasing
31587ac9a364SKalle Valo  *   sensitivity is used only if:
31597ac9a364SKalle Valo  *
31607ac9a364SKalle Valo  *   1a)  Previous beacon did not have too many false alarms
31617ac9a364SKalle Valo  *   1b)  AND difference between previous "silence reference" and current
31627ac9a364SKalle Valo  *        "silence reference" (prev - current) is 2 or more,
31637ac9a364SKalle Valo  *   OR 2)  100 or more consecutive beacon periods have had rate of
31647ac9a364SKalle Valo  *          less than 5 false alarms per 204.8 milliseconds rx time.
31657ac9a364SKalle Valo  *
31667ac9a364SKalle Valo  *   Method for increasing sensitivity:
31677ac9a364SKalle Valo  *
31687ac9a364SKalle Valo  *   1)  *Subtract* 3 from value in HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX,
31697ac9a364SKalle Valo  *       down to min 125.
31707ac9a364SKalle Valo  *
31717ac9a364SKalle Valo  *   2)  *Subtract* 3 from value in HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX,
31727ac9a364SKalle Valo  *       down to min 200.
31737ac9a364SKalle Valo  *
31747ac9a364SKalle Valo  *   3)  *Add* 2 to value in HD_MIN_ENERGY_CCK_DET_IDX, up to max 100.
31757ac9a364SKalle Valo  *
31767ac9a364SKalle Valo  *   If actual rate of CCK false alarms (+ plcp_errors) is within good range
31777ac9a364SKalle Valo  *   (between 5 and 50 for each 204.8 msecs listening):
31787ac9a364SKalle Valo  *
31797ac9a364SKalle Valo  *   1)  Save a snapshot of the silence reference.
31807ac9a364SKalle Valo  *
31817ac9a364SKalle Valo  *   2)  If previous beacon had too many CCK false alarms (+ plcp_errors),
31827ac9a364SKalle Valo  *       give some extra margin to energy threshold by *subtracting* 8
31837ac9a364SKalle Valo  *       from value in HD_MIN_ENERGY_CCK_DET_IDX.
31847ac9a364SKalle Valo  *
31857ac9a364SKalle Valo  *   For all cases (too few, too many, good range), make sure that the CCK
31867ac9a364SKalle Valo  *   detection threshold (energy) is below the energy level for robust
31877ac9a364SKalle Valo  *   detection over the past 10 beacon periods, the "Max cck energy".
31887ac9a364SKalle Valo  *   Lower values mean higher energy; this means making sure that the value
31897ac9a364SKalle Valo  *   in HD_MIN_ENERGY_CCK_DET_IDX is at or *above* "Max cck energy".
31907ac9a364SKalle Valo  *
31917ac9a364SKalle Valo  */
31927ac9a364SKalle Valo 
31937ac9a364SKalle Valo /*
31947ac9a364SKalle Valo  * Table entries in C_SENSITIVITY (struct il_sensitivity_cmd)
31957ac9a364SKalle Valo  */
31967ac9a364SKalle Valo #define HD_TBL_SIZE  (11)	/* number of entries */
31977ac9a364SKalle Valo #define HD_MIN_ENERGY_CCK_DET_IDX                 (0)	/* table idxes */
31987ac9a364SKalle Valo #define HD_MIN_ENERGY_OFDM_DET_IDX                (1)
31997ac9a364SKalle Valo #define HD_AUTO_CORR32_X1_TH_ADD_MIN_IDX          (2)
32007ac9a364SKalle Valo #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_IDX      (3)
32017ac9a364SKalle Valo #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX      (4)
32027ac9a364SKalle Valo #define HD_AUTO_CORR32_X4_TH_ADD_MIN_IDX          (5)
32037ac9a364SKalle Valo #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_IDX      (6)
32047ac9a364SKalle Valo #define HD_BARKER_CORR_TH_ADD_MIN_IDX             (7)
32057ac9a364SKalle Valo #define HD_BARKER_CORR_TH_ADD_MIN_MRC_IDX         (8)
32067ac9a364SKalle Valo #define HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX          (9)
32077ac9a364SKalle Valo #define HD_OFDM_ENERGY_TH_IN_IDX                  (10)
32087ac9a364SKalle Valo 
32097ac9a364SKalle Valo /* Control field in struct il_sensitivity_cmd */
32107ac9a364SKalle Valo #define C_SENSITIVITY_CONTROL_DEFAULT_TBL	cpu_to_le16(0)
32117ac9a364SKalle Valo #define C_SENSITIVITY_CONTROL_WORK_TBL	cpu_to_le16(1)
32127ac9a364SKalle Valo 
32137ac9a364SKalle Valo /**
32147ac9a364SKalle Valo  * struct il_sensitivity_cmd
32157ac9a364SKalle Valo  * @control:  (1) updates working table, (0) updates default table
32167ac9a364SKalle Valo  * @table:  energy threshold values, use HD_* as idx into table
32177ac9a364SKalle Valo  *
32187ac9a364SKalle Valo  * Always use "1" in "control" to update uCode's working table and DSP.
32197ac9a364SKalle Valo  */
32207ac9a364SKalle Valo struct il_sensitivity_cmd {
32217ac9a364SKalle Valo 	__le16 control;		/* always use "1" */
32227ac9a364SKalle Valo 	__le16 table[HD_TBL_SIZE];	/* use HD_* as idx */
32237ac9a364SKalle Valo } __packed;
32247ac9a364SKalle Valo 
32257ac9a364SKalle Valo /**
32267ac9a364SKalle Valo  * C_PHY_CALIBRATION = 0xb0 (command, has simple generic response)
32277ac9a364SKalle Valo  *
32287ac9a364SKalle Valo  * This command sets the relative gains of 4965 device's 3 radio receiver chains.
32297ac9a364SKalle Valo  *
32307ac9a364SKalle Valo  * After the first association, driver should accumulate signal and noise
32317ac9a364SKalle Valo  * stats from the N_STATSs that follow the first 20
32327ac9a364SKalle Valo  * beacons from the associated network (don't collect stats that come
32337ac9a364SKalle Valo  * in from scanning, or any other non-network source).
32347ac9a364SKalle Valo  *
32357ac9a364SKalle Valo  * DISCONNECTED ANTENNA:
32367ac9a364SKalle Valo  *
32377ac9a364SKalle Valo  * Driver should determine which antennas are actually connected, by comparing
32387ac9a364SKalle Valo  * average beacon signal levels for the 3 Rx chains.  Accumulate (add) the
32397ac9a364SKalle Valo  * following values over 20 beacons, one accumulator for each of the chains
32407ac9a364SKalle Valo  * a/b/c, from struct stats_rx_non_phy:
32417ac9a364SKalle Valo  *
32427ac9a364SKalle Valo  * beacon_rssi_[abc] & 0x0FF (unsigned, units in dB)
32437ac9a364SKalle Valo  *
32447ac9a364SKalle Valo  * Find the strongest signal from among a/b/c.  Compare the other two to the
32457ac9a364SKalle Valo  * strongest.  If any signal is more than 15 dB (times 20, unless you
32467ac9a364SKalle Valo  * divide the accumulated values by 20) below the strongest, the driver
32477ac9a364SKalle Valo  * considers that antenna to be disconnected, and should not try to use that
32487ac9a364SKalle Valo  * antenna/chain for Rx or Tx.  If both A and B seem to be disconnected,
32497ac9a364SKalle Valo  * driver should declare the stronger one as connected, and attempt to use it
32507ac9a364SKalle Valo  * (A and B are the only 2 Tx chains!).
32517ac9a364SKalle Valo  *
32527ac9a364SKalle Valo  *
32537ac9a364SKalle Valo  * RX BALANCE:
32547ac9a364SKalle Valo  *
32557ac9a364SKalle Valo  * Driver should balance the 3 receivers (but just the ones that are connected
32567ac9a364SKalle Valo  * to antennas, see above) for gain, by comparing the average signal levels
32577ac9a364SKalle Valo  * detected during the silence after each beacon (background noise).
32587ac9a364SKalle Valo  * Accumulate (add) the following values over 20 beacons, one accumulator for
32597ac9a364SKalle Valo  * each of the chains a/b/c, from struct stats_rx_non_phy:
32607ac9a364SKalle Valo  *
32617ac9a364SKalle Valo  * beacon_silence_rssi_[abc] & 0x0FF (unsigned, units in dB)
32627ac9a364SKalle Valo  *
32637ac9a364SKalle Valo  * Find the weakest background noise level from among a/b/c.  This Rx chain
32647ac9a364SKalle Valo  * will be the reference, with 0 gain adjustment.  Attenuate other channels by
32657ac9a364SKalle Valo  * finding noise difference:
32667ac9a364SKalle Valo  *
32677ac9a364SKalle Valo  * (accum_noise[i] - accum_noise[reference]) / 30
32687ac9a364SKalle Valo  *
32697ac9a364SKalle Valo  * The "30" adjusts the dB in the 20 accumulated samples to units of 1.5 dB.
32707ac9a364SKalle Valo  * For use in diff_gain_[abc] fields of struct il_calibration_cmd, the
32717ac9a364SKalle Valo  * driver should limit the difference results to a range of 0-3 (0-4.5 dB),
32727ac9a364SKalle Valo  * and set bit 2 to indicate "reduce gain".  The value for the reference
32737ac9a364SKalle Valo  * (weakest) chain should be "0".
32747ac9a364SKalle Valo  *
32757ac9a364SKalle Valo  * diff_gain_[abc] bit fields:
32767ac9a364SKalle Valo  *   2: (1) reduce gain, (0) increase gain
32777ac9a364SKalle Valo  * 1-0: amount of gain, units of 1.5 dB
32787ac9a364SKalle Valo  */
32797ac9a364SKalle Valo 
32807ac9a364SKalle Valo /* Phy calibration command for series */
32817ac9a364SKalle Valo /* The default calibrate table size if not specified by firmware */
32827ac9a364SKalle Valo #define IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE	18
32837ac9a364SKalle Valo enum {
32847ac9a364SKalle Valo 	IL_PHY_CALIBRATE_DIFF_GAIN_CMD = 7,
32857ac9a364SKalle Valo 	IL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE = 19,
32867ac9a364SKalle Valo };
32877ac9a364SKalle Valo 
32887ac9a364SKalle Valo #define IL_MAX_PHY_CALIBRATE_TBL_SIZE		(253)
32897ac9a364SKalle Valo 
32907ac9a364SKalle Valo struct il_calib_hdr {
32917ac9a364SKalle Valo 	u8 op_code;
32927ac9a364SKalle Valo 	u8 first_group;
32937ac9a364SKalle Valo 	u8 groups_num;
32947ac9a364SKalle Valo 	u8 data_valid;
32957ac9a364SKalle Valo } __packed;
32967ac9a364SKalle Valo 
32977ac9a364SKalle Valo /* IL_PHY_CALIBRATE_DIFF_GAIN_CMD (7) */
32987ac9a364SKalle Valo struct il_calib_diff_gain_cmd {
32997ac9a364SKalle Valo 	struct il_calib_hdr hdr;
33007ac9a364SKalle Valo 	s8 diff_gain_a;		/* see above */
33017ac9a364SKalle Valo 	s8 diff_gain_b;
33027ac9a364SKalle Valo 	s8 diff_gain_c;
33037ac9a364SKalle Valo 	u8 reserved1;
33047ac9a364SKalle Valo } __packed;
33057ac9a364SKalle Valo 
33067ac9a364SKalle Valo /******************************************************************************
33077ac9a364SKalle Valo  * (12)
33087ac9a364SKalle Valo  * Miscellaneous Commands:
33097ac9a364SKalle Valo  *
33107ac9a364SKalle Valo  *****************************************************************************/
33117ac9a364SKalle Valo 
33127ac9a364SKalle Valo /*
33137ac9a364SKalle Valo  * LEDs Command & Response
33147ac9a364SKalle Valo  * C_LEDS = 0x48 (command, has simple generic response)
33157ac9a364SKalle Valo  *
33167ac9a364SKalle Valo  * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field),
33177ac9a364SKalle Valo  * this command turns it on or off, or sets up a periodic blinking cycle.
33187ac9a364SKalle Valo  */
33197ac9a364SKalle Valo struct il_led_cmd {
33207ac9a364SKalle Valo 	__le32 interval;	/* "interval" in uSec */
33217ac9a364SKalle Valo 	u8 id;			/* 1: Activity, 2: Link, 3: Tech */
33227ac9a364SKalle Valo 	u8 off;			/* # intervals off while blinking;
33237ac9a364SKalle Valo 				 * "0", with >0 "on" value, turns LED on */
33247ac9a364SKalle Valo 	u8 on;			/* # intervals on while blinking;
33257ac9a364SKalle Valo 				 * "0", regardless of "off", turns LED off */
33267ac9a364SKalle Valo 	u8 reserved;
33277ac9a364SKalle Valo } __packed;
33287ac9a364SKalle Valo 
33297ac9a364SKalle Valo /******************************************************************************
33307ac9a364SKalle Valo  * (13)
33317ac9a364SKalle Valo  * Union of all expected notifications/responses:
33327ac9a364SKalle Valo  *
33337ac9a364SKalle Valo  *****************************************************************************/
33347ac9a364SKalle Valo 
33357ac9a364SKalle Valo #define IL_RX_FRAME_SIZE_MSK	0x00003fff
33367ac9a364SKalle Valo 
33377ac9a364SKalle Valo struct il_rx_pkt {
33387ac9a364SKalle Valo 	/*
33397ac9a364SKalle Valo 	 * The first 4 bytes of the RX frame header contain both the RX frame
33407ac9a364SKalle Valo 	 * size and some flags.
33417ac9a364SKalle Valo 	 * Bit fields:
33427ac9a364SKalle Valo 	 * 31:    flag flush RB request
33437ac9a364SKalle Valo 	 * 30:    flag ignore TC (terminal counter) request
33447ac9a364SKalle Valo 	 * 29:    flag fast IRQ request
33457ac9a364SKalle Valo 	 * 28-14: Reserved
33467ac9a364SKalle Valo 	 * 13-00: RX frame size
33477ac9a364SKalle Valo 	 */
33487ac9a364SKalle Valo 	__le32 len_n_flags;
33497ac9a364SKalle Valo 	struct il_cmd_header hdr;
33507ac9a364SKalle Valo 	union {
33517ac9a364SKalle Valo 		struct il3945_rx_frame rx_frame;
33527ac9a364SKalle Valo 		struct il3945_tx_resp tx_resp;
33537ac9a364SKalle Valo 		struct il3945_beacon_notif beacon_status;
33547ac9a364SKalle Valo 
33557ac9a364SKalle Valo 		struct il_alive_resp alive_frame;
33567ac9a364SKalle Valo 		struct il_spectrum_notification spectrum_notif;
33577ac9a364SKalle Valo 		struct il_csa_notification csa_notif;
33587ac9a364SKalle Valo 		struct il_error_resp err_resp;
33597ac9a364SKalle Valo 		struct il_card_state_notif card_state_notif;
33607ac9a364SKalle Valo 		struct il_add_sta_resp add_sta;
33617ac9a364SKalle Valo 		struct il_rem_sta_resp rem_sta;
33627ac9a364SKalle Valo 		struct il_sleep_notification sleep_notif;
33637ac9a364SKalle Valo 		struct il_spectrum_resp spectrum;
33647ac9a364SKalle Valo 		struct il_notif_stats stats;
33657ac9a364SKalle Valo 		struct il_compressed_ba_resp compressed_ba;
33667ac9a364SKalle Valo 		struct il_missed_beacon_notif missed_beacon;
33677ac9a364SKalle Valo 		__le32 status;
3368*56df3d40SGustavo A. R. Silva 		DECLARE_FLEX_ARRAY(u8, raw);
33697ac9a364SKalle Valo 	} u;
33707ac9a364SKalle Valo } __packed;
33717ac9a364SKalle Valo 
33727ac9a364SKalle Valo #endif /* __il_commands_h__ */
3373