1aa5f59dfSChristophe Leroy /* SPDX-License-Identifier: GPL-2.0 */ 2aa5f59dfSChristophe Leroy #ifndef _ASM_POWERPC_MMU_BOOK3E_H_ 3aa5f59dfSChristophe Leroy #define _ASM_POWERPC_MMU_BOOK3E_H_ 4aa5f59dfSChristophe Leroy /* 5aa5f59dfSChristophe Leroy * Freescale Book-E/Book-3e (ISA 2.06+) MMU support 6aa5f59dfSChristophe Leroy */ 7aa5f59dfSChristophe Leroy 8aa5f59dfSChristophe Leroy /* Book-3e defined page sizes */ 9aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_1K 0 10aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_2K 1 11aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_4K 2 12aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_8K 3 13aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_16K 4 14aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_32K 5 15aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_64K 6 16aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_128K 7 17aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_256K 8 18aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_512K 9 19aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_1M 10 20aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_2M 11 21aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_4M 12 22aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_8M 13 23aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_16M 14 24aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_32M 15 25aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_64M 16 26aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_128M 17 27aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_256M 18 28aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_512M 19 29aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_1GB 20 30aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_2GB 21 31aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_4GB 22 32aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_8GB 23 33aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_16GB 24 34aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_32GB 25 35aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_64GB 26 36aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_128GB 27 37aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_256GB 28 38aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_512GB 29 39aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_1TB 30 40aa5f59dfSChristophe Leroy #define BOOK3E_PAGESZ_2TB 31 41aa5f59dfSChristophe Leroy 42aa5f59dfSChristophe Leroy /* MAS registers bit definitions */ 43aa5f59dfSChristophe Leroy 44aa5f59dfSChristophe Leroy #define MAS0_TLBSEL_MASK 0x30000000 45aa5f59dfSChristophe Leroy #define MAS0_TLBSEL_SHIFT 28 46aa5f59dfSChristophe Leroy #define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK) 47aa5f59dfSChristophe Leroy #define MAS0_GET_TLBSEL(mas0) (((mas0) & MAS0_TLBSEL_MASK) >> \ 48aa5f59dfSChristophe Leroy MAS0_TLBSEL_SHIFT) 49aa5f59dfSChristophe Leroy #define MAS0_ESEL_MASK 0x0FFF0000 50aa5f59dfSChristophe Leroy #define MAS0_ESEL_SHIFT 16 51aa5f59dfSChristophe Leroy #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) 52aa5f59dfSChristophe Leroy #define MAS0_NV(x) ((x) & 0x00000FFF) 53aa5f59dfSChristophe Leroy #define MAS0_HES 0x00004000 54aa5f59dfSChristophe Leroy #define MAS0_WQ_ALLWAYS 0x00000000 55aa5f59dfSChristophe Leroy #define MAS0_WQ_COND 0x00001000 56aa5f59dfSChristophe Leroy #define MAS0_WQ_CLR_RSRV 0x00002000 57aa5f59dfSChristophe Leroy 58aa5f59dfSChristophe Leroy #define MAS1_VALID 0x80000000 59aa5f59dfSChristophe Leroy #define MAS1_IPROT 0x40000000 60aa5f59dfSChristophe Leroy #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) 61aa5f59dfSChristophe Leroy #define MAS1_IND 0x00002000 62aa5f59dfSChristophe Leroy #define MAS1_TS 0x00001000 63aa5f59dfSChristophe Leroy #define MAS1_TSIZE_MASK 0x00000f80 64aa5f59dfSChristophe Leroy #define MAS1_TSIZE_SHIFT 7 65aa5f59dfSChristophe Leroy #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) 66aa5f59dfSChristophe Leroy #define MAS1_GET_TSIZE(mas1) (((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT) 67aa5f59dfSChristophe Leroy 68aa5f59dfSChristophe Leroy #define MAS2_EPN (~0xFFFUL) 69aa5f59dfSChristophe Leroy #define MAS2_X0 0x00000040 70aa5f59dfSChristophe Leroy #define MAS2_X1 0x00000020 71aa5f59dfSChristophe Leroy #define MAS2_W 0x00000010 72aa5f59dfSChristophe Leroy #define MAS2_I 0x00000008 73aa5f59dfSChristophe Leroy #define MAS2_M 0x00000004 74aa5f59dfSChristophe Leroy #define MAS2_G 0x00000002 75aa5f59dfSChristophe Leroy #define MAS2_E 0x00000001 76aa5f59dfSChristophe Leroy #define MAS2_WIMGE_MASK 0x0000001f 77aa5f59dfSChristophe Leroy #define MAS2_EPN_MASK(size) (~0 << (size + 10)) 78aa5f59dfSChristophe Leroy 79aa5f59dfSChristophe Leroy #define MAS3_RPN 0xFFFFF000 80aa5f59dfSChristophe Leroy #define MAS3_U0 0x00000200 81aa5f59dfSChristophe Leroy #define MAS3_U1 0x00000100 82aa5f59dfSChristophe Leroy #define MAS3_U2 0x00000080 83aa5f59dfSChristophe Leroy #define MAS3_U3 0x00000040 84aa5f59dfSChristophe Leroy #define MAS3_UX 0x00000020 85aa5f59dfSChristophe Leroy #define MAS3_SX 0x00000010 86aa5f59dfSChristophe Leroy #define MAS3_UW 0x00000008 87aa5f59dfSChristophe Leroy #define MAS3_SW 0x00000004 88aa5f59dfSChristophe Leroy #define MAS3_UR 0x00000002 89aa5f59dfSChristophe Leroy #define MAS3_SR 0x00000001 90aa5f59dfSChristophe Leroy #define MAS3_BAP_MASK 0x0000003f 91aa5f59dfSChristophe Leroy #define MAS3_SPSIZE 0x0000003e 92aa5f59dfSChristophe Leroy #define MAS3_SPSIZE_SHIFT 1 93aa5f59dfSChristophe Leroy 94aa5f59dfSChristophe Leroy #define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK 95aa5f59dfSChristophe Leroy #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) 96aa5f59dfSChristophe Leroy #define MAS4_INDD 0x00008000 /* Default IND */ 97aa5f59dfSChristophe Leroy #define MAS4_TSIZED(x) MAS1_TSIZE(x) 98aa5f59dfSChristophe Leroy #define MAS4_X0D 0x00000040 99aa5f59dfSChristophe Leroy #define MAS4_X1D 0x00000020 100aa5f59dfSChristophe Leroy #define MAS4_WD 0x00000010 101aa5f59dfSChristophe Leroy #define MAS4_ID 0x00000008 102aa5f59dfSChristophe Leroy #define MAS4_MD 0x00000004 103aa5f59dfSChristophe Leroy #define MAS4_GD 0x00000002 104aa5f59dfSChristophe Leroy #define MAS4_ED 0x00000001 105aa5f59dfSChristophe Leroy #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ 106aa5f59dfSChristophe Leroy #define MAS4_WIMGED_SHIFT 0 107aa5f59dfSChristophe Leroy #define MAS4_VLED MAS4_X1D /* Default VLE */ 108aa5f59dfSChristophe Leroy #define MAS4_ACMD 0x000000c0 /* Default ACM */ 109aa5f59dfSChristophe Leroy #define MAS4_ACMD_SHIFT 6 110aa5f59dfSChristophe Leroy #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */ 111aa5f59dfSChristophe Leroy #define MAS4_TSIZED_SHIFT 7 112aa5f59dfSChristophe Leroy 113aa5f59dfSChristophe Leroy #define MAS5_SGS 0x80000000 114aa5f59dfSChristophe Leroy 115aa5f59dfSChristophe Leroy #define MAS6_SPID0 0x3FFF0000 116aa5f59dfSChristophe Leroy #define MAS6_SPID1 0x00007FFE 117aa5f59dfSChristophe Leroy #define MAS6_ISIZE(x) MAS1_TSIZE(x) 118aa5f59dfSChristophe Leroy #define MAS6_SAS 0x00000001 119aa5f59dfSChristophe Leroy #define MAS6_SPID MAS6_SPID0 120aa5f59dfSChristophe Leroy #define MAS6_SIND 0x00000002 /* Indirect page */ 121aa5f59dfSChristophe Leroy #define MAS6_SIND_SHIFT 1 122aa5f59dfSChristophe Leroy #define MAS6_SPID_MASK 0x3fff0000 123aa5f59dfSChristophe Leroy #define MAS6_SPID_SHIFT 16 124aa5f59dfSChristophe Leroy #define MAS6_ISIZE_MASK 0x00000f80 125aa5f59dfSChristophe Leroy #define MAS6_ISIZE_SHIFT 7 126aa5f59dfSChristophe Leroy 127aa5f59dfSChristophe Leroy #define MAS7_RPN 0xFFFFFFFF 128aa5f59dfSChristophe Leroy 129aa5f59dfSChristophe Leroy #define MAS8_TGS 0x80000000 /* Guest space */ 130aa5f59dfSChristophe Leroy #define MAS8_VF 0x40000000 /* Virtualization Fault */ 131aa5f59dfSChristophe Leroy #define MAS8_TLPID 0x000000ff 132aa5f59dfSChristophe Leroy 133aa5f59dfSChristophe Leroy /* Bit definitions for MMUCFG */ 134aa5f59dfSChristophe Leroy #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 135aa5f59dfSChristophe Leroy #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ 136aa5f59dfSChristophe Leroy #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ 137aa5f59dfSChristophe Leroy #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ 138aa5f59dfSChristophe Leroy #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ 139aa5f59dfSChristophe Leroy #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ 140aa5f59dfSChristophe Leroy #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ 141aa5f59dfSChristophe Leroy #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ 142aa5f59dfSChristophe Leroy #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ 143aa5f59dfSChristophe Leroy 144aa5f59dfSChristophe Leroy /* Bit definitions for MMUCSR0 */ 145aa5f59dfSChristophe Leroy #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 146aa5f59dfSChristophe Leroy #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 147aa5f59dfSChristophe Leroy #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 148aa5f59dfSChristophe Leroy #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ 149aa5f59dfSChristophe Leroy #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ 150aa5f59dfSChristophe Leroy MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) 151aa5f59dfSChristophe Leroy #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ 152aa5f59dfSChristophe Leroy #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ 153aa5f59dfSChristophe Leroy #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 154aa5f59dfSChristophe Leroy #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 155aa5f59dfSChristophe Leroy 156aa5f59dfSChristophe Leroy /* MMUCFG bits */ 157aa5f59dfSChristophe Leroy #define MMUCFG_MAVN_NASK 0x00000003 158aa5f59dfSChristophe Leroy #define MMUCFG_MAVN_V1_0 0x00000000 159aa5f59dfSChristophe Leroy #define MMUCFG_MAVN_V2_0 0x00000001 160aa5f59dfSChristophe Leroy #define MMUCFG_NTLB_MASK 0x0000000c 161aa5f59dfSChristophe Leroy #define MMUCFG_NTLB_SHIFT 2 162aa5f59dfSChristophe Leroy #define MMUCFG_PIDSIZE_MASK 0x000007c0 163aa5f59dfSChristophe Leroy #define MMUCFG_PIDSIZE_SHIFT 6 164aa5f59dfSChristophe Leroy #define MMUCFG_TWC 0x00008000 165aa5f59dfSChristophe Leroy #define MMUCFG_LRAT 0x00010000 166aa5f59dfSChristophe Leroy #define MMUCFG_RASIZE_MASK 0x00fe0000 167aa5f59dfSChristophe Leroy #define MMUCFG_RASIZE_SHIFT 17 168aa5f59dfSChristophe Leroy #define MMUCFG_LPIDSIZE_MASK 0x0f000000 169aa5f59dfSChristophe Leroy #define MMUCFG_LPIDSIZE_SHIFT 24 170aa5f59dfSChristophe Leroy 171aa5f59dfSChristophe Leroy /* TLBnCFG encoding */ 172aa5f59dfSChristophe Leroy #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 173aa5f59dfSChristophe Leroy #define TLBnCFG_HES 0x00002000 /* HW select supported */ 174aa5f59dfSChristophe Leroy #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ 175aa5f59dfSChristophe Leroy #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 176aa5f59dfSChristophe Leroy #define TLBnCFG_IND 0x00020000 /* IND entries supported */ 177aa5f59dfSChristophe Leroy #define TLBnCFG_PT 0x00040000 /* Can load from page table */ 178aa5f59dfSChristophe Leroy #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ 179aa5f59dfSChristophe Leroy #define TLBnCFG_MINSIZE_SHIFT 20 180aa5f59dfSChristophe Leroy #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ 181aa5f59dfSChristophe Leroy #define TLBnCFG_MAXSIZE_SHIFT 16 182aa5f59dfSChristophe Leroy #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 183aa5f59dfSChristophe Leroy #define TLBnCFG_ASSOC_SHIFT 24 184aa5f59dfSChristophe Leroy 185aa5f59dfSChristophe Leroy /* TLBnPS encoding */ 186aa5f59dfSChristophe Leroy #define TLBnPS_4K 0x00000004 187aa5f59dfSChristophe Leroy #define TLBnPS_8K 0x00000008 188aa5f59dfSChristophe Leroy #define TLBnPS_16K 0x00000010 189aa5f59dfSChristophe Leroy #define TLBnPS_32K 0x00000020 190aa5f59dfSChristophe Leroy #define TLBnPS_64K 0x00000040 191aa5f59dfSChristophe Leroy #define TLBnPS_128K 0x00000080 192aa5f59dfSChristophe Leroy #define TLBnPS_256K 0x00000100 193aa5f59dfSChristophe Leroy #define TLBnPS_512K 0x00000200 194aa5f59dfSChristophe Leroy #define TLBnPS_1M 0x00000400 195aa5f59dfSChristophe Leroy #define TLBnPS_2M 0x00000800 196aa5f59dfSChristophe Leroy #define TLBnPS_4M 0x00001000 197aa5f59dfSChristophe Leroy #define TLBnPS_8M 0x00002000 198aa5f59dfSChristophe Leroy #define TLBnPS_16M 0x00004000 199aa5f59dfSChristophe Leroy #define TLBnPS_32M 0x00008000 200aa5f59dfSChristophe Leroy #define TLBnPS_64M 0x00010000 201aa5f59dfSChristophe Leroy #define TLBnPS_128M 0x00020000 202aa5f59dfSChristophe Leroy #define TLBnPS_256M 0x00040000 203aa5f59dfSChristophe Leroy #define TLBnPS_512M 0x00080000 204aa5f59dfSChristophe Leroy #define TLBnPS_1G 0x00100000 205aa5f59dfSChristophe Leroy #define TLBnPS_2G 0x00200000 206aa5f59dfSChristophe Leroy #define TLBnPS_4G 0x00400000 207aa5f59dfSChristophe Leroy #define TLBnPS_8G 0x00800000 208aa5f59dfSChristophe Leroy #define TLBnPS_16G 0x01000000 209aa5f59dfSChristophe Leroy #define TLBnPS_32G 0x02000000 210aa5f59dfSChristophe Leroy #define TLBnPS_64G 0x04000000 211aa5f59dfSChristophe Leroy #define TLBnPS_128G 0x08000000 212aa5f59dfSChristophe Leroy #define TLBnPS_256G 0x10000000 213aa5f59dfSChristophe Leroy 214aa5f59dfSChristophe Leroy /* tlbilx action encoding */ 215aa5f59dfSChristophe Leroy #define TLBILX_T_ALL 0 216aa5f59dfSChristophe Leroy #define TLBILX_T_TID 1 217aa5f59dfSChristophe Leroy #define TLBILX_T_FULLMATCH 3 218aa5f59dfSChristophe Leroy #define TLBILX_T_CLASS0 4 219aa5f59dfSChristophe Leroy #define TLBILX_T_CLASS1 5 220aa5f59dfSChristophe Leroy #define TLBILX_T_CLASS2 6 221aa5f59dfSChristophe Leroy #define TLBILX_T_CLASS3 7 222aa5f59dfSChristophe Leroy 223aa5f59dfSChristophe Leroy /* 224aa5f59dfSChristophe Leroy * The mapping only needs to be cache-coherent on SMP, except on 225aa5f59dfSChristophe Leroy * Freescale e500mc derivatives where it's also needed for coherent DMA. 226aa5f59dfSChristophe Leroy */ 227aa5f59dfSChristophe Leroy #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 228aa5f59dfSChristophe Leroy #define MAS2_M_IF_NEEDED MAS2_M 229aa5f59dfSChristophe Leroy #else 230aa5f59dfSChristophe Leroy #define MAS2_M_IF_NEEDED 0 231aa5f59dfSChristophe Leroy #endif 232aa5f59dfSChristophe Leroy 233aa5f59dfSChristophe Leroy #ifndef __ASSEMBLY__ 234aa5f59dfSChristophe Leroy #include <asm/bug.h> 235aa5f59dfSChristophe Leroy 236aa5f59dfSChristophe Leroy extern unsigned int tlbcam_index; 237aa5f59dfSChristophe Leroy 238aa5f59dfSChristophe Leroy typedef struct { 239aa5f59dfSChristophe Leroy unsigned int id; 240aa5f59dfSChristophe Leroy unsigned int active; 241aa5f59dfSChristophe Leroy void __user *vdso; 242aa5f59dfSChristophe Leroy } mm_context_t; 243aa5f59dfSChristophe Leroy 244aa5f59dfSChristophe Leroy /* Page size definitions, common between 32 and 64-bit 245aa5f59dfSChristophe Leroy * 246aa5f59dfSChristophe Leroy * shift : is the "PAGE_SHIFT" value for that page size 247aa5f59dfSChristophe Leroy * penc : is the pte encoding mask 248aa5f59dfSChristophe Leroy * 249aa5f59dfSChristophe Leroy */ 250aa5f59dfSChristophe Leroy struct mmu_psize_def 251aa5f59dfSChristophe Leroy { 252aa5f59dfSChristophe Leroy unsigned int shift; /* number of bits */ 253aa5f59dfSChristophe Leroy unsigned int enc; /* PTE encoding */ 254aa5f59dfSChristophe Leroy unsigned int ind; /* Corresponding indirect page size shift */ 255aa5f59dfSChristophe Leroy unsigned int flags; 256aa5f59dfSChristophe Leroy #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ 257aa5f59dfSChristophe Leroy #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ 258aa5f59dfSChristophe Leroy }; 259aa5f59dfSChristophe Leroy extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 260aa5f59dfSChristophe Leroy shift_to_mmu_psize(unsigned int shift)261aa5f59dfSChristophe Leroystatic inline int shift_to_mmu_psize(unsigned int shift) 262aa5f59dfSChristophe Leroy { 263aa5f59dfSChristophe Leroy int psize; 264aa5f59dfSChristophe Leroy 265aa5f59dfSChristophe Leroy for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) 266aa5f59dfSChristophe Leroy if (mmu_psize_defs[psize].shift == shift) 267aa5f59dfSChristophe Leroy return psize; 268aa5f59dfSChristophe Leroy return -1; 269aa5f59dfSChristophe Leroy } 270aa5f59dfSChristophe Leroy mmu_psize_to_shift(unsigned int mmu_psize)271aa5f59dfSChristophe Leroystatic inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) 272aa5f59dfSChristophe Leroy { 273aa5f59dfSChristophe Leroy if (mmu_psize_defs[mmu_psize].shift) 274aa5f59dfSChristophe Leroy return mmu_psize_defs[mmu_psize].shift; 275aa5f59dfSChristophe Leroy BUG(); 276aa5f59dfSChristophe Leroy } 277aa5f59dfSChristophe Leroy 278aa5f59dfSChristophe Leroy /* The page sizes use the same names as 64-bit hash but are 279aa5f59dfSChristophe Leroy * constants 280aa5f59dfSChristophe Leroy */ 281aa5f59dfSChristophe Leroy #if defined(CONFIG_PPC_4K_PAGES) 282aa5f59dfSChristophe Leroy #define mmu_virtual_psize MMU_PAGE_4K 283aa5f59dfSChristophe Leroy #else 284aa5f59dfSChristophe Leroy #error Unsupported page size 285aa5f59dfSChristophe Leroy #endif 286aa5f59dfSChristophe Leroy 287aa5f59dfSChristophe Leroy extern int mmu_linear_psize; 288aa5f59dfSChristophe Leroy extern int mmu_vmemmap_psize; 289aa5f59dfSChristophe Leroy 290aa5f59dfSChristophe Leroy struct tlb_core_data { 291aa5f59dfSChristophe Leroy /* 292aa5f59dfSChristophe Leroy * Per-core spinlock for e6500 TLB handlers (no tlbsrx.) 293aa5f59dfSChristophe Leroy * Must be the first struct element. 294aa5f59dfSChristophe Leroy */ 295aa5f59dfSChristophe Leroy u8 lock; 296aa5f59dfSChristophe Leroy 297aa5f59dfSChristophe Leroy /* For software way selection, as on Freescale TLB1 */ 298aa5f59dfSChristophe Leroy u8 esel_next, esel_max, esel_first; 299aa5f59dfSChristophe Leroy }; 300aa5f59dfSChristophe Leroy 301aa5f59dfSChristophe Leroy #ifdef CONFIG_PPC64 302aa5f59dfSChristophe Leroy extern unsigned long linear_map_top; 303aa5f59dfSChristophe Leroy extern int book3e_htw_mode; 304aa5f59dfSChristophe Leroy 305aa5f59dfSChristophe Leroy #define PPC_HTW_NONE 0 306aa5f59dfSChristophe Leroy #define PPC_HTW_IBM 1 307aa5f59dfSChristophe Leroy #define PPC_HTW_E6500 2 308aa5f59dfSChristophe Leroy 309aa5f59dfSChristophe Leroy /* 310aa5f59dfSChristophe Leroy * 64-bit booke platforms don't load the tlb in the tlb miss handler code. 311aa5f59dfSChristophe Leroy * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to 312aa5f59dfSChristophe Leroy * return 1, indicating that the tlb requires preloading. 313aa5f59dfSChristophe Leroy */ 314aa5f59dfSChristophe Leroy #define HUGETLB_NEED_PRELOAD 315aa5f59dfSChristophe Leroy 316aa5f59dfSChristophe Leroy #define mmu_cleanup_all NULL 317aa5f59dfSChristophe Leroy 318aa5f59dfSChristophe Leroy #define MAX_PHYSMEM_BITS 44 319aa5f59dfSChristophe Leroy 320aa5f59dfSChristophe Leroy #endif 321aa5f59dfSChristophe Leroy 322*0e2a34c4SChristophe Leroy #include <asm/percpu.h> 323*0e2a34c4SChristophe Leroy DECLARE_PER_CPU(int, next_tlbcam_idx); 324*0e2a34c4SChristophe Leroy 325aa5f59dfSChristophe Leroy #endif /* !__ASSEMBLY__ */ 326aa5f59dfSChristophe Leroy 327aa5f59dfSChristophe Leroy #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ 328