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/openbmc/linux/drivers/gpu/drm/rockchip/
H A Ddw_hdmi-rockchip.c23 #define RK3228_GRF_SOC_CON2 0x0408
26 #define RK3228_GRF_SOC_CON6 0x0418
31 #define RK3288_GRF_SOC_CON6 0x025C
33 #define RK3328_GRF_SOC_CON2 0x0408
38 #define RK3328_GRF_SOC_CON3 0x040c
44 #define RK3328_GRF_SOC_CON4 0x0410
51 #define RK3399_GRF_SOC_CON20 0x6250
54 #define RK3568_GRF_VO_CON1 0x0364
96 { 0x00b3, 0x0000},
97 { 0x2153, 0x0000},
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-mba6.dtsi30 pinctrl-0 = <&pinctrl_gpiobeeper>;
37 pinctrl-0 = <&pinctrl_gpiobuttons>;
64 pinctrl-0 = <&pinctrl_gpioled>;
90 pinctrl-0 = <&pinctrl_regpcie>;
95 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
112 pinctrl-0 = <&pinctrl_audmux>;
155 pinctrl-0 = <&pinctrl_can1>;
161 pinctrl-0 = <&pinctrl_can2>;
167 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
168 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
[all …]
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp-pinfunc.h26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
[all …]
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
24 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
25 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_hdmi.c27 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
30 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
33 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
36 .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
38 .mpixelclock = ~0ul,
39 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
46 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
49 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
52 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
55 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
/openbmc/linux/include/linux/
H A Drio_ids.h12 #define RIO_VID_IDT 0x0038
13 #define RIO_DID_IDT70K200 0x0310
14 #define RIO_DID_IDTCPS8 0x035c
15 #define RIO_DID_IDTCPS12 0x035d
16 #define RIO_DID_IDTCPS16 0x035b
17 #define RIO_DID_IDTCPS6Q 0x035f
18 #define RIO_DID_IDTCPS10Q 0x035e
19 #define RIO_DID_IDTCPS1848 0x0374
20 #define RIO_DID_IDTCPS1432 0x0375
21 #define RIO_DID_IDTCPS1616 0x0379
[all …]
/openbmc/linux/Documentation/admin-guide/media/
H A Ddvb-usb-cinergyT2-cardlist.rst11 :stub-columns: 0
15 * - TerraTec/qanu USB2.0 Highspeed DVB-T Receiver
16 - 0ccd:0x0038
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-mixer.h17 #define MXR_STATUS 0x0000
18 #define MXR_CFG 0x0004
19 #define MXR_INT_EN 0x0008
20 #define MXR_INT_STATUS 0x000C
21 #define MXR_LAYER_CFG 0x0010
22 #define MXR_VIDEO_CFG 0x0014
23 #define MXR_GRAPHIC0_CFG 0x0020
24 #define MXR_GRAPHIC0_BASE 0x0024
25 #define MXR_GRAPHIC0_SPAN 0x0028
26 #define MXR_GRAPHIC0_SXY 0x002C
[all …]
/openbmc/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.h50 #define XEON_PBAR23LMT_OFFSET 0x0000
51 #define XEON_PBAR45LMT_OFFSET 0x0008
52 #define XEON_PBAR4LMT_OFFSET 0x0008
53 #define XEON_PBAR5LMT_OFFSET 0x000c
54 #define XEON_PBAR23XLAT_OFFSET 0x0010
55 #define XEON_PBAR45XLAT_OFFSET 0x0018
56 #define XEON_PBAR4XLAT_OFFSET 0x0018
57 #define XEON_PBAR5XLAT_OFFSET 0x001c
58 #define XEON_SBAR23LMT_OFFSET 0x0020
59 #define XEON_SBAR45LMT_OFFSET 0x0028
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dxirlink_cit.c29 module_param(ibm_netcam_pro, int, 0);
44 #define CIT_MODEL0 0 /* bcd version 0.01 cams ie the xvp-500 */
125 {0, 0x0000, 0x010c},
126 {0, 0x0006, 0x012c},
127 {0, 0x0078, 0x012d},
128 {0, 0x0046, 0x012f},
129 {0, 0xd141, 0x0124},
130 {0, 0x0000, 0x0127},
131 {0, 0xfea8, 0x0124},
132 {1, 0x0000, 0x0116},
[all …]
/openbmc/linux/include/linux/mfd/
H A Dlochnagar2_regs.h15 #define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D
16 #define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E
17 #define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F
18 #define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010
19 #define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011
20 #define LOCHNAGAR2_PSIA1_CTRL 0x0012
21 #define LOCHNAGAR2_PSIA2_CTRL 0x0013
22 #define LOCHNAGAR2_GF_AIF3_CTRL 0x0014
23 #define LOCHNAGAR2_GF_AIF4_CTRL 0x0015
24 #define LOCHNAGAR2_GF_AIF1_CTRL 0x0016
[all …]
/openbmc/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x07_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
H A Dhw_host1x08_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
H A Dhw_host1x06_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-v0-regs.h15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
[all …]
/openbmc/linux/drivers/net/ethernet/renesas/
H A Drcar_gen4_ptp.h12 #define PTPTIVC_INIT 0x19000000 /* 320MHz */
14 #define RCAR_GEN4_GPTP_OFFSET_S4 0x00018000
22 #define RCAR_GEN4_RXTSTAMP_ENABLED BIT(0)
27 #define RCAR_GEN4_TXTSTAMP_ENABLED BIT(0)
29 #define PTPRO 0
32 PTPTMEC = PTPRO + 0x0010,
33 PTPTMDC = PTPRO + 0x0014,
34 PTPTIVC0 = PTPRO + 0x0020,
35 PTPTOVC00 = PTPRO + 0x0030,
36 PTPTOVC10 = PTPRO + 0x0034,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dmx7ulp-pins.h12 …_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000,…
13 … = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000,…
14 …CS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104,…
15 …CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8,…
16 …CL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C,…
17 …IN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8,…
18 …BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8,…
19 … = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000,…
20 …_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000,…
21 … = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000,…
[all …]

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