1a9065055SDave Jiang /* 2a9065055SDave Jiang * This file is provided under a dual BSD/GPLv2 license. When using or 3a9065055SDave Jiang * redistributing this file, you may do so under either license. 4a9065055SDave Jiang * 5a9065055SDave Jiang * GPL LICENSE SUMMARY 6a9065055SDave Jiang * 7a9065055SDave Jiang * Copyright(c) 2012-2017 Intel Corporation. All rights reserved. 8a9065055SDave Jiang * 9a9065055SDave Jiang * This program is free software; you can redistribute it and/or modify 10a9065055SDave Jiang * it under the terms of version 2 of the GNU General Public License as 11a9065055SDave Jiang * published by the Free Software Foundation. 12a9065055SDave Jiang * 13a9065055SDave Jiang * BSD LICENSE 14a9065055SDave Jiang * 15a9065055SDave Jiang * Copyright(c) 2012-2017 Intel Corporation. All rights reserved. 16a9065055SDave Jiang * 17a9065055SDave Jiang * Redistribution and use in source and binary forms, with or without 18a9065055SDave Jiang * modification, are permitted provided that the following conditions 19a9065055SDave Jiang * are met: 20a9065055SDave Jiang * 21a9065055SDave Jiang * * Redistributions of source code must retain the above copyright 22a9065055SDave Jiang * notice, this list of conditions and the following disclaimer. 23a9065055SDave Jiang * * Redistributions in binary form must reproduce the above copy 24a9065055SDave Jiang * notice, this list of conditions and the following disclaimer in 25a9065055SDave Jiang * the documentation and/or other materials provided with the 26a9065055SDave Jiang * distribution. 27a9065055SDave Jiang * * Neither the name of Intel Corporation nor the names of its 28a9065055SDave Jiang * contributors may be used to endorse or promote products derived 29a9065055SDave Jiang * from this software without specific prior written permission. 30a9065055SDave Jiang * 31a9065055SDave Jiang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32a9065055SDave Jiang * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33a9065055SDave Jiang * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34a9065055SDave Jiang * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35a9065055SDave Jiang * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36a9065055SDave Jiang * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37a9065055SDave Jiang * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38a9065055SDave Jiang * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39a9065055SDave Jiang * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40a9065055SDave Jiang * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41a9065055SDave Jiang * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42a9065055SDave Jiang */ 43a9065055SDave Jiang 44a9065055SDave Jiang #ifndef _NTB_INTEL_GEN1_H_ 45a9065055SDave Jiang #define _NTB_INTEL_GEN1_H_ 46a9065055SDave Jiang 47f6e51c35SDave Jiang #include "ntb_hw_intel.h" 48f6e51c35SDave Jiang 49a9065055SDave Jiang /* Intel Gen1 Xeon hardware */ 50a9065055SDave Jiang #define XEON_PBAR23LMT_OFFSET 0x0000 51a9065055SDave Jiang #define XEON_PBAR45LMT_OFFSET 0x0008 52a9065055SDave Jiang #define XEON_PBAR4LMT_OFFSET 0x0008 53a9065055SDave Jiang #define XEON_PBAR5LMT_OFFSET 0x000c 54a9065055SDave Jiang #define XEON_PBAR23XLAT_OFFSET 0x0010 55a9065055SDave Jiang #define XEON_PBAR45XLAT_OFFSET 0x0018 56a9065055SDave Jiang #define XEON_PBAR4XLAT_OFFSET 0x0018 57a9065055SDave Jiang #define XEON_PBAR5XLAT_OFFSET 0x001c 58a9065055SDave Jiang #define XEON_SBAR23LMT_OFFSET 0x0020 59a9065055SDave Jiang #define XEON_SBAR45LMT_OFFSET 0x0028 60a9065055SDave Jiang #define XEON_SBAR4LMT_OFFSET 0x0028 61a9065055SDave Jiang #define XEON_SBAR5LMT_OFFSET 0x002c 62a9065055SDave Jiang #define XEON_SBAR23XLAT_OFFSET 0x0030 63a9065055SDave Jiang #define XEON_SBAR45XLAT_OFFSET 0x0038 64a9065055SDave Jiang #define XEON_SBAR4XLAT_OFFSET 0x0038 65a9065055SDave Jiang #define XEON_SBAR5XLAT_OFFSET 0x003c 66a9065055SDave Jiang #define XEON_SBAR0BASE_OFFSET 0x0040 67a9065055SDave Jiang #define XEON_SBAR23BASE_OFFSET 0x0048 68a9065055SDave Jiang #define XEON_SBAR45BASE_OFFSET 0x0050 69a9065055SDave Jiang #define XEON_SBAR4BASE_OFFSET 0x0050 70a9065055SDave Jiang #define XEON_SBAR5BASE_OFFSET 0x0054 71a9065055SDave Jiang #define XEON_SBDF_OFFSET 0x005c 72a9065055SDave Jiang #define XEON_NTBCNTL_OFFSET 0x0058 73a9065055SDave Jiang #define XEON_PDOORBELL_OFFSET 0x0060 74a9065055SDave Jiang #define XEON_PDBMSK_OFFSET 0x0062 75a9065055SDave Jiang #define XEON_SDOORBELL_OFFSET 0x0064 76a9065055SDave Jiang #define XEON_SDBMSK_OFFSET 0x0066 77a9065055SDave Jiang #define XEON_USMEMMISS_OFFSET 0x0070 78a9065055SDave Jiang #define XEON_SPAD_OFFSET 0x0080 79a9065055SDave Jiang #define XEON_PBAR23SZ_OFFSET 0x00d0 80a9065055SDave Jiang #define XEON_PBAR45SZ_OFFSET 0x00d1 81a9065055SDave Jiang #define XEON_PBAR4SZ_OFFSET 0x00d1 82a9065055SDave Jiang #define XEON_SBAR23SZ_OFFSET 0x00d2 83a9065055SDave Jiang #define XEON_SBAR45SZ_OFFSET 0x00d3 84a9065055SDave Jiang #define XEON_SBAR4SZ_OFFSET 0x00d3 85a9065055SDave Jiang #define XEON_PPD_OFFSET 0x00d4 86a9065055SDave Jiang #define XEON_PBAR5SZ_OFFSET 0x00d5 87a9065055SDave Jiang #define XEON_SBAR5SZ_OFFSET 0x00d6 88a9065055SDave Jiang #define XEON_WCCNTRL_OFFSET 0x00e0 89a9065055SDave Jiang #define XEON_UNCERRSTS_OFFSET 0x014c 90a9065055SDave Jiang #define XEON_CORERRSTS_OFFSET 0x0158 91a9065055SDave Jiang #define XEON_LINK_STATUS_OFFSET 0x01a2 92a9065055SDave Jiang #define XEON_SPCICMD_OFFSET 0x0504 93a9065055SDave Jiang #define XEON_DEVCTRL_OFFSET 0x0598 94a9065055SDave Jiang #define XEON_DEVSTS_OFFSET 0x059a 95a9065055SDave Jiang #define XEON_SLINK_STATUS_OFFSET 0x05a2 96a9065055SDave Jiang #define XEON_B2B_SPAD_OFFSET 0x0100 97a9065055SDave Jiang #define XEON_B2B_DOORBELL_OFFSET 0x0140 98a9065055SDave Jiang #define XEON_B2B_XLAT_OFFSETL 0x0144 99a9065055SDave Jiang #define XEON_B2B_XLAT_OFFSETU 0x0148 100a9065055SDave Jiang #define XEON_PPD_CONN_MASK 0x03 101a9065055SDave Jiang #define XEON_PPD_CONN_TRANSPARENT 0x00 102a9065055SDave Jiang #define XEON_PPD_CONN_B2B 0x01 103a9065055SDave Jiang #define XEON_PPD_CONN_RP 0x02 104a9065055SDave Jiang #define XEON_PPD_DEV_MASK 0x10 105a9065055SDave Jiang #define XEON_PPD_DEV_USD 0x00 106a9065055SDave Jiang #define XEON_PPD_DEV_DSD 0x10 107a9065055SDave Jiang #define XEON_PPD_SPLIT_BAR_MASK 0x40 108a9065055SDave Jiang 109a9065055SDave Jiang #define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK) 110a9065055SDave Jiang #define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD) 111a9065055SDave Jiang #define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD) 112a9065055SDave Jiang #define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD) 113a9065055SDave Jiang #define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD) 114a9065055SDave Jiang #define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD) 115a9065055SDave Jiang #define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD) 116a9065055SDave Jiang 117a9065055SDave Jiang #define XEON_MW_COUNT 2 118a9065055SDave Jiang #define HSX_SPLIT_BAR_MW_COUNT 3 119a9065055SDave Jiang #define XEON_DB_COUNT 15 120a9065055SDave Jiang #define XEON_DB_LINK 15 121a9065055SDave Jiang #define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK) 122a9065055SDave Jiang #define XEON_DB_MSIX_VECTOR_COUNT 4 123a9065055SDave Jiang #define XEON_DB_MSIX_VECTOR_SHIFT 5 124a9065055SDave Jiang #define XEON_DB_TOTAL_SHIFT 16 125a9065055SDave Jiang #define XEON_SPAD_COUNT 16 126a9065055SDave Jiang 127a9065055SDave Jiang /* Use the following addresses for translation between b2b ntb devices in case 128a9065055SDave Jiang * the hardware default values are not reliable. */ 129a9065055SDave Jiang #define XEON_B2B_BAR0_ADDR 0x1000000000000000ull 130a9065055SDave Jiang #define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull 131a9065055SDave Jiang #define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull 132a9065055SDave Jiang #define XEON_B2B_BAR4_ADDR32 0x20000000u 133a9065055SDave Jiang #define XEON_B2B_BAR5_ADDR32 0x40000000u 134a9065055SDave Jiang 135a9065055SDave Jiang /* The peer ntb secondary config space is 32KB fixed size */ 136a9065055SDave Jiang #define XEON_B2B_MIN_SIZE 0x8000 137a9065055SDave Jiang 138a9065055SDave Jiang /* flags to indicate hardware errata */ 139a9065055SDave Jiang #define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0) 140a9065055SDave Jiang #define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1) 141a9065055SDave Jiang #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2) 142a9065055SDave Jiang #define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3) 143134a8654SDave Jiang #define NTB_HWERR_BAR_ALIGN BIT_ULL(4) 144*75b6f648SDave Jiang #define NTB_HWERR_LTR_BAD BIT_ULL(5) 145a9065055SDave Jiang 146f6e51c35SDave Jiang extern struct intel_b2b_addr xeon_b2b_usd_addr; 147f6e51c35SDave Jiang extern struct intel_b2b_addr xeon_b2b_dsd_addr; 148f6e51c35SDave Jiang 149f6e51c35SDave Jiang int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max, 150f6e51c35SDave Jiang int msix_shift, int total_shift); 151f6e51c35SDave Jiang enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd); 152ebb09b33SLeonid Ravich void ndev_db_addr(struct intel_ntb_dev *ndev, 153ebb09b33SLeonid Ravich phys_addr_t *db_addr, resource_size_t *db_size, 154ebb09b33SLeonid Ravich phys_addr_t reg_addr, unsigned long reg); 155f6e51c35SDave Jiang u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio); 156f6e51c35SDave Jiang int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits, 157f6e51c35SDave Jiang void __iomem *mmio); 158f6e51c35SDave Jiang int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx); 159f6e51c35SDave Jiang int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx); 160f6e51c35SDave Jiang int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, 161f6e51c35SDave Jiang resource_size_t *addr_align, resource_size_t *size_align, 162f6e51c35SDave Jiang resource_size_t *size_max); 163f6e51c35SDave Jiang int intel_ntb_peer_mw_count(struct ntb_dev *ntb); 164f6e51c35SDave Jiang int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx, 165f6e51c35SDave Jiang phys_addr_t *base, resource_size_t *size); 166f6e51c35SDave Jiang u64 intel_ntb_link_is_up(struct ntb_dev *ntb, enum ntb_speed *speed, 167f6e51c35SDave Jiang enum ntb_width *width); 168f6e51c35SDave Jiang int intel_ntb_link_disable(struct ntb_dev *ntb); 169f6e51c35SDave Jiang u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb); 170f6e51c35SDave Jiang int intel_ntb_db_vector_count(struct ntb_dev *ntb); 171f6e51c35SDave Jiang u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector); 172f6e51c35SDave Jiang int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits); 173f6e51c35SDave Jiang int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits); 174f6e51c35SDave Jiang int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb); 175f6e51c35SDave Jiang int intel_ntb_spad_count(struct ntb_dev *ntb); 176f6e51c35SDave Jiang u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx); 177f6e51c35SDave Jiang int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val); 178f6e51c35SDave Jiang u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx); 179f6e51c35SDave Jiang int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, int sidx, 180f6e51c35SDave Jiang u32 val); 181f6e51c35SDave Jiang int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx, 182f6e51c35SDave Jiang phys_addr_t *spad_addr); 183f6e51c35SDave Jiang int xeon_link_is_up(struct intel_ntb_dev *ndev); 184f6e51c35SDave Jiang 185a9065055SDave Jiang #endif 186