drm/rockchip/dw_hdmi-rockchip.c

23 #define RK3228_GRF_SOC_CON2		0x0408
26 #define RK3228_GRF_SOC_CON6		0x0418
31 #define RK3288_GRF_SOC_CON6		0x025C
33 #define RK3328_GRF_SOC_CON2		0x0408
38 #define RK3328_GRF_SOC_CON3		0x040c
44 #define RK3328_GRF_SOC_CON4		0x0410
51 #define RK3399_GRF_SOC_CON20		0x6250
54 #define RK3568_GRF_VO_CON1		0x0364
96 			{ 0x00b3, 0x0000},
97 			{ 0x2153, 0x0000},
98 			{ 0x40f3, 0x0000}
102 			{ 0x00b3, 0x0000},
103 			{ 0x2153, 0x0000},
104 			{ 0x40f3, 0x0000}
108 			{ 0x00b3, 0x0000},
109 			{ 0x2153, 0x0000},
110 			{ 0x40f3, 0x0000}
114 			{ 0x0072, 0x0001},
115 			{ 0x2142, 0x0001},
116 			{ 0x40a2, 0x0001},
120 			{ 0x0072, 0x0001},
121 			{ 0x2142, 0x0001},
122 			{ 0x40a2, 0x0001},
126 			{ 0x013e, 0x0003},
127 			{ 0x217e, 0x0002},
128 			{ 0x4061, 0x0002}
132 			{ 0x0072, 0x0001},
133 			{ 0x2145, 0x0002},
134 			{ 0x4061, 0x0002}
138 			{ 0x0072, 0x0001},
142 			{ 0x0051, 0x0002},
143 			{ 0x2145, 0x0002},
144 			{ 0x4061, 0x0002}
148 			{ 0x0051, 0x0002},
149 			{ 0x2145, 0x0002},
150 			{ 0x4061, 0x0002}
154 			{ 0x0051, 0x0002},
155 			{ 0x2145, 0x0002},
156 			{ 0x4061, 0x0002}
160 			{ 0x0051, 0x0003},
161 			{ 0x214c, 0x0003},
162 			{ 0x4064, 0x0003}
166 			{ 0x0040, 0x0003 },
167 			{ 0x3b4c, 0x0003 },
168 			{ 0x5a64, 0x0003 },
171 		~0UL, {
172 			{ 0x00a0, 0x000a },
173 			{ 0x2001, 0x000f },
174 			{ 0x4002, 0x000f },
182 		40000000,  { 0x0018, 0x0018, 0x0018 },
184 		65000000,  { 0x0028, 0x0028, 0x0028 },
186 		66000000,  { 0x0038, 0x0038, 0x0038 },
188 		74250000,  { 0x0028, 0x0038, 0x0038 },
190 		83500000,  { 0x0028, 0x0038, 0x0038 },
192 		146250000, { 0x0038, 0x0038, 0x0038 },
194 		148500000, { 0x0000, 0x0038, 0x0038 },
196 		600000000, { 0x0000, 0x0000, 0x0000 },
198 		~0UL,      { 0x0000, 0x0000, 0x0000},
204 	{ 74250000,  0x8009, 0x0004, 0x0272},
205 	{ 148500000, 0x802b, 0x0004, 0x028d},
206 	{ 297000000, 0x8039, 0x0005, 0x028d},
207 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
241 	hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");  in rockchip_hdmi_parse_dt()
249 	return 0;  in rockchip_hdmi_parse_dt()
270 	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {  in dw_hdmi_rockchip_mode_valid()
315 	if (hdmi->chip_data->lcdsel_grf_reg < 0)  in dw_hdmi_rockchip_encoder_enable()
325 	if (ret < 0) {  in dw_hdmi_rockchip_encoder_enable()
331 	if (ret != 0)  in dw_hdmi_rockchip_encoder_enable()
349 	return 0;  in dw_hdmi_rockchip_encoder_atomic_check()
411 			HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |  in dw_hdmi_rk3328_read_hpd()
425 		HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |  in dw_hdmi_rk3328_setup_hpd()
430 		HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |  in dw_hdmi_rk3328_setup_hpd()
467 	.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
505 	.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
584 						  dev->of_node, 0, 0);  in dw_hdmi_rockchip_bind()
592 	if (encoder->possible_crtcs == 0)  in dw_hdmi_rockchip_bind()
653 	return 0;  in dw_hdmi_rockchip_bind()
700 	return 0;  in dw_hdmi_rockchip_resume()