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12

/openbmc/linux/Documentation/devicetree/bindings/gpu/
H A Dvivante,gc.yaml67 reg = <0x00130000 0x4000>;
68 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5271.h12 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
15 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
16 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
17 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
18 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
19 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
20 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
21 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
H A Dimmap_5282.h11 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
12 #define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040)
13 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
14 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
15 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140)
16 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180)
17 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0)
18 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
19 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
20 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
H A Dimmap_5275.h13 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
14 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
15 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
16 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
17 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
18 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
19 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
20 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
21 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
22 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
H A Dimmap_5235.h12 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
15 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
16 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
17 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
18 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
19 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
20 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
21 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
/openbmc/u-boot/arch/x86/include/asm/fsp/
H A Dfsp_fv.h11 #define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
12 #define EFI_FV_FILE_ATTR_FIXED 0x00000100
13 #define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
16 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
17 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
18 #define EFI_FVB2_READ_STATUS 0x00000004
19 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
20 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
21 #define EFI_FVB2_WRITE_STATUS 0x00000020
22 #define EFI_FVB2_LOCK_CAP 0x00000040
[all …]
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dsoc.h20 * the synchronous boot mode is selected. When ASDO is "0" (i.e
24 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
25 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
26 * decoded at 0xf0000000.
35 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
36 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
37 #define EP93XX_CS1_PHYS_BASE 0x10000000
38 #define EP93XX_CS2_PHYS_BASE 0x20000000
39 #define EP93XX_CS3_PHYS_BASE 0x30000000
40 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/
H A Dsouthcluster.asl13 Name (_ADR, 0)
14 Name (_BBN, 0)
20 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
22 /* IO Region 0 */
24 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
27 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
31 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
36 0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000,
37 0x00000010, , , GP00)
39 /* PSH Memory Region 0 */
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm528xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam437x-idk-evm.dts108 pinctrl-0 = <&gpio_keys_pins_default>;
110 switch@0 {
119 #clock-cells = <0>;
128 AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
134 AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
135 AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
141 AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
142 AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
148 AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
149 AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
[all …]
H A Dam437x-sk-evm.dts34 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
35 brightness-levels = <0 51 53 56 62 75 101 152 255>;
50 matrix_keypad: matrix_keypad@0 {
54 pinctrl-0 = <&matrix_keypad_pins>;
66 MATRIX_KEY(0, 0, KEY_DOWN)
67 MATRIX_KEY(0, 1, KEY_RIGHT)
68 MATRIX_KEY(1, 0, KEY_LEFT)
77 pinctrl-0 = <&leds_pins>;
79 led@0 {
81 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
[all …]
H A Dam43x-epos-evm.dts40 vbat: fixedregulator@0 {
62 hsync-active = <0>;
63 vsync-active = <0>;
75 matrix_keypad: matrix_keypad@0 {
90 linux,keymap = <0x00000201 /* P1 */
91 0x01000204 /* P4 */
92 0x02000207 /* P7 */
93 0x0300020a /* NUMERIC_STAR */
94 0x00010202 /* P2 */
95 0x01010205 /* P5 */
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-ich.c27 GPIO_USE_SEL = 0,
34 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
35 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
36 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
37 {0x18, 0x18, 0x18}, /* BLINK offset */
41 0x30, 0x10, 0x10,
45 {0x00, 0x80, 0x00},
46 {0x04, 0x84, 0x00},
47 {0x08, 0x88, 0x00},
51 0x10, 0x10, 0x00,
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-idk-evm.dts104 pinctrl-0 = <&gpio_keys_pins_default>;
106 switch-0 {
115 #clock-cells = <0>;
125 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
176 AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
182 AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
183 AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
189 AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
190 AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
196 AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
[all …]
H A Dam437x-sk-evm.dts31 #clock-cells = <0>;
38 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 51 53 56 62 75 101 152 255>;
73 pinctrl-0 = <&matrix_keypad_pins>;
85 MATRIX_KEY(0, 0, KEY_DOWN)
86 MATRIX_KEY(0, 1, KEY_RIGHT)
87 MATRIX_KEY(1, 0, KEY_LEFT)
96 pinctrl-0 = <&leds_pins>;
100 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
131 pinctrl-0 = <&lcd_pins>;
[all …]
H A Dam43x-epos-evm.dts62 pinctrl-0 = <&matrix_keypad_default>;
76 linux,keymap = <0x00000201 /* P1 */
77 0x01000204 /* P4 */
78 0x02000207 /* P7 */
79 0x0300020a /* NUMERIC_STAR */
80 0x00010202 /* P2 */
81 0x01010205 /* P5 */
82 0x02010208 /* P8 */
83 0x03010200 /* P0 */
84 0x00020203 /* P3 */
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/linux/drivers/message/fusion/lsi/
H A Dmpi_log_sas.h16 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
17 #define SAS_LOGINFO_MASK 0xFFFF0000
20 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
23 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
25 /* Bits 15-0: LOGINFO_CODE Specific */
31 #define IOC_LOGINFO_ORIGINATOR_IOP (0x00000000)
32 #define IOC_LOGINFO_ORIGINATOR_PL (0x01000000)
33 #define IOC_LOGINFO_ORIGINATOR_IR (0x02000000)
35 #define IOC_LOGINFO_ORIGINATOR_MASK (0x0F000000)
40 #define IOC_LOGINFO_CODE_MASK (0x00FF0000)
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h11 #define ROMCP_ARB_BASE_ADDR 0x00000000
12 #define ROMCP_ARB_END_ADDR 0x000FFFFF
15 #define GPU_2D_ARB_BASE_ADDR 0x02200000
16 #define GPU_2D_ARB_END_ADDR 0x02203FFF
17 #define OPENVG_ARB_BASE_ADDR 0x02204000
18 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #define CAAM_ARB_BASE_ADDR 0x00100000
21 #define CAAM_ARB_END_ADDR 0x00107FFF
22 #define GPU_ARB_BASE_ADDR 0x01800000
23 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]

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