1a8c21a54SThe etnaviv authors #ifndef STATE_HI_XML 2a8c21a54SThe etnaviv authors #define STATE_HI_XML 3a8c21a54SThe etnaviv authors 4a8c21a54SThe etnaviv authors /* Autogenerated file, DO NOT EDIT manually! 5a8c21a54SThe etnaviv authors 6a8c21a54SThe etnaviv authors This file was generated by the rules-ng-ng headergen tool in this git repository: 7a8c21a54SThe etnaviv authors http://0x04.net/cgit/index.cgi/rules-ng-ng 8a8c21a54SThe etnaviv authors git clone git://0x04.net/rules-ng-ng 9a8c21a54SThe etnaviv authors 10a8c21a54SThe etnaviv authors The rules-ng-ng source files this header was generated from are: 11*50f79da4SLucas Stach - state.xml ( 27198 bytes, from 2022-04-22 10:35:24) 12*50f79da4SLucas Stach - common.xml ( 35468 bytes, from 2020-10-28 12:56:03) 13*50f79da4SLucas Stach - common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03) 14*50f79da4SLucas Stach - state_hi.xml ( 34804 bytes, from 2022-12-02 09:06:28) 15*50f79da4SLucas Stach - copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) 16*50f79da4SLucas Stach - state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03) 17*50f79da4SLucas Stach - state_3d.xml ( 84445 bytes, from 2022-11-15 15:59:38) 18*50f79da4SLucas Stach - state_blt.xml ( 14424 bytes, from 2022-11-07 11:18:41) 19*50f79da4SLucas Stach - state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) 20a8c21a54SThe etnaviv authors 21*50f79da4SLucas Stach Copyright (C) 2012-2022 by the following authors: 22059ad731SLucas Stach - Wladimir J. van der Laan <laanwj@gmail.com> 23059ad731SLucas Stach - Christian Gmeiner <christian.gmeiner@gmail.com> 24059ad731SLucas Stach - Lucas Stach <l.stach@pengutronix.de> 25059ad731SLucas Stach - Russell King <rmk@arm.linux.org.uk> 26059ad731SLucas Stach 27059ad731SLucas Stach Permission is hereby granted, free of charge, to any person obtaining a 28059ad731SLucas Stach copy of this software and associated documentation files (the "Software"), 29059ad731SLucas Stach to deal in the Software without restriction, including without limitation 30059ad731SLucas Stach the rights to use, copy, modify, merge, publish, distribute, sub license, 31059ad731SLucas Stach and/or sell copies of the Software, and to permit persons to whom the 32059ad731SLucas Stach Software is furnished to do so, subject to the following conditions: 33059ad731SLucas Stach 34059ad731SLucas Stach The above copyright notice and this permission notice (including the 35059ad731SLucas Stach next paragraph) shall be included in all copies or substantial portions 36059ad731SLucas Stach of the Software. 37059ad731SLucas Stach 38059ad731SLucas Stach THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 39059ad731SLucas Stach IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 40059ad731SLucas Stach FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 41059ad731SLucas Stach THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 42059ad731SLucas Stach LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43059ad731SLucas Stach FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 44059ad731SLucas Stach DEALINGS IN THE SOFTWARE. 45a8c21a54SThe etnaviv authors */ 46a8c21a54SThe etnaviv authors 47a8c21a54SThe etnaviv authors 48a8c21a54SThe etnaviv authors #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001 49a8c21a54SThe etnaviv authors #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002 50a8c21a54SThe etnaviv authors #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003 518ed226ffSChristian Gmeiner #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004 528ed226ffSChristian Gmeiner #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005 538ed226ffSChristian Gmeiner #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006 54a8c21a54SThe etnaviv authors #define VIVS_HI 0x00000000 55a8c21a54SThe etnaviv authors 56a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL 0x00000000 57a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001 58a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002 59a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc 60a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 2 61a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK) 62a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200 63a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400 64a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800 65a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000 66a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000 67a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000 68a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000 69a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000 70a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000 71a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 20 72a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK) 73a8c21a54SThe etnaviv authors 74a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE 0x00000004 75a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_FE 0x00000001 76a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_DE 0x00000002 77a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_PE 0x00000004 78a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_SH 0x00000008 79a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_PA 0x00000010 80a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_SE 0x00000020 81a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_RA 0x00000040 82a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_TX 0x00000080 83a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_VG 0x00000100 84a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_IM 0x00000200 85a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_FP 0x00000400 86a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_TS 0x00000800 87b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_BL 0x00001000 88b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_ASYNCFE 0x00002000 89b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_MC 0x00004000 90b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_PPA 0x00008000 91b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_WD 0x00010000 92b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_NN 0x00020000 93b9e352edSGuido Günther #define VIVS_HI_IDLE_STATE_TP 0x00040000 94a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000 95a8c21a54SThe etnaviv authors 96a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG 0x00000008 97a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f 98a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0 99a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK) 100a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0 101a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4 102a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK) 103a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00 104a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8 105a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK) 106a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000 107a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12 108a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK) 109a8c21a54SThe etnaviv authors 110a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS 0x0000000c 111a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f 112a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0 113a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK) 114a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0 115a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4 116a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK) 117a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100 118a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 119a8c21a54SThe etnaviv authors 120a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 121128a9b1dSLucas Stach #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff 122a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 123a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) 124128a9b1dSLucas Stach #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 125a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 126a8c21a54SThe etnaviv authors 127a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL 0x00000014 128a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff 129a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0 130a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK) 131a8c21a54SThe etnaviv authors 132a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY 0x00000018 133a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000 134a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24 135a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK) 136a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000 137a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16 138a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK) 139a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000 140a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12 141a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK) 142a8c21a54SThe etnaviv authors 143a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_FEATURE 0x0000001c 144a8c21a54SThe etnaviv authors 145a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MODEL 0x00000020 146a8c21a54SThe etnaviv authors 147a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_REV 0x00000024 148a8c21a54SThe etnaviv authors 149a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_DATE 0x00000028 150a8c21a54SThe etnaviv authors 151a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_TIME 0x0000002c 152a8c21a54SThe etnaviv authors 1538ed226ffSChristian Gmeiner #define VIVS_HI_CHIP_CUSTOMER_ID 0x00000030 1548ed226ffSChristian Gmeiner 155a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034 156a8c21a54SThe etnaviv authors 157a8c21a54SThe etnaviv authors #define VIVS_HI_CACHE_CONTROL 0x00000038 158a8c21a54SThe etnaviv authors 159a8c21a54SThe etnaviv authors #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c 160a8c21a54SThe etnaviv authors 161a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040 162a8c21a54SThe etnaviv authors 163a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044 164a8c21a54SThe etnaviv authors 165a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS 0x00000048 166a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f 167a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0 168a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK) 169a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0 170a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4 171a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK) 172a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00 173a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8 174a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK) 175a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000 176a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12 177a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK) 178a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000 179a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20 180a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK) 181a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000 182a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25 183a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK) 184a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000 185a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28 186a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK) 187a8c21a54SThe etnaviv authors 188a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c 189a8c21a54SThe etnaviv authors 190a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050 191a8c21a54SThe etnaviv authors 192a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058 193a8c21a54SThe etnaviv authors 194a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c 195a8c21a54SThe etnaviv authors 196a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_LASTS 0x00000060 197a8c21a54SThe etnaviv authors 198a8c21a54SThe etnaviv authors #define VIVS_HI_GP_OUT0 0x00000064 199a8c21a54SThe etnaviv authors 200a8c21a54SThe etnaviv authors #define VIVS_HI_GP_OUT1 0x00000068 201a8c21a54SThe etnaviv authors 202a8c21a54SThe etnaviv authors #define VIVS_HI_GP_OUT2 0x0000006c 203a8c21a54SThe etnaviv authors 204a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONTROL 0x00000070 205a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001 206a8c21a54SThe etnaviv authors 207a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074 208a8c21a54SThe etnaviv authors 209a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078 210a8c21a54SThe etnaviv authors 211a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c 212a8c21a54SThe etnaviv authors 213a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2 0x00000080 214a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff 215a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0 216a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK) 217a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00 218a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8 219a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK) 220a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000 221a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16 222a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK) 223a8c21a54SThe etnaviv authors 224a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084 225a8c21a54SThe etnaviv authors 226a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088 227a8c21a54SThe etnaviv authors 228e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3 0x0000008c 229e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0 230e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4 231e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK) 232e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007 233e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 234e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) 235e2a2e263SRussell King 236059ad731SLucas Stach #define VIVS_HI_COMPRESSION_FLAGS 0x00000090 237059ad731SLucas Stach #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040 238059ad731SLucas Stach 239a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 240a8c21a54SThe etnaviv authors 241e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4 0x0000009c 242e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000 243e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12 244e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK) 245e2a2e263SRussell King 246e2a2e263SRussell King #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0 247e2a2e263SRussell King 248e2a2e263SRussell King #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 249e2a2e263SRussell King 250059ad731SLucas Stach #define VIVS_HI_BLT_INTR 0x000000d4 251059ad731SLucas Stach 2528ed226ffSChristian Gmeiner #define VIVS_HI_CHIP_ECO_ID 0x000000e8 2538ed226ffSChristian Gmeiner 254059ad731SLucas Stach #define VIVS_HI_AUXBIT 0x000000ec 255059ad731SLucas Stach 256a8c21a54SThe etnaviv authors #define VIVS_PM 0x00000000 257a8c21a54SThe etnaviv authors 258a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS 0x00000100 259a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001 260a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002 261a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004 262a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0 263a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4 264a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK) 265a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000 266a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16 267a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK) 268a8c21a54SThe etnaviv authors 269a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS 0x00000104 270a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001 271a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002 272a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004 2737d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008 2747d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010 2757d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020 2767d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040 2777d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080 2787d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000 2797d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000 280a8c21a54SThe etnaviv authors 281a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS 0x00000108 282a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 283a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002 284a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004 285e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008 286e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010 287e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020 288e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040 289e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 290a8c21a54SThe etnaviv authors 291a8c21a54SThe etnaviv authors #define VIVS_PM_PULSE_EATER 0x0000010c 292059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001 293059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00 294059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8 295059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK) 296059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK16 0x00010000 297059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK17 0x00020000 298059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000 299059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK19 0x00080000 300059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK20 0x00100000 301059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK22 0x00400000 302059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK23 0x00800000 303a8c21a54SThe etnaviv authors 304a8c21a54SThe etnaviv authors #define VIVS_MMUv2 0x00000000 305a8c21a54SThe etnaviv authors 306a8c21a54SThe etnaviv authors #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180 307a8c21a54SThe etnaviv authors 308a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION 0x00000184 309a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001 310a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0 311a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000 312a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001 313a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008 314a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010 315a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4 316a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010 317a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080 318a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100 319a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00 320a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10 321a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK) 322a8c21a54SThe etnaviv authors 323a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS 0x00000188 324*50f79da4SLucas Stach #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x0000000f 325a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0 326a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK) 327*50f79da4SLucas Stach #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x000000f0 328a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4 329a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK) 330*50f79da4SLucas Stach #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000f00 331a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8 332a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK) 333*50f79da4SLucas Stach #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x0000f000 334a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12 335a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK) 336a8c21a54SThe etnaviv authors 337a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONTROL 0x0000018c 338a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001 339a8c21a54SThe etnaviv authors 340a8c21a54SThe etnaviv authors #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) 341a8c21a54SThe etnaviv authors #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 342a8c21a54SThe etnaviv authors #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 343a8c21a54SThe etnaviv authors 344059ad731SLucas Stach #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4 345059ad731SLucas Stach 346059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG 0x000001ac 347059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff 348059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0 349059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK) 350059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000 351059ad731SLucas Stach 352059ad731SLucas Stach #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) 353059ad731SLucas Stach #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004 354059ad731SLucas Stach #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008 355059ad731SLucas Stach 356059ad731SLucas Stach #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380 357059ad731SLucas Stach 358059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS 0x00000384 359059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003 360059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0 361059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK) 362059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030 363059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4 364059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK) 365059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300 366059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8 367059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK) 368059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000 369059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12 370059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK) 371059ad731SLucas Stach 372059ad731SLucas Stach #define VIVS_MMUv2_SEC_CONTROL 0x00000388 373059ad731SLucas Stach #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001 374059ad731SLucas Stach 375059ad731SLucas Stach #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c 376059ad731SLucas Stach 377059ad731SLucas Stach #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390 378059ad731SLucas Stach 379059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONTROL 0x00000394 380059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001 381059ad731SLucas Stach 382059ad731SLucas Stach #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398 383059ad731SLucas Stach 384059ad731SLucas Stach #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c 385059ad731SLucas Stach 386059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0 387059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff 388059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0 389059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK) 390059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000 391059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000 392059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16 393059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK) 394059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000 395059ad731SLucas Stach 396059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4 397059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff 398059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0 399059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK) 400059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000 401059ad731SLucas Stach 402059ad731SLucas Stach #define VIVS_MMUv2_AHB_CONTROL 0x000003a8 403059ad731SLucas Stach #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001 404059ad731SLucas Stach #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002 405059ad731SLucas Stach 406a8c21a54SThe etnaviv authors #define VIVS_MC 0x00000000 407a8c21a54SThe etnaviv authors 408a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 409a8c21a54SThe etnaviv authors 410a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404 411a8c21a54SThe etnaviv authors 412a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408 413a8c21a54SThe etnaviv authors 414a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c 415a8c21a54SThe etnaviv authors 416a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410 417a8c21a54SThe etnaviv authors 418a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY 0x00000414 419a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008 420a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000 421a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000 422a8c21a54SThe etnaviv authors 423a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418 424a8c21a54SThe etnaviv authors 425a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c 426a8c21a54SThe etnaviv authors 427a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420 428a8c21a54SThe etnaviv authors 429a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424 430a8c21a54SThe etnaviv authors 431a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428 432a8c21a54SThe etnaviv authors 433a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c 434a8c21a54SThe etnaviv authors 435a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_FLUSH 0x00000430 436a8c21a54SThe etnaviv authors 437a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438 438a8c21a54SThe etnaviv authors 439a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_READ0 0x0000043c 440a8c21a54SThe etnaviv authors 441a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_READ1 0x00000440 442a8c21a54SThe etnaviv authors 443a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_WRITE 0x00000444 444a8c21a54SThe etnaviv authors 445a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_RA_READ 0x00000448 446a8c21a54SThe etnaviv authors 447a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_TX_READ 0x0000044c 448a8c21a54SThe etnaviv authors 449a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_FE_READ 0x00000450 450a8c21a54SThe etnaviv authors 451a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_PE_READ 0x00000454 452a8c21a54SThe etnaviv authors 453a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_DE_READ 0x00000458 454a8c21a54SThe etnaviv authors 455a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_SH_READ 0x0000045c 456a8c21a54SThe etnaviv authors 457a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_PA_READ 0x00000460 458a8c21a54SThe etnaviv authors 459a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_SE_READ 0x00000464 460a8c21a54SThe etnaviv authors 461a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_MC_READ 0x00000468 462a8c21a54SThe etnaviv authors 463a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_HI_READ 0x0000046c 464a8c21a54SThe etnaviv authors 465a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0 0x00000470 466059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff 467a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 468*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT 0x0000000a 469*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT 0x0000000b 470*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT 0x0000000c 471a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f 472*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_LK_COUNT 0x00000010 473*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE_STALL_COUNT 0x00000011 474*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE_PROCESS_COUNT 0x00000012 475059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00 476a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 477a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 478059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000 479a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 480a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 481a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 482a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000 483a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 484a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 485a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 486059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000 487a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 488a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 489a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 490a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000 491a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000 492a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000 493a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000 494a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000 495a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000 496a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000 497a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 498a8c21a54SThe etnaviv authors 499a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1 0x00000474 500059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff 501a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 502a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 503a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 504a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005 505a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006 506a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 507a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 508*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_PA_DROPED_PRIM_COUNTER 0x00000009 509*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_PA_FRUSTUM_CLIPPED_PRIM_COUNTER 0x0000000a 510a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f 511059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00 512a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 513a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 514a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 515*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_SE_TRIVIAL_REJECTED_LINE_COUNT 0x00000400 516a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 517059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000 518a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 519a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 520a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 521a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000 522a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000 523a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000 524a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 525a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 526a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 527*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_HZ_CACHE_MISS_COUNTER 0x00110000 528*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_HZ_CACHE_MISS_COUNTER 0x00120000 529059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000 530a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 531a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 532a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 533a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000 534a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000 535a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000 536a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000 537a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000 538a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000 539a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000 540a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000 541a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 542a8c21a54SThe etnaviv authors 543a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2 0x00000478 544059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff 545a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 546a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 547a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 548a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 549*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_COLORPIPE 0x00000004 550*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_COLORPIPE 0x00000005 551*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_DEPTHPIPE 0x00000007 552*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_SENTOUT_FROM_DEPTHPIPE 0x00000008 553*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_DEPTHPIPE 0x00000009 554*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_DEPTHPIPE 0x0000000a 555*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_DEPTHPIPE 0x0000000b 556*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_OTHERS 0x0000000c 557*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_OTHERS 0x0000000d 558*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_FROM_OTHERS 0x0000000e 559*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_OTHERS 0x0000000f 560*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_FE_READ_BANDWIDTH 0x00000015 561*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_MMU_READ_BANDWIDTH 0x00000016 562*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_READ_BANDWIDTH 0x00000017 563*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_READ_BANDWIDTH 0x00000018 564*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_READ_BANDWIDTH 0x00000019 565*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_PE_WRITE_BANDWIDTH 0x0000001a 566*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_WRITE_BANDWIDTH 0x0000001b 567*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_WRITE_BANDWIDTH 0x0000001c 568*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_WRITE_BANDWIDTH 0x0000001d 569059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00 570a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 571a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 572a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 573a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 574a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 575*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2__MASK 0x00ff0000 576*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2__SHIFT 16 577*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_READ_REQUEST_COUNT 0x00000000 578*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_WRITE_REQUEST_COUNT 0x00040000 579*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI1_WRITE_REQUEST_COUNT 0x00050000 580*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI0 0x00080000 581*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI1 0x00090000 582*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI0 0x000c0000 583*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI1 0x000d0000 584*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_RESET 0x000f0000 585*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_MINMAX_LATENCY 0x00100000 586*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_LATENCY 0x00110000 587*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_REQUEST_COUNT 0x00120000 588*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_MINMAX_LATENCY 0x00130000 589*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_LATENCY 0x00140000 590*50f79da4SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_REQUEST_COUNT 0x00150000 591059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000 592059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24 593059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000 594a8c21a54SThe etnaviv authors 595a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG3 0x0000047c 596a8c21a54SThe etnaviv authors 597a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG 0x00000480 598a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f 599a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0 600a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK) 601a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0 602a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4 603a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK) 604a8c21a54SThe etnaviv authors 605a8c21a54SThe etnaviv authors #define VIVS_MC_START_COMPOSITION 0x00000554 606a8c21a54SThe etnaviv authors 607059ad731SLucas Stach #define VIVS_MC_FLAGS 0x00000558 608059ad731SLucas Stach #define VIVS_MC_FLAGS_128B_MERGE 0x00000001 609059ad731SLucas Stach #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000 610059ad731SLucas Stach 611059ad731SLucas Stach #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c 612059ad731SLucas Stach 613059ad731SLucas Stach #define VIVS_MC_PROFILE_L2_READ 0x00000564 614a8c21a54SThe etnaviv authors 615*50f79da4SLucas Stach #define VIVS_MC_MC_LATENCY_RESET 0x00000568 616*50f79da4SLucas Stach 617*50f79da4SLucas Stach #define VIVS_MC_MC_AXI_MAX_MIN_LATENCY 0x0000056c 618*50f79da4SLucas Stach 619*50f79da4SLucas Stach #define VIVS_MC_MC_AXI_TOTAL_LATENCY 0x00000570 620*50f79da4SLucas Stach 621*50f79da4SLucas Stach #define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574 622*50f79da4SLucas Stach 623a8c21a54SThe etnaviv authors 624a8c21a54SThe etnaviv authors #endif /* STATE_HI_XML */ 625