Lines Matching +full:0 +full:x00130000
34 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
35 brightness-levels = <0 51 53 56 62 75 101 152 255>;
50 matrix_keypad: matrix_keypad@0 {
54 pinctrl-0 = <&matrix_keypad_pins>;
66 MATRIX_KEY(0, 0, KEY_DOWN)
67 MATRIX_KEY(0, 1, KEY_RIGHT)
68 MATRIX_KEY(1, 0, KEY_LEFT)
77 pinctrl-0 = <&leds_pins>;
79 led@0 {
81 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
112 pinctrl-0 = <&lcd_pins>;
126 hsync-active = <0>;
127 vsync-active = <0>;
143 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
144 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
145 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
146 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
152 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
153 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
154 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
155 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
161 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
162 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
168 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
169 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
175 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
176 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
177 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
178 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
179 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
180 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
181 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
187 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
193 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
194 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
200 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
201 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
202 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
203 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
204 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
205 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
206 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
207 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
208 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
209 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
210 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
211 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
212 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
213 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
214 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
220 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
221 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
222 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
223 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
224 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
225 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
226 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
227 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
228 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
229 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
230 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
231 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
232 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
233 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
234 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
241 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
242 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
243 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
244 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
245 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
246 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
247 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
248 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
249 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
250 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
251 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
252 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
255 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
256 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
257 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
258 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
259 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
260 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
261 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
262 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
263 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
264 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
265 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
266 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
273 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
274 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
275 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
276 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
277 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
278 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
279 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
280 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
281 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
282 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
283 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
284 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
287 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
288 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
289 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
290 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
291 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
292 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
293 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
294 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
295 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
296 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
297 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
298 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
305 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
306 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
313 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
314 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
320 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
321 0x024 (PIN_OUTPUT | MUX_MODE1)
322 0x028 (PIN_OUTPUT | MUX_MODE1)
323 0x02c (PIN_OUTPUT | MUX_MODE1)
324 0x030 (PIN_OUTPUT | MUX_MODE1)
325 0x034 (PIN_OUTPUT | MUX_MODE1)
326 0x038 (PIN_OUTPUT | MUX_MODE1)
327 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
328 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
329 0x0a4 (PIN_OUTPUT | MUX_MODE0)
330 0x0a8 (PIN_OUTPUT | MUX_MODE0)
331 0x0ac (PIN_OUTPUT | MUX_MODE0)
332 0x0b0 (PIN_OUTPUT | MUX_MODE0)
333 0x0b4 (PIN_OUTPUT | MUX_MODE0)
334 0x0b8 (PIN_OUTPUT | MUX_MODE0)
335 0x0bc (PIN_OUTPUT | MUX_MODE0)
336 0x0c0 (PIN_OUTPUT | MUX_MODE0)
337 0x0c4 (PIN_OUTPUT | MUX_MODE0)
338 0x0c8 (PIN_OUTPUT | MUX_MODE0)
339 0x0cc (PIN_OUTPUT | MUX_MODE0)
340 0x0d0 (PIN_OUTPUT | MUX_MODE0)
341 0x0d4 (PIN_OUTPUT | MUX_MODE0)
342 0x0d8 (PIN_OUTPUT | MUX_MODE0)
343 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
344 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
345 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
346 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
347 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
354 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
355 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
356 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
357 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
358 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
359 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
365 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
366 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
367 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
368 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
374 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
380 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
386 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
394 pinctrl-0 = <&i2c0_pins>;
399 reg = <0x24>;
461 reg = <0x50>;
468 pinctrl-0 = <&i2c1_pins>;
475 pinctrl-0 = <&edt_ft5306_ts_pins>;
477 reg = <0x38>;
479 interrupts = <31 0>;
489 reg = <0x1b>;
501 reg = <0x18>;
506 interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
517 pinctrl-0 = <&ecap0_pins>;
535 pinctrl-0 = <&mmc1_pins>;
550 pinctrl-0 = <&usb1_pins>;
561 pinctrl-0 = <&usb2_pins>;
567 pinctrl-0 = <&qspi_pins>;
570 m25p80@0 {
573 reg = <0>;
585 partition@0 {
587 reg = <0x00000000 0x000080000>;
591 reg = <0x00080000 0x00080000>;
595 reg = <0x00100000 0x00010000>;
599 reg = <0x00110000 0x00010000>;
603 reg = <0x00120000 0x00010000>;
607 reg = <0x00130000 0x0800000>;
611 reg = <0x00930000 0x36D0000>;
618 pinctrl-0 = <&cpsw_default>;
626 pinctrl-0 = <&davinci_mdio_default>;
649 pinctrl-0 = <&mcasp1_pins>;
653 op-mode = <0>;
656 0 0 1 2
667 pinctrl-0 = <&dss_pins>;
670 dpi_out: endpoint@0 {
692 pinctrl-0 = <&vpfe0_pins_default>;
699 ti,am437x-vpfe-interface = <0>;
701 hsync-active = <0>;
702 vsync-active = <0>;