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/openbmc/linux/arch/arm/mach-omap2/
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
H A Dprcm_mpu44xx.h27 #define OMAP4430_PRCM_MPU_BASE 0x48243000
33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
53 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
54 … OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
[all …]
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
/openbmc/u-boot/include/
H A Dlxt971a.h18 #define PHY_LXT971_PORT_CFG (0x10)
19 #define PHY_LXT971_STAT2 (0x11)
20 #define PHY_LXT971_INT_ENABLE (0x12)
21 #define PHY_LXT971_INT_STATUS (0x13)
22 #define PHY_LXT971_LED_CFG (0x14)
23 #define PHY_LXT971_DIG_CFG (0x1A)
24 #define PHY_LXT971_TX_CTRL (0x1E)
27 #define PHY_LXT971_PORT_CFG_RES1 (0x8000)
28 #define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
29 #define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
[all …]
H A Dgdsys_fpga.h13 FPGA_STATE_DONE_FAILED = 1 << 0,
80 u16 reflection_low; /* 0x0000 */
81 u16 versions; /* 0x0002 */
82 u16 fpga_features; /* 0x0004 */
83 u16 fpga_version; /* 0x0006 */
84 u16 reserved_0[8187]; /* 0x0008 */
85 u16 reflection_high; /* 0x3ffe */
91 u16 reflection_low; /* 0x0000 */
92 u16 versions; /* 0x0002 */
93 u16 fpga_features; /* 0x0004 */
[all …]
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dsgtl5000.h14 #define SGTL5000_CHIP_ID 0x0000
15 #define SGTL5000_CHIP_DIG_POWER 0x0002
16 #define SGTL5000_CHIP_CLK_CTRL 0x0004
17 #define SGTL5000_CHIP_I2S_CTRL 0x0006
18 #define SGTL5000_CHIP_SSS_CTRL 0x000a
19 #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
20 #define SGTL5000_CHIP_DAC_VOL 0x0010
21 #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
22 #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
23 #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/openbmc/linux/include/linux/
H A Dmicrochipphy.h9 #define LAN88XX_INT_MASK (0x19)
10 #define LAN88XX_INT_MASK_MDINTPIN_EN_ (0x8000)
11 #define LAN88XX_INT_MASK_SPEED_CHANGE_ (0x4000)
12 #define LAN88XX_INT_MASK_LINK_CHANGE_ (0x2000)
13 #define LAN88XX_INT_MASK_FDX_CHANGE_ (0x1000)
14 #define LAN88XX_INT_MASK_AUTONEG_ERR_ (0x0800)
15 #define LAN88XX_INT_MASK_AUTONEG_DONE_ (0x0400)
16 #define LAN88XX_INT_MASK_POE_DETECT_ (0x0200)
17 #define LAN88XX_INT_MASK_SYMBOL_ERR_ (0x0100)
18 #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ (0x0080)
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dspca501.c29 #define Arowana300KCMOSCamera 0
53 .priv = 0},
56 #define SPCA50X_REG_USB 0x2 /* spca505 501 */
65 #define SPCA501_SNAPBIT 0x80
66 #define SPCA501_SNAPCTRL 0x10
78 #define SPCA501_PROP_SNAP(d) ((d) & 0x40)
79 #define SPCA501_PROP_SNAP_CTRL(d) ((d) & 0x10)
80 #define SPCA501_PROP_COMP_THRESH(d) (((d) & 0x0e) >> 1)
81 #define SPCA501_PROP_COMP_QUANT(d) (((d) & 0x70) >> 4)
84 #define SPCA501_REG_CCDSP 0x01
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG11 0x28
41 #define PHYREG11_SU_TRIM_0_7 0xF0
43 #define PHYREG12 0x2C
46 #define PHYREG13 0x3
[all...]
/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-v0-regs.h15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
[all …]
/openbmc/linux/include/linux/mfd/
H A Dlochnagar1_regs.h15 #define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
16 #define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
17 #define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
18 #define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
19 #define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
20 #define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
21 #define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
22 #define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
23 #define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
24 #define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
[all …]
H A Didt8a340_reg.h3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7785.c70 [DIV4_P] = DIV4(0, 0x0f80, 0),
71 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
72 [DIV4_GA] = DIV4(8, 0x0030, 0),
73 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
74 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
80 #define MSTPCR0 0xffc80030
81 #define MSTPCR1 0xffc80034
[all …]
/openbmc/qemu/include/hw/usb/
H A Dehci-regs.h5 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
6 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
7 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */
8 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */
10 #define HCSPPORTROUTE1 0x000c
11 #define HCSPPORTROUTE2 0x0010
13 #define USBCMD 0x0000
14 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
24 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
27 #define USBSTS 0x0004
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm21664.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
33 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
34 .hyst = HYST(0x0414, 8, 9),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
45 .enable = CCU_LVM_EN(0x0034, 0),
46 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
58 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
64 .sel = SELECTOR(0x0a28, 0, 3),
65 .div = DIVIDER(0x0a28, 4, 14),
[all …]
/openbmc/linux/drivers/dma/ptdma/
H A Dptdma.h36 #define IRQ_MASK_REG 0x040
37 #define IRQ_STATUS_REG 0x200
39 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
41 #define CMD_QUEUE_PRIO_OFFSET 0x00
42 #define CMD_REQID_CONFIG_OFFSET 0x04
43 #define CMD_TIMEOUT_OFFSET 0x08
44 #define CMD_PT_VERSION 0x10
46 #define CMD_Q_CONTROL_BASE 0x0000
47 #define CMD_Q_TAIL_LO_BASE 0x0004
48 #define CMD_Q_HEAD_LO_BASE 0x0008
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp-pinfunc.h26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
[all …]
/openbmc/linux/net/bluetooth/
H A Dmgmt_config.c82 TLV_SET_U16(0x0000, def_page_scan_type), in read_def_system_config()
83 TLV_SET_U16(0x0001, def_page_scan_int), in read_def_system_config()
84 TLV_SET_U16(0x0002, def_page_scan_window), in read_def_system_config()
85 TLV_SET_U16(0x0003, def_inq_scan_type), in read_def_system_config()
86 TLV_SET_U16(0x0004, def_inq_scan_int), in read_def_system_config()
87 TLV_SET_U16(0x0005, def_inq_scan_window), in read_def_system_config()
88 TLV_SET_U16(0x0006, def_br_lsto), in read_def_system_config()
89 TLV_SET_U16(0x0007, def_page_timeout), in read_def_system_config()
90 TLV_SET_U16(0x0008, sniff_min_interval), in read_def_system_config()
91 TLV_SET_U16(0x0009, sniff_max_interval), in read_def_system_config()
[all …]
/openbmc/linux/include/acpi/
H A Dacexcep.h18 #define AE_CODE_ENVIRONMENTAL 0x0000 /* General ACPICA environment */
19 #define AE_CODE_PROGRAMMER 0x1000 /* External ACPICA interface caller */
20 #define AE_CODE_ACPI_TABLES 0x2000 /* ACPI tables */
21 #define AE_CODE_AML 0x3000 /* From executing AML code */
22 #define AE_CODE_CONTROL 0x4000 /* Internal control codes */
24 #define AE_CODE_MAX 0x4000
25 #define AE_CODE_MASK 0xF000
60 #define AE_OK (acpi_status) 0x0000
71 #define AE_ERROR EXCEP_ENV (0x0001)
72 #define AE_NO_ACPI_TABLES EXCEP_ENV (0x0002)
[all …]
/openbmc/linux/include/scsi/fc/
H A Dfc_ms.h25 #define FC_FDMI_SUBTYPE 0x10 /* fs_ct_hdr.ct_fs_subtype */
37 FC_FDMI_GRHL = 0x0100, /* Get Registered HBA List */
38 FC_FDMI_GHAT = 0x0101, /* Get HBA Attributes */
39 FC_FDMI_GRPL = 0x0102, /* Get Registered Port List */
40 FC_FDMI_GPAT = 0x0110, /* Get Port Attributes */
41 FC_FDMI_RHBA = 0x0200, /* Register HBA */
42 FC_FDMI_RHAT = 0x0201, /* Register HBA Attributes */
43 FC_FDMI_RPRT = 0x0210, /* Register Port */
44 FC_FDMI_RPA = 0x0211, /* Register Port Attributes */
45 FC_FDMI_DHBA = 0x0300, /* Deregister HBA */
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dcarminefb_regs.h5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x00)
[all …]

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