1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22da0fc0dSDirk Eibach /* 32da0fc0dSDirk Eibach * (C) Copyright 2010 4d38826a3SMario Six * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 52da0fc0dSDirk Eibach */ 62da0fc0dSDirk Eibach 72da0fc0dSDirk Eibach #ifndef __GDSYS_FPGA_H 82da0fc0dSDirk Eibach #define __GDSYS_FPGA_H 92da0fc0dSDirk Eibach 10255ef4d9SDirk Eibach int init_func_fpga(void); 11255ef4d9SDirk Eibach 122da0fc0dSDirk Eibach enum { 132da0fc0dSDirk Eibach FPGA_STATE_DONE_FAILED = 1 << 0, 142da0fc0dSDirk Eibach FPGA_STATE_REFLECTION_FAILED = 1 << 1, 15255ef4d9SDirk Eibach FPGA_STATE_PLATFORM = 1 << 2, 162da0fc0dSDirk Eibach }; 172da0fc0dSDirk Eibach 182da0fc0dSDirk Eibach int get_fpga_state(unsigned dev); 192da0fc0dSDirk Eibach 20aba27acfSDirk Eibach int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); 21aba27acfSDirk Eibach int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); 22aba27acfSDirk Eibach 23aba27acfSDirk Eibach extern struct ihs_fpga *fpga_ptr[]; 24aba27acfSDirk Eibach 25aba27acfSDirk Eibach #define FPGA_SET_REG(ix, fld, val) \ 26aba27acfSDirk Eibach fpga_set_reg((ix), \ 27aba27acfSDirk Eibach &fpga_ptr[ix]->fld, \ 28aba27acfSDirk Eibach offsetof(struct ihs_fpga, fld), \ 29aba27acfSDirk Eibach val) 30aba27acfSDirk Eibach 31aba27acfSDirk Eibach #define FPGA_GET_REG(ix, fld, val) \ 32aba27acfSDirk Eibach fpga_get_reg((ix), \ 33aba27acfSDirk Eibach &fpga_ptr[ix]->fld, \ 34aba27acfSDirk Eibach offsetof(struct ihs_fpga, fld), \ 35aba27acfSDirk Eibach val) 36aba27acfSDirk Eibach 370e60aa85SDirk Eibach struct ihs_gpio { 382da0fc0dSDirk Eibach u16 read; 392da0fc0dSDirk Eibach u16 clear; 402da0fc0dSDirk Eibach u16 set; 410e60aa85SDirk Eibach }; 422da0fc0dSDirk Eibach 430e60aa85SDirk Eibach struct ihs_i2c { 44b46226bdSDirk Eibach u16 interrupt_status; 45b46226bdSDirk Eibach u16 interrupt_enable; 462da0fc0dSDirk Eibach u16 write_mailbox_ext; 47b46226bdSDirk Eibach u16 write_mailbox; 482da0fc0dSDirk Eibach u16 read_mailbox_ext; 49b46226bdSDirk Eibach u16 read_mailbox; 500e60aa85SDirk Eibach }; 512da0fc0dSDirk Eibach 520e60aa85SDirk Eibach struct ihs_osd { 532da0fc0dSDirk Eibach u16 version; 542da0fc0dSDirk Eibach u16 features; 552da0fc0dSDirk Eibach u16 control; 562da0fc0dSDirk Eibach u16 xy_size; 5752158e36SDirk Eibach u16 xy_scale; 5852158e36SDirk Eibach u16 x_pos; 5952158e36SDirk Eibach u16 y_pos; 600e60aa85SDirk Eibach }; 612da0fc0dSDirk Eibach 6250dcf89dSDirk Eibach struct ihs_mdio { 6350dcf89dSDirk Eibach u16 control; 6450dcf89dSDirk Eibach u16 address_data; 6550dcf89dSDirk Eibach u16 rx_data; 6650dcf89dSDirk Eibach }; 6750dcf89dSDirk Eibach 6850dcf89dSDirk Eibach struct ihs_io_ep { 6950dcf89dSDirk Eibach u16 transmit_data; 7050dcf89dSDirk Eibach u16 rx_tx_control; 7150dcf89dSDirk Eibach u16 receive_data; 7250dcf89dSDirk Eibach u16 rx_tx_status; 7350dcf89dSDirk Eibach u16 reserved; 7450dcf89dSDirk Eibach u16 device_address; 7550dcf89dSDirk Eibach u16 target_address; 7650dcf89dSDirk Eibach }; 7750dcf89dSDirk Eibach 786e9e6c36SDirk Eibach #ifdef CONFIG_NEO 790e60aa85SDirk Eibach struct ihs_fpga { 806e9e6c36SDirk Eibach u16 reflection_low; /* 0x0000 */ 816e9e6c36SDirk Eibach u16 versions; /* 0x0002 */ 826e9e6c36SDirk Eibach u16 fpga_features; /* 0x0004 */ 836e9e6c36SDirk Eibach u16 fpga_version; /* 0x0006 */ 846e9e6c36SDirk Eibach u16 reserved_0[8187]; /* 0x0008 */ 856e9e6c36SDirk Eibach u16 reflection_high; /* 0x3ffe */ 860e60aa85SDirk Eibach }; 876e9e6c36SDirk Eibach #endif 886e9e6c36SDirk Eibach 892da0fc0dSDirk Eibach #ifdef CONFIG_IO 900e60aa85SDirk Eibach struct ihs_fpga { 912da0fc0dSDirk Eibach u16 reflection_low; /* 0x0000 */ 922da0fc0dSDirk Eibach u16 versions; /* 0x0002 */ 932da0fc0dSDirk Eibach u16 fpga_features; /* 0x0004 */ 942da0fc0dSDirk Eibach u16 fpga_version; /* 0x0006 */ 952da0fc0dSDirk Eibach u16 reserved_0[5]; /* 0x0008 */ 962da0fc0dSDirk Eibach u16 quad_serdes_reset; /* 0x0012 */ 972da0fc0dSDirk Eibach u16 reserved_1[8181]; /* 0x0014 */ 982da0fc0dSDirk Eibach u16 reflection_high; /* 0x3ffe */ 990e60aa85SDirk Eibach }; 1002da0fc0dSDirk Eibach #endif 1012da0fc0dSDirk Eibach 102255ef4d9SDirk Eibach #ifdef CONFIG_IO64 103aba27acfSDirk Eibach struct ihs_fpga_channel { 104aba27acfSDirk Eibach u16 status_int; 105aba27acfSDirk Eibach u16 config_int; 106aba27acfSDirk Eibach u16 switch_connect_config; 107aba27acfSDirk Eibach u16 tx_destination; 108aba27acfSDirk Eibach }; 109aba27acfSDirk Eibach 110aba27acfSDirk Eibach struct ihs_fpga_hicb { 111aba27acfSDirk Eibach u16 status_int; 112aba27acfSDirk Eibach u16 config_int; 113aba27acfSDirk Eibach }; 114aba27acfSDirk Eibach 1150e60aa85SDirk Eibach struct ihs_fpga { 116255ef4d9SDirk Eibach u16 reflection_low; /* 0x0000 */ 117255ef4d9SDirk Eibach u16 versions; /* 0x0002 */ 118255ef4d9SDirk Eibach u16 fpga_features; /* 0x0004 */ 119255ef4d9SDirk Eibach u16 fpga_version; /* 0x0006 */ 120255ef4d9SDirk Eibach u16 reserved_0[5]; /* 0x0008 */ 121255ef4d9SDirk Eibach u16 quad_serdes_reset; /* 0x0012 */ 122255ef4d9SDirk Eibach u16 reserved_1[502]; /* 0x0014 */ 123aba27acfSDirk Eibach struct ihs_fpga_channel ch[32]; /* 0x0400 */ 124aba27acfSDirk Eibach struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */ 125aba27acfSDirk Eibach u16 reserved_2[7487]; /* 0x0580 */ 126255ef4d9SDirk Eibach u16 reflection_high; /* 0x3ffe */ 1270e60aa85SDirk Eibach }; 128255ef4d9SDirk Eibach #endif 129255ef4d9SDirk Eibach 1302da0fc0dSDirk Eibach #ifdef CONFIG_IOCON 1310e60aa85SDirk Eibach struct ihs_fpga { 1322da0fc0dSDirk Eibach u16 reflection_low; /* 0x0000 */ 1332da0fc0dSDirk Eibach u16 versions; /* 0x0002 */ 1342da0fc0dSDirk Eibach u16 fpga_version; /* 0x0004 */ 1352da0fc0dSDirk Eibach u16 fpga_features; /* 0x0006 */ 13650dcf89dSDirk Eibach u16 reserved_0[1]; /* 0x0008 */ 13750dcf89dSDirk Eibach u16 top_interrupt; /* 0x000a */ 13850dcf89dSDirk Eibach u16 reserved_1[4]; /* 0x000c */ 1390e60aa85SDirk Eibach struct ihs_gpio gpio; /* 0x0014 */ 1402da0fc0dSDirk Eibach u16 mpc3w_control; /* 0x001a */ 14150dcf89dSDirk Eibach u16 reserved_2[2]; /* 0x001c */ 14250dcf89dSDirk Eibach struct ihs_io_ep ep; /* 0x0020 */ 14350dcf89dSDirk Eibach u16 reserved_3[9]; /* 0x002e */ 144071be896SDirk Eibach struct ihs_i2c i2c0; /* 0x0040 */ 14550dcf89dSDirk Eibach u16 reserved_4[10]; /* 0x004c */ 146e50e8968SDirk Eibach u16 mc_int; /* 0x0060 */ 147e50e8968SDirk Eibach u16 mc_int_en; /* 0x0062 */ 148e50e8968SDirk Eibach u16 mc_status; /* 0x0064 */ 149e50e8968SDirk Eibach u16 mc_control; /* 0x0066 */ 150e50e8968SDirk Eibach u16 mc_tx_data; /* 0x0068 */ 151e50e8968SDirk Eibach u16 mc_tx_address; /* 0x006a */ 152e50e8968SDirk Eibach u16 mc_tx_cmd; /* 0x006c */ 153e50e8968SDirk Eibach u16 mc_res; /* 0x006e */ 154e50e8968SDirk Eibach u16 mc_rx_cmd_status; /* 0x0070 */ 155e50e8968SDirk Eibach u16 mc_rx_data; /* 0x0072 */ 15650dcf89dSDirk Eibach u16 reserved_5[69]; /* 0x0074 */ 1572da0fc0dSDirk Eibach u16 reflection_high; /* 0x00fe */ 1587ed45d3dSDirk Eibach struct ihs_osd osd0; /* 0x0100 */ 15950dcf89dSDirk Eibach u16 reserved_6[889]; /* 0x010e */ 1607ed45d3dSDirk Eibach u16 videomem0[2048]; /* 0x0800 */ 16150dcf89dSDirk Eibach }; 16250dcf89dSDirk Eibach #endif 16350dcf89dSDirk Eibach 1641d2541baSDirk Eibach #if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP) 16550dcf89dSDirk Eibach struct ihs_fpga { 16650dcf89dSDirk Eibach u16 reflection_low; /* 0x0000 */ 16750dcf89dSDirk Eibach u16 versions; /* 0x0002 */ 16850dcf89dSDirk Eibach u16 fpga_version; /* 0x0004 */ 16950dcf89dSDirk Eibach u16 fpga_features; /* 0x0006 */ 17050dcf89dSDirk Eibach u16 reserved_0[1]; /* 0x0008 */ 17150dcf89dSDirk Eibach u16 top_interrupt; /* 0x000a */ 1727ed45d3dSDirk Eibach u16 reserved_1[2]; /* 0x000c */ 1737ed45d3dSDirk Eibach u16 control; /* 0x0010 */ 1747ed45d3dSDirk Eibach u16 extended_control; /* 0x0012 */ 17550dcf89dSDirk Eibach struct ihs_gpio gpio; /* 0x0014 */ 17650dcf89dSDirk Eibach u16 mpc3w_control; /* 0x001a */ 17750dcf89dSDirk Eibach u16 reserved_2[2]; /* 0x001c */ 17850dcf89dSDirk Eibach struct ihs_io_ep ep; /* 0x0020 */ 17950dcf89dSDirk Eibach u16 reserved_3[9]; /* 0x002e */ 180071be896SDirk Eibach struct ihs_i2c i2c0; /* 0x0040 */ 18150dcf89dSDirk Eibach u16 reserved_4[10]; /* 0x004c */ 18250dcf89dSDirk Eibach u16 mc_int; /* 0x0060 */ 18350dcf89dSDirk Eibach u16 mc_int_en; /* 0x0062 */ 18450dcf89dSDirk Eibach u16 mc_status; /* 0x0064 */ 18550dcf89dSDirk Eibach u16 mc_control; /* 0x0066 */ 18650dcf89dSDirk Eibach u16 mc_tx_data; /* 0x0068 */ 18750dcf89dSDirk Eibach u16 mc_tx_address; /* 0x006a */ 18850dcf89dSDirk Eibach u16 mc_tx_cmd; /* 0x006c */ 18950dcf89dSDirk Eibach u16 mc_res; /* 0x006e */ 19050dcf89dSDirk Eibach u16 mc_rx_cmd_status; /* 0x0070 */ 19150dcf89dSDirk Eibach u16 mc_rx_data; /* 0x0072 */ 19250dcf89dSDirk Eibach u16 reserved_5[69]; /* 0x0074 */ 19350dcf89dSDirk Eibach u16 reflection_high; /* 0x00fe */ 1947ed45d3dSDirk Eibach struct ihs_osd osd0; /* 0x0100 */ 1957ed45d3dSDirk Eibach #ifdef CONFIG_SYS_OSD_DH 1967ed45d3dSDirk Eibach u16 reserved_6[57]; /* 0x010e */ 1977ed45d3dSDirk Eibach struct ihs_osd osd1; /* 0x0180 */ 1987ed45d3dSDirk Eibach u16 reserved_7[9]; /* 0x018e */ 1997ed45d3dSDirk Eibach struct ihs_i2c i2c1; /* 0x01a0 */ 2007ed45d3dSDirk Eibach u16 reserved_8[1834]; /* 0x01ac */ 2017ed45d3dSDirk Eibach u16 videomem0[2048]; /* 0x1000 */ 2027ed45d3dSDirk Eibach u16 videomem1[2048]; /* 0x2000 */ 2037ed45d3dSDirk Eibach #else 20450dcf89dSDirk Eibach u16 reserved_6[889]; /* 0x010e */ 2057ed45d3dSDirk Eibach u16 videomem0[2048]; /* 0x0800 */ 2067ed45d3dSDirk Eibach #endif 2070e60aa85SDirk Eibach }; 2082da0fc0dSDirk Eibach #endif 2092da0fc0dSDirk Eibach 210a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CPU 211a3f9d6c7SDirk Eibach struct ihs_fpga { 212a3f9d6c7SDirk Eibach u16 reflection_low; /* 0x0000 */ 213a3f9d6c7SDirk Eibach u16 versions; /* 0x0002 */ 214a3f9d6c7SDirk Eibach u16 fpga_version; /* 0x0004 */ 215a3f9d6c7SDirk Eibach u16 fpga_features; /* 0x0006 */ 216a3f9d6c7SDirk Eibach u16 reserved_0[1]; /* 0x0008 */ 217a3f9d6c7SDirk Eibach u16 top_interrupt; /* 0x000a */ 218a3f9d6c7SDirk Eibach u16 reserved_1[3]; /* 0x000c */ 219a3f9d6c7SDirk Eibach u16 extended_control; /* 0x0012 */ 220a3f9d6c7SDirk Eibach struct ihs_gpio gpio; /* 0x0014 */ 221a3f9d6c7SDirk Eibach u16 mpc3w_control; /* 0x001a */ 222a3f9d6c7SDirk Eibach u16 reserved_2[2]; /* 0x001c */ 223a3f9d6c7SDirk Eibach struct ihs_io_ep ep; /* 0x0020 */ 224a3f9d6c7SDirk Eibach u16 reserved_3[9]; /* 0x002e */ 225a3f9d6c7SDirk Eibach u16 mc_int; /* 0x0040 */ 226a3f9d6c7SDirk Eibach u16 mc_int_en; /* 0x0042 */ 227a3f9d6c7SDirk Eibach u16 mc_status; /* 0x0044 */ 228a3f9d6c7SDirk Eibach u16 mc_control; /* 0x0046 */ 229a3f9d6c7SDirk Eibach u16 mc_tx_data; /* 0x0048 */ 230a3f9d6c7SDirk Eibach u16 mc_tx_address; /* 0x004a */ 231a3f9d6c7SDirk Eibach u16 mc_tx_cmd; /* 0x004c */ 232a3f9d6c7SDirk Eibach u16 mc_res; /* 0x004e */ 233a3f9d6c7SDirk Eibach u16 mc_rx_cmd_status; /* 0x0050 */ 234a3f9d6c7SDirk Eibach u16 mc_rx_data; /* 0x0052 */ 235a3f9d6c7SDirk Eibach u16 reserved_4[62]; /* 0x0054 */ 236a3f9d6c7SDirk Eibach struct ihs_i2c i2c0; /* 0x00d0 */ 237a3f9d6c7SDirk Eibach }; 238a3f9d6c7SDirk Eibach #endif 239a3f9d6c7SDirk Eibach 240a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 241a3f9d6c7SDirk Eibach struct ihs_fpga { 242a3f9d6c7SDirk Eibach u16 reflection_low; /* 0x0000 */ 243a3f9d6c7SDirk Eibach u16 versions; /* 0x0002 */ 244a3f9d6c7SDirk Eibach u16 fpga_version; /* 0x0004 */ 245a3f9d6c7SDirk Eibach u16 fpga_features; /* 0x0006 */ 246a3f9d6c7SDirk Eibach u16 reserved_0[1]; /* 0x0008 */ 247a3f9d6c7SDirk Eibach u16 top_interrupt; /* 0x000a */ 248a3f9d6c7SDirk Eibach u16 reserved_1[4]; /* 0x000c */ 249a3f9d6c7SDirk Eibach struct ihs_gpio gpio; /* 0x0014 */ 250a3f9d6c7SDirk Eibach u16 mpc3w_control; /* 0x001a */ 251a3f9d6c7SDirk Eibach u16 reserved_2[2]; /* 0x001c */ 252a3f9d6c7SDirk Eibach struct ihs_io_ep ep; /* 0x0020 */ 253a3f9d6c7SDirk Eibach u16 reserved_3[9]; /* 0x002e */ 254a3f9d6c7SDirk Eibach struct ihs_i2c i2c0; /* 0x0040 */ 255a3f9d6c7SDirk Eibach u16 reserved_4[10]; /* 0x004c */ 256a3f9d6c7SDirk Eibach u16 mc_int; /* 0x0060 */ 257a3f9d6c7SDirk Eibach u16 mc_int_en; /* 0x0062 */ 258a3f9d6c7SDirk Eibach u16 mc_status; /* 0x0064 */ 259a3f9d6c7SDirk Eibach u16 mc_control; /* 0x0066 */ 260a3f9d6c7SDirk Eibach u16 mc_tx_data; /* 0x0068 */ 261a3f9d6c7SDirk Eibach u16 mc_tx_address; /* 0x006a */ 262a3f9d6c7SDirk Eibach u16 mc_tx_cmd; /* 0x006c */ 263a3f9d6c7SDirk Eibach u16 mc_res; /* 0x006e */ 264a3f9d6c7SDirk Eibach u16 mc_rx_cmd_status; /* 0x0070 */ 265a3f9d6c7SDirk Eibach u16 mc_rx_data; /* 0x0072 */ 266a3f9d6c7SDirk Eibach u16 reserved_5[70]; /* 0x0074 */ 2677ed45d3dSDirk Eibach struct ihs_osd osd0; /* 0x0100 */ 268a3f9d6c7SDirk Eibach u16 reserved_6[889]; /* 0x010e */ 2697ed45d3dSDirk Eibach u16 videomem0[2048]; /* 0x0800 */ 270a3f9d6c7SDirk Eibach }; 271a3f9d6c7SDirk Eibach #endif 272a3f9d6c7SDirk Eibach 2732da0fc0dSDirk Eibach #ifdef CONFIG_DLVISION_10G 2740e60aa85SDirk Eibach struct ihs_fpga { 2752da0fc0dSDirk Eibach u16 reflection_low; /* 0x0000 */ 2762da0fc0dSDirk Eibach u16 versions; /* 0x0002 */ 2772da0fc0dSDirk Eibach u16 fpga_version; /* 0x0004 */ 2782da0fc0dSDirk Eibach u16 fpga_features; /* 0x0006 */ 2792da0fc0dSDirk Eibach u16 reserved_0[10]; /* 0x0008 */ 2802da0fc0dSDirk Eibach u16 extended_interrupt; /* 0x001c */ 281b46226bdSDirk Eibach u16 reserved_1[29]; /* 0x001e */ 2827749c84eSDirk Eibach u16 mpc3w_control; /* 0x0058 */ 283b46226bdSDirk Eibach u16 reserved_2[3]; /* 0x005a */ 284071be896SDirk Eibach struct ihs_i2c i2c0; /* 0x0060 */ 285071be896SDirk Eibach u16 reserved_3[2]; /* 0x006c */ 286071be896SDirk Eibach struct ihs_i2c i2c1; /* 0x0070 */ 287071be896SDirk Eibach u16 reserved_4[194]; /* 0x007c */ 2887ed45d3dSDirk Eibach struct ihs_osd osd0; /* 0x0200 */ 289071be896SDirk Eibach u16 reserved_5[761]; /* 0x020e */ 2907ed45d3dSDirk Eibach u16 videomem0[2048]; /* 0x0800 */ 2910e60aa85SDirk Eibach }; 2922da0fc0dSDirk Eibach #endif 2932da0fc0dSDirk Eibach 2942da0fc0dSDirk Eibach #endif 295