1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2429168eaSwdenk /*********************************************************************** 3429168eaSwdenk * 4429168eaSwdenk * Copyright (C) 2004 by FS Forth-Systeme GmbH. 5429168eaSwdenk * All rights reserved. 6429168eaSwdenk * 7429168eaSwdenk * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ 8429168eaSwdenk * @Author: Markus Pietrek 9429168eaSwdenk * @References: [1] NS9750 Hardware Reference, December 2003 10429168eaSwdenk * [2] Intel LXT971 Datasheet #249414 Rev. 02 11429168eaSwdenk * [3] NS7520 Linux Ethernet Driver 121a459660SWolfgang Denk */ 13429168eaSwdenk 14429168eaSwdenk #ifndef __LXT971A_H__ 15429168eaSwdenk #define __LXT971A_H__ 16429168eaSwdenk 17429168eaSwdenk /* PHY definitions (LXT971A) [2] */ 18429168eaSwdenk #define PHY_LXT971_PORT_CFG (0x10) 19429168eaSwdenk #define PHY_LXT971_STAT2 (0x11) 20429168eaSwdenk #define PHY_LXT971_INT_ENABLE (0x12) 21429168eaSwdenk #define PHY_LXT971_INT_STATUS (0x13) 22429168eaSwdenk #define PHY_LXT971_LED_CFG (0x14) 23429168eaSwdenk #define PHY_LXT971_DIG_CFG (0x1A) 24429168eaSwdenk #define PHY_LXT971_TX_CTRL (0x1E) 25429168eaSwdenk 26429168eaSwdenk /* PORT_CFG Port Configuration Register Bit Fields */ 27429168eaSwdenk #define PHY_LXT971_PORT_CFG_RES1 (0x8000) 28429168eaSwdenk #define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) 29429168eaSwdenk #define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000) 30429168eaSwdenk #define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000) 31429168eaSwdenk #define PHY_LXT971_PORT_CFG_RES2 (0x0800) 32429168eaSwdenk #define PHY_LXT971_PORT_CFG_JABBER (0x0400) 33429168eaSwdenk #define PHY_LXT971_PORT_CFG_SQE (0x0200) 34429168eaSwdenk #define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100) 35429168eaSwdenk #define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080) 36429168eaSwdenk #define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040) 37429168eaSwdenk #define PHY_LXT971_PORT_CFG_PRE_EN (0x0020) 38429168eaSwdenk #define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018) 39429168eaSwdenk #define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010) 40429168eaSwdenk #define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001) 41429168eaSwdenk #define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000) 42429168eaSwdenk #define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004) 43429168eaSwdenk #define PHY_LXT971_PORT_CFG_ALT_NP (0x0002) 44429168eaSwdenk #define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001) 45429168eaSwdenk 46429168eaSwdenk /* STAT2 Status Register #2 Bit Fields */ 47429168eaSwdenk #define PHY_LXT971_STAT2_RES1 (0x8000) 48429168eaSwdenk #define PHY_LXT971_STAT2_100BTX (0x4000) 49429168eaSwdenk #define PHY_LXT971_STAT2_TX_STATUS (0x2000) 50429168eaSwdenk #define PHY_LXT971_STAT2_RX_STATUS (0x1000) 51429168eaSwdenk #define PHY_LXT971_STAT2_COL_STATUS (0x0800) 52429168eaSwdenk #define PHY_LXT971_STAT2_LINK (0x0400) 53429168eaSwdenk #define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200) 54429168eaSwdenk #define PHY_LXT971_STAT2_AUTO_NEG (0x0100) 55429168eaSwdenk #define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080) 56429168eaSwdenk #define PHY_LXT971_STAT2_RES2 (0x0040) 57429168eaSwdenk #define PHY_LXT971_STAT2_POLARITY (0x0020) 58429168eaSwdenk #define PHY_LXT971_STAT2_PAUSE (0x0010) 59429168eaSwdenk #define PHY_LXT971_STAT2_ERROR (0x0008) 60429168eaSwdenk #define PHY_LXT971_STAT2_RES3 (0x0007) 61429168eaSwdenk 62429168eaSwdenk /* INT_ENABLE Interrupt Enable Register Bit Fields */ 63429168eaSwdenk #define PHY_LXT971_INT_ENABLE_RES1 (0xFF00) 64429168eaSwdenk #define PHY_LXT971_INT_ENABLE_ANMSK (0x0080) 65429168eaSwdenk #define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040) 66429168eaSwdenk #define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020) 67429168eaSwdenk #define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010) 68429168eaSwdenk #define PHY_LXT971_INT_ENABLE_RES2 (0x000C) 69429168eaSwdenk #define PHY_LXT971_INT_ENABLE_INTEN (0x0002) 70429168eaSwdenk #define PHY_LXT971_INT_ENABLE_TINT (0x0001) 71429168eaSwdenk 72429168eaSwdenk /* INT_STATUS Interrupt Status Register Bit Fields */ 73429168eaSwdenk #define PHY_LXT971_INT_STATUS_RES1 (0xFF00) 74429168eaSwdenk #define PHY_LXT971_INT_STATUS_ANDONE (0x0080) 75429168eaSwdenk #define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040) 76429168eaSwdenk #define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020) 77429168eaSwdenk #define PHY_LXT971_INT_STATUS_LINKCHG (0x0010) 78429168eaSwdenk #define PHY_LXT971_INT_STATUS_RES2 (0x0008) 79429168eaSwdenk #define PHY_LXT971_INT_STATUS_MDINT (0x0004) 80429168eaSwdenk #define PHY_LXT971_INT_STATUS_RES3 (0x0003) 81429168eaSwdenk 82429168eaSwdenk /* LED_CFG Interrupt LED Configuration Register Bit Fields */ 83429168eaSwdenk #define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C) 84429168eaSwdenk #define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008) 85429168eaSwdenk #define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004) 86429168eaSwdenk #define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C) 87429168eaSwdenk #define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C) 88429168eaSwdenk #define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008) 89429168eaSwdenk #define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004) 90429168eaSwdenk #define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000) 91429168eaSwdenk #define PHY_LXT971_LED_CFG_PULSE_STR (0x0002) 92429168eaSwdenk #define PHY_LXT971_LED_CFG_RES1 (0x0001) 93429168eaSwdenk 94429168eaSwdenk /* only one of these values must be shifted for each SHIFT_LED? */ 95429168eaSwdenk #define PHY_LXT971_LED_CFG_UNUSED1 (0x000F) 96429168eaSwdenk #define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E) 97429168eaSwdenk #define PHY_LXT971_LED_CFG_LINK_ACT (0x000D) 98429168eaSwdenk #define PHY_LXT971_LED_CFG_LINK_RX (0x000C) 99429168eaSwdenk #define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B) 100429168eaSwdenk #define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A) 101429168eaSwdenk #define PHY_LXT971_LED_CFG_TEST_OFF (0x0009) 102429168eaSwdenk #define PHY_LXT971_LED_CFG_TEST_ON (0x0008) 103429168eaSwdenk #define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007) 104429168eaSwdenk #define PHY_LXT971_LED_CFG_UNUSED2 (0x0006) 105429168eaSwdenk #define PHY_LXT971_LED_CFG_DUPLEX (0x0005) 106429168eaSwdenk #define PHY_LXT971_LED_CFG_LINK (0x0004) 107429168eaSwdenk #define PHY_LXT971_LED_CFG_COLLISION (0x0003) 108429168eaSwdenk #define PHY_LXT971_LED_CFG_RECEIVE (0x0002) 109429168eaSwdenk #define PHY_LXT971_LED_CFG_TRANSMIT (0x0001) 110429168eaSwdenk #define PHY_LXT971_LED_CFG_SPEED (0x0000) 111429168eaSwdenk 112429168eaSwdenk /* DIG_CFG Digitial Configuration Register Bit Fields */ 113429168eaSwdenk #define PHY_LXT971_DIG_CFG_RES1 (0xF000) 114429168eaSwdenk #define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800) 115429168eaSwdenk #define PHY_LXT971_DIG_CFG_RES2 (0x0400) 116429168eaSwdenk #define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200) 117429168eaSwdenk #define PHY_LXT971_DIG_CFG_RES3 (0x01FF) 118429168eaSwdenk 119429168eaSwdenk #define PHY_LXT971_MDIO_MAX_CLK (8000000) 120429168eaSwdenk #define PHY_MDIO_MAX_CLK (2500000) 121429168eaSwdenk 122429168eaSwdenk /* TX_CTRL Transmit Control Register Bit Fields 123429168eaSwdenk documentation is buggy for this register, therefore setting not included */ 124429168eaSwdenk 125429168eaSwdenk typedef enum 126429168eaSwdenk { 127429168eaSwdenk PHY_NONE = 0x0000, /* no PHY detected yet */ 128429168eaSwdenk PHY_LXT971A = 0x0013 129429168eaSwdenk } PhyType; 130429168eaSwdenk 131429168eaSwdenk #endif /* __LXT971A_H__ */ 132