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/openbmc/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dssi.h23 u8 resv0[0x4];
25 u8 resv1[0x8];
34 #define SSI_CR_CIS (0x00000200)
35 #define SSI_CR_TCH (0x00000100)
36 #define SSI_CR_MCE (0x00000080)
37 #define SSI_CR_I2S_MASK (0xFFFFFF9F)
38 #define SSI_CR_I2S_SLAVE (0x00000040)
39 #define SSI_CR_I2S_MASTER (0x00000020)
40 #define SSI_CR_I2S_NORMAL (0x00000000)
41 #define SSI_CR_SYN (0x00000010)
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dcom.fuc32 ctx_object: .b32 0
35 ctx_dma_query: .b32 0
36 ctx_dma_src: .b32 0
37 ctx_dma_dst: .b32 0
40 ctx_query_address_high: .b32 0
41 ctx_query_address_low: .b32 0
42 ctx_query_counter: .b32 0
43 ctx_src_address_high: .b32 0
44 ctx_src_address_low: .b32 0
45 ctx_src_pitch: .b32 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x25.dtsi24 0xffffffff 0xffe03fff 0xc000001c /* pioA */
25 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
26 0x80000000 0xfffd0000 0xb83fffff /* pioC */
27 0x003fffff 0x003f8000 0x00000000 /* pioD */
H A Dat91sam9g25.dtsi23 0xffffffff 0xffe0399f 0xc000001c /* pioA */
24 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
25 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
26 0x003fffff 0x003f8000 0x00000000 /* pioD */
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x25.dtsi23 0xffffffff 0xffe03fff 0xc000001c /* pioA */
24 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
25 0x80000000 0xfffd0000 0xb83fffff /* pioC */
26 0x003fffff 0x003f8000 0x00000000 /* pioD */
H A Dat91sam9g25.dtsi22 0xffffffff 0xffe0399f 0xc000001c /* pioA */
23 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
24 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
25 0x003fffff 0x003f8000 0x00000000 /* pioD */
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2400-vic.yaml56 reg = <0x1e6c0080 0x80>;
59 valid-sources = <0xffffffff 0x0007ffff>;
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dmisc_arria10.c24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
50 0
70 writel(0x003f0000, &noc_fw_ocram_base->region0); in socfpga_init_security_policies()
71 writel(0x1, &noc_fw_ocram_base->enable); in socfpga_init_security_policies()
74 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); in socfpga_init_security_policies()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dsun3mmu.h25 #define SUN3_CONTROL_MASK (0x0FFFFFFC)
29 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
30 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
31 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
32 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
33 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
34 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
35 #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
36 #define AC_SYNC_ERR 0x60000000 /* c fault type */
37 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
[all …]
/openbmc/u-boot/include/configs/
H A Dedb93xx.h38 #define CONFIG_ENV_SECT_SIZE 0x00020000
42 #define CONFIG_ENV_SECT_SIZE 0x00020000
46 #define CONFIG_ENV_SECT_SIZE 0x00020000
50 #define CONFIG_ENV_SECT_SIZE 0x00040000
54 #define CONFIG_ENV_SECT_SIZE 0x00020000
58 #define CONFIG_ENV_SECT_SIZE 0x00040000
62 #define CONFIG_ENV_SECT_SIZE 0x00040000
66 #define CONFIG_ENV_SECT_SIZE 0x00020000
83 #define CONFIG_SYS_SERIAL0 0x808C0000
84 #define CONFIG_SYS_SERIAL1 0x808D0000
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-tpiu.c22 #define TPIU_SUPP_PORTSZ 0x000
23 #define TPIU_CURR_PORTSZ 0x004
24 #define TPIU_SUPP_TRIGMODES 0x100
25 #define TPIU_TRIG_CNTRVAL 0x104
26 #define TPIU_TRIG_MULT 0x108
27 #define TPIU_SUPP_TESTPATM 0x200
28 #define TPIU_CURR_TESTPATM 0x204
29 #define TPIU_TEST_PATREPCNTR 0x208
30 #define TPIU_FFSR 0x300
31 #define TPIU_FFCR 0x304
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Dscx200_docflash.c27 static int probe = 0; /* Don't autoprobe */
28 static unsigned size = 0x1000000; /* 16 MiB the whole ISA address space */
32 module_param(probe, int, 0);
34 module_param(size, int, 0);
36 module_param(width, int, 0);
38 module_param(flashtype, charp, 0);
51 .offset = 0,
52 .size = 0xc0000
56 .offset = 0xc0000,
57 .size = 0x40000
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.c18 .rtc_soc_base_address = 0x00004000,
19 .rtc_wmac_base_address = 0x00005000,
20 .soc_core_base_address = 0x00009000,
21 .wlan_mac_base_address = 0x00020000,
22 .ce_wrapper_base_address = 0x00057000,
23 .ce0_base_address = 0x00057400,
24 .ce1_base_address = 0x00057800,
25 .ce2_base_address = 0x00057c00,
26 .ce3_base_address = 0x00058000,
27 .ce4_base_address = 0x00058400,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvega10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
42 #define SDMA_SUBOP_TIMESTAMP_SET 0
45 #define SDMA_SUBOP_COPY_LINEAR 0
53 #define SDMA_SUBOP_WRITE_LINEAR 0
55 #define SDMA_SUBOP_PTEPDE_GEN 0
65 #define SDMA_OP_AQL_COPY 0
66 #define SDMA_OP_AQL_BARRIER_OR 0
69 #define SDMA_PKT_HEADER_op_offset 0
70 #define SDMA_PKT_HEADER_op_mask 0x000000FF
71 #define SDMA_PKT_HEADER_op_shift 0
[all …]
H A Dnavi10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
60 #define SDMA_SUBOP_WRITE_LINEAR 0
63 #define SDMA_SUBOP_PTEPDE_GEN 0
73 #define SDMA_OP_AQL_COPY 0
74 #define SDMA_OP_AQL_BARRIER_OR 0
77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
H A Dtonga_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
H A Diceland_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
H A Dsdma_v6_0_0_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
61 #define SDMA_SUBOP_WRITE_LINEAR 0
64 #define SDMA_SUBOP_PTEPDE_GEN 0
76 #define SDMA_OP_AQL_COPY 0
77 #define SDMA_OP_AQL_BARRIER_OR 0
80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
[all …]
/openbmc/u-boot/drivers/net/
H A Dmvgbe.h18 #define PHY_BASE_ADR 0x08 /* default phy base addr */
22 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
23 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
24 #define MRU_MASK 0xfff1ffff
25 #define PHYADR_MASK 0x0000001f
26 #define PHYREG_MASK 0x0000001f
27 #define QTKNBKT_DEF_VAL 0x3fffffff
28 #define QMTBS_DEF_VAL 0x000003ff
29 #define QTKNRT_DEF_VAL 0x0000fcff
30 #define RXUQ 0 /* Used Rx queue */
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/openbmc/u-boot/board/freescale/m54455evb/
H A DREADME74 CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
157 Flash: 0x00000000-0x3FFFFFFF (1024MB)
158 DDR: 0x40000000-0x7FFFFFFF (1024MB)
159 SRAM: 0x80000000-0x8FFFFFFF (256MB)
160 ATA: 0x90000000-0x9FFFFFFF (256MB)
161 PCI: 0xA0000000-0xBFFFFFFF (512MB)
162 FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
163 IP: 0xF0000000-0xFFFFFFFF (256MB)
168 Flash0: 0x00000000-0x0007FFFF (512KB)
169 Flash1: 0x04000000-0x05FFFFFF (32MB)
[all …]

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