19a87c32fSHawking Zhang /* 29a87c32fSHawking Zhang * Copyright (C) 2019 Advanced Micro Devices, Inc. 39a87c32fSHawking Zhang * 49a87c32fSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 59a87c32fSHawking Zhang * copy of this software and associated documentation files (the "Software"), 69a87c32fSHawking Zhang * to deal in the Software without restriction, including without limitation 79a87c32fSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 89a87c32fSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 99a87c32fSHawking Zhang * Software is furnished to do so, subject to the following conditions: 109a87c32fSHawking Zhang * 119a87c32fSHawking Zhang * The above copyright notice and this permission notice shall be included 129a87c32fSHawking Zhang * in all copies or substantial portions of the Software. 139a87c32fSHawking Zhang * 149a87c32fSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 159a87c32fSHawking Zhang * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 169a87c32fSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 179a87c32fSHawking Zhang * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 189a87c32fSHawking Zhang * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 199a87c32fSHawking Zhang * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 209a87c32fSHawking Zhang * 219a87c32fSHawking Zhang */ 229a87c32fSHawking Zhang 239a87c32fSHawking Zhang #ifndef __NAVI10_SDMA_PKT_OPEN_H_ 249a87c32fSHawking Zhang #define __NAVI10_SDMA_PKT_OPEN_H_ 259a87c32fSHawking Zhang 269a87c32fSHawking Zhang #define SDMA_OP_NOP 0 279a87c32fSHawking Zhang #define SDMA_OP_COPY 1 289a87c32fSHawking Zhang #define SDMA_OP_WRITE 2 299a87c32fSHawking Zhang #define SDMA_OP_INDIRECT 4 309a87c32fSHawking Zhang #define SDMA_OP_FENCE 5 319a87c32fSHawking Zhang #define SDMA_OP_TRAP 6 329a87c32fSHawking Zhang #define SDMA_OP_SEM 7 339a87c32fSHawking Zhang #define SDMA_OP_POLL_REGMEM 8 349a87c32fSHawking Zhang #define SDMA_OP_COND_EXE 9 359a87c32fSHawking Zhang #define SDMA_OP_ATOMIC 10 369a87c32fSHawking Zhang #define SDMA_OP_CONST_FILL 11 379a87c32fSHawking Zhang #define SDMA_OP_PTEPDE 12 389a87c32fSHawking Zhang #define SDMA_OP_TIMESTAMP 13 399a87c32fSHawking Zhang #define SDMA_OP_SRBM_WRITE 14 409a87c32fSHawking Zhang #define SDMA_OP_PRE_EXE 15 419a87c32fSHawking Zhang #define SDMA_OP_GPUVM_INV 16 429a87c32fSHawking Zhang #define SDMA_OP_GCR_REQ 17 439a87c32fSHawking Zhang #define SDMA_OP_DUMMY_TRAP 32 449a87c32fSHawking Zhang #define SDMA_SUBOP_TIMESTAMP_SET 0 459a87c32fSHawking Zhang #define SDMA_SUBOP_TIMESTAMP_GET 1 469a87c32fSHawking Zhang #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 479a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_LINEAR 0 489a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 499a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_TILED 1 509a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 519a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 529a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_SOA 3 539a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 549a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_PHY 8 559a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_BC 16 569a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_TILED_BC 17 579a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 589a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 599a87c32fSHawking Zhang #define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 609a87c32fSHawking Zhang #define SDMA_SUBOP_WRITE_LINEAR 0 619a87c32fSHawking Zhang #define SDMA_SUBOP_WRITE_TILED 1 629a87c32fSHawking Zhang #define SDMA_SUBOP_WRITE_TILED_BC 17 639a87c32fSHawking Zhang #define SDMA_SUBOP_PTEPDE_GEN 0 649a87c32fSHawking Zhang #define SDMA_SUBOP_PTEPDE_COPY 1 659a87c32fSHawking Zhang #define SDMA_SUBOP_PTEPDE_RMW 2 669a87c32fSHawking Zhang #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 679a87c32fSHawking Zhang #define SDMA_SUBOP_DATA_FILL_MULTI 1 689a87c32fSHawking Zhang #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 699a87c32fSHawking Zhang #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 709a87c32fSHawking Zhang #define SDMA_SUBOP_POLL_MEM_VERIFY 3 719a87c32fSHawking Zhang #define HEADER_AGENT_DISPATCH 4 729a87c32fSHawking Zhang #define HEADER_BARRIER 5 739a87c32fSHawking Zhang #define SDMA_OP_AQL_COPY 0 749a87c32fSHawking Zhang #define SDMA_OP_AQL_BARRIER_OR 0 759a87c32fSHawking Zhang 76fdf83646SMarek Olšák #define SDMA_GCR_RANGE_IS_PA (1 << 18) 77fdf83646SMarek Olšák #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) 78fdf83646SMarek Olšák #define SDMA_GCR_GL2_WB (1 << 15) 79fdf83646SMarek Olšák #define SDMA_GCR_GL2_INV (1 << 14) 80fdf83646SMarek Olšák #define SDMA_GCR_GL2_DISCARD (1 << 13) 81fdf83646SMarek Olšák #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) 82fdf83646SMarek Olšák #define SDMA_GCR_GL2_US (1 << 10) 83fdf83646SMarek Olšák #define SDMA_GCR_GL1_INV (1 << 9) 84fdf83646SMarek Olšák #define SDMA_GCR_GLV_INV (1 << 8) 85fdf83646SMarek Olšák #define SDMA_GCR_GLK_INV (1 << 7) 86fdf83646SMarek Olšák #define SDMA_GCR_GLK_WB (1 << 6) 87fdf83646SMarek Olšák #define SDMA_GCR_GLM_INV (1 << 5) 88fdf83646SMarek Olšák #define SDMA_GCR_GLM_WB (1 << 4) 89fdf83646SMarek Olšák #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) 90fdf83646SMarek Olšák #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) 91fdf83646SMarek Olšák 929a87c32fSHawking Zhang /*define for op field*/ 939a87c32fSHawking Zhang #define SDMA_PKT_HEADER_op_offset 0 949a87c32fSHawking Zhang #define SDMA_PKT_HEADER_op_mask 0x000000FF 959a87c32fSHawking Zhang #define SDMA_PKT_HEADER_op_shift 0 969a87c32fSHawking Zhang #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 979a87c32fSHawking Zhang 989a87c32fSHawking Zhang /*define for sub_op field*/ 999a87c32fSHawking Zhang #define SDMA_PKT_HEADER_sub_op_offset 0 1009a87c32fSHawking Zhang #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 1019a87c32fSHawking Zhang #define SDMA_PKT_HEADER_sub_op_shift 8 1029a87c32fSHawking Zhang #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 1039a87c32fSHawking Zhang 1049a87c32fSHawking Zhang /* 1059a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR packet 1069a87c32fSHawking Zhang */ 1079a87c32fSHawking Zhang 1089a87c32fSHawking Zhang /*define for HEADER word*/ 1099a87c32fSHawking Zhang /*define for op field*/ 1109a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 1119a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 1129a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 1139a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 1149a87c32fSHawking Zhang 1159a87c32fSHawking Zhang /*define for sub_op field*/ 1169a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 1179a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 1189a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 1199a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 1209a87c32fSHawking Zhang 1219a87c32fSHawking Zhang /*define for encrypt field*/ 1229a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 1239a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 1249a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 1259a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 1269a87c32fSHawking Zhang 1279a87c32fSHawking Zhang /*define for tmz field*/ 1289a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 1299a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 1309a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 1319a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 1329a87c32fSHawking Zhang 1339a87c32fSHawking Zhang /*define for backwards field*/ 1349a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 1359a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 1369a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 1379a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) 1389a87c32fSHawking Zhang 1399a87c32fSHawking Zhang /*define for broadcast field*/ 1409a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 1419a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 1429a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 1439a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 1449a87c32fSHawking Zhang 1459a87c32fSHawking Zhang /*define for COUNT word*/ 1469a87c32fSHawking Zhang /*define for count field*/ 1479a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 1489a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 1499a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 1509a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 1519a87c32fSHawking Zhang 1529a87c32fSHawking Zhang /*define for PARAMETER word*/ 1539a87c32fSHawking Zhang /*define for dst_sw field*/ 1549a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 1559a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 1569a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 1579a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 1589a87c32fSHawking Zhang 1599a87c32fSHawking Zhang /*define for src_sw field*/ 1609a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 1619a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 1629a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 1639a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 1649a87c32fSHawking Zhang 1659a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 1669a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 1679a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 1689a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1699a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 1709a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 1719a87c32fSHawking Zhang 1729a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 1739a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 1749a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 1759a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1769a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 1779a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 1789a87c32fSHawking Zhang 1799a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 1809a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 1819a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 1829a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1839a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 1849a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 1859a87c32fSHawking Zhang 1869a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 1879a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 1889a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 1899a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1909a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 1919a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 1929a87c32fSHawking Zhang 1939a87c32fSHawking Zhang 1949a87c32fSHawking Zhang /* 1959a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_BC packet 1969a87c32fSHawking Zhang */ 1979a87c32fSHawking Zhang 1989a87c32fSHawking Zhang /*define for HEADER word*/ 1999a87c32fSHawking Zhang /*define for op field*/ 2009a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 2019a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF 2029a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 2039a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) 2049a87c32fSHawking Zhang 2059a87c32fSHawking Zhang /*define for sub_op field*/ 2069a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 2079a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF 2089a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 2099a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) 2109a87c32fSHawking Zhang 2119a87c32fSHawking Zhang /*define for COUNT word*/ 2129a87c32fSHawking Zhang /*define for count field*/ 2139a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 2149a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF 2159a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 2169a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) 2179a87c32fSHawking Zhang 2189a87c32fSHawking Zhang /*define for PARAMETER word*/ 2199a87c32fSHawking Zhang /*define for dst_sw field*/ 2209a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 2219a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 2229a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 2239a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) 2249a87c32fSHawking Zhang 2259a87c32fSHawking Zhang /*define for dst_ha field*/ 2269a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 2279a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 2289a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 22 2299a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) 2309a87c32fSHawking Zhang 2319a87c32fSHawking Zhang /*define for src_sw field*/ 2329a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 2339a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 2349a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 2359a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) 2369a87c32fSHawking Zhang 2379a87c32fSHawking Zhang /*define for src_ha field*/ 2389a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 2399a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 2409a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 30 2419a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) 2429a87c32fSHawking Zhang 2439a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 2449a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 2459a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 2469a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 2479a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 2489a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) 2499a87c32fSHawking Zhang 2509a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 2519a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 2529a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 2539a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 2549a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 2559a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) 2569a87c32fSHawking Zhang 2579a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 2589a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 2599a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 2609a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2619a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 2629a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) 2639a87c32fSHawking Zhang 2649a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 2659a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 2669a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 2679a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2689a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 2699a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) 2709a87c32fSHawking Zhang 2719a87c32fSHawking Zhang 2729a87c32fSHawking Zhang /* 2739a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 2749a87c32fSHawking Zhang */ 2759a87c32fSHawking Zhang 2769a87c32fSHawking Zhang /*define for HEADER word*/ 2779a87c32fSHawking Zhang /*define for op field*/ 2789a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 2799a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 2809a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 2819a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 2829a87c32fSHawking Zhang 2839a87c32fSHawking Zhang /*define for sub_op field*/ 2849a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 2859a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 2869a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 2879a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 2889a87c32fSHawking Zhang 2899a87c32fSHawking Zhang /*define for tmz field*/ 2909a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 2919a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 2929a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 2939a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 2949a87c32fSHawking Zhang 2959a87c32fSHawking Zhang /*define for all field*/ 2969a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 2979a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 2989a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 2999a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 3009a87c32fSHawking Zhang 3019a87c32fSHawking Zhang /*define for COUNT word*/ 3029a87c32fSHawking Zhang /*define for count field*/ 3039a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 3049a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 3059a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 3069a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 3079a87c32fSHawking Zhang 3089a87c32fSHawking Zhang /*define for PARAMETER word*/ 3099a87c32fSHawking Zhang /*define for dst_mtype field*/ 3109a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 3119a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 3129a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 3139a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) 3149a87c32fSHawking Zhang 3159a87c32fSHawking Zhang /*define for dst_l2_policy field*/ 3169a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 3179a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 3189a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 3199a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) 3209a87c32fSHawking Zhang 3219a87c32fSHawking Zhang /*define for src_mtype field*/ 3229a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 3239a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 3249a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 3259a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) 3269a87c32fSHawking Zhang 3279a87c32fSHawking Zhang /*define for src_l2_policy field*/ 3289a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 3299a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 3309a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 3319a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) 3329a87c32fSHawking Zhang 3339a87c32fSHawking Zhang /*define for dst_sw field*/ 3349a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 3359a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 3369a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 3379a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 3389a87c32fSHawking Zhang 3399a87c32fSHawking Zhang /*define for dst_gcc field*/ 3409a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 3419a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 3429a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 3439a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 3449a87c32fSHawking Zhang 3459a87c32fSHawking Zhang /*define for dst_sys field*/ 3469a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 3479a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 3489a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 3499a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 3509a87c32fSHawking Zhang 3519a87c32fSHawking Zhang /*define for dst_snoop field*/ 3529a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 3539a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 3549a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 3559a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 3569a87c32fSHawking Zhang 3579a87c32fSHawking Zhang /*define for dst_gpa field*/ 3589a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 3599a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 3609a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 3619a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 3629a87c32fSHawking Zhang 3639a87c32fSHawking Zhang /*define for src_sw field*/ 3649a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 3659a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 3669a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 3679a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 3689a87c32fSHawking Zhang 3699a87c32fSHawking Zhang /*define for src_sys field*/ 3709a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 3719a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 3729a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 3739a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 3749a87c32fSHawking Zhang 3759a87c32fSHawking Zhang /*define for src_snoop field*/ 3769a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 3779a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 3789a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 3799a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 3809a87c32fSHawking Zhang 3819a87c32fSHawking Zhang /*define for src_gpa field*/ 3829a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 3839a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 3849a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 3859a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 3869a87c32fSHawking Zhang 3879a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 3889a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 3899a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 3909a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3919a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 3929a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 3939a87c32fSHawking Zhang 3949a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 3959a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 3969a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 3979a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3989a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 3999a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 4009a87c32fSHawking Zhang 4019a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 4029a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 4039a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 4049a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4059a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 4069a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 4079a87c32fSHawking Zhang 4089a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 4099a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 4109a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 4119a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4129a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 4139a87c32fSHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 4149a87c32fSHawking Zhang 4159a87c32fSHawking Zhang 4169a87c32fSHawking Zhang /* 4179a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 4189a87c32fSHawking Zhang */ 4199a87c32fSHawking Zhang 4209a87c32fSHawking Zhang /*define for HEADER word*/ 4219a87c32fSHawking Zhang /*define for op field*/ 4229a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 4239a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 4249a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 4259a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 4269a87c32fSHawking Zhang 4279a87c32fSHawking Zhang /*define for sub_op field*/ 4289a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 4299a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 4309a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 4319a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 4329a87c32fSHawking Zhang 4339a87c32fSHawking Zhang /*define for tmz field*/ 4349a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 4359a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 4369a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 4379a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 4389a87c32fSHawking Zhang 4399a87c32fSHawking Zhang /*define for COUNT word*/ 4409a87c32fSHawking Zhang /*define for count field*/ 4419a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 4429a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 4439a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 4449a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 4459a87c32fSHawking Zhang 4469a87c32fSHawking Zhang /*define for PARAMETER word*/ 4479a87c32fSHawking Zhang /*define for dst_mtype field*/ 4489a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 4499a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 4509a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 4519a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) 4529a87c32fSHawking Zhang 4539a87c32fSHawking Zhang /*define for dst_l2_policy field*/ 4549a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 4559a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 4569a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 4579a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) 4589a87c32fSHawking Zhang 4599a87c32fSHawking Zhang /*define for src_mtype field*/ 4609a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 4619a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 4629a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 4639a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) 4649a87c32fSHawking Zhang 4659a87c32fSHawking Zhang /*define for src_l2_policy field*/ 4669a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 4679a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 4689a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 4699a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) 4709a87c32fSHawking Zhang 4719a87c32fSHawking Zhang /*define for dst_sw field*/ 4729a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 4739a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 4749a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 4759a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 4769a87c32fSHawking Zhang 4779a87c32fSHawking Zhang /*define for dst_gcc field*/ 4789a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 4799a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 4809a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 4819a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 4829a87c32fSHawking Zhang 4839a87c32fSHawking Zhang /*define for dst_sys field*/ 4849a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 4859a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 4869a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 4879a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 4889a87c32fSHawking Zhang 4899a87c32fSHawking Zhang /*define for dst_log field*/ 4909a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 4919a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 4929a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 4939a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 4949a87c32fSHawking Zhang 4959a87c32fSHawking Zhang /*define for dst_snoop field*/ 4969a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 4979a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 4989a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 4999a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 5009a87c32fSHawking Zhang 5019a87c32fSHawking Zhang /*define for dst_gpa field*/ 5029a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 5039a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 5049a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 5059a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 5069a87c32fSHawking Zhang 5079a87c32fSHawking Zhang /*define for src_sw field*/ 5089a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 5099a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 5109a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 5119a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 5129a87c32fSHawking Zhang 5139a87c32fSHawking Zhang /*define for src_gcc field*/ 5149a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 5159a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 5169a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 5179a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 5189a87c32fSHawking Zhang 5199a87c32fSHawking Zhang /*define for src_sys field*/ 5209a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 5219a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 5229a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 5239a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 5249a87c32fSHawking Zhang 5259a87c32fSHawking Zhang /*define for src_snoop field*/ 5269a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 5279a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 5289a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 5299a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 5309a87c32fSHawking Zhang 5319a87c32fSHawking Zhang /*define for src_gpa field*/ 5329a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 5339a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 5349a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 5359a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 5369a87c32fSHawking Zhang 5379a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 5389a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 5399a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 5409a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 5419a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 5429a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 5439a87c32fSHawking Zhang 5449a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 5459a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 5469a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 5479a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 5489a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 5499a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 5509a87c32fSHawking Zhang 5519a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 5529a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 5539a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 5549a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 5559a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 5569a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 5579a87c32fSHawking Zhang 5589a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 5599a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 5609a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 5619a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 5629a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 5639a87c32fSHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 5649a87c32fSHawking Zhang 5659a87c32fSHawking Zhang 5669a87c32fSHawking Zhang /* 5679a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 5689a87c32fSHawking Zhang */ 5699a87c32fSHawking Zhang 5709a87c32fSHawking Zhang /*define for HEADER word*/ 5719a87c32fSHawking Zhang /*define for op field*/ 5729a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 5739a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 5749a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 5759a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 5769a87c32fSHawking Zhang 5779a87c32fSHawking Zhang /*define for sub_op field*/ 5789a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 5799a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 5809a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 5819a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 5829a87c32fSHawking Zhang 5839a87c32fSHawking Zhang /*define for encrypt field*/ 5849a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 5859a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 5869a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 5879a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 5889a87c32fSHawking Zhang 5899a87c32fSHawking Zhang /*define for tmz field*/ 5909a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 5919a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 5929a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 5939a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 5949a87c32fSHawking Zhang 5959a87c32fSHawking Zhang /*define for broadcast field*/ 5969a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 5979a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 5989a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 5999a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 6009a87c32fSHawking Zhang 6019a87c32fSHawking Zhang /*define for COUNT word*/ 6029a87c32fSHawking Zhang /*define for count field*/ 6039a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 6049a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 6059a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 6069a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 6079a87c32fSHawking Zhang 6089a87c32fSHawking Zhang /*define for PARAMETER word*/ 6099a87c32fSHawking Zhang /*define for dst2_sw field*/ 6109a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 6119a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 6129a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 6139a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 6149a87c32fSHawking Zhang 6159a87c32fSHawking Zhang /*define for dst1_sw field*/ 6169a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 6179a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 6189a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 6199a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 6209a87c32fSHawking Zhang 6219a87c32fSHawking Zhang /*define for src_sw field*/ 6229a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 6239a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 6249a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 6259a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 6269a87c32fSHawking Zhang 6279a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 6289a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 6299a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 6309a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 6319a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 6329a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 6339a87c32fSHawking Zhang 6349a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 6359a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 6369a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 6379a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 6389a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 6399a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 6409a87c32fSHawking Zhang 6419a87c32fSHawking Zhang /*define for DST1_ADDR_LO word*/ 6429a87c32fSHawking Zhang /*define for dst1_addr_31_0 field*/ 6439a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 6449a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 6459a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 6469a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 6479a87c32fSHawking Zhang 6489a87c32fSHawking Zhang /*define for DST1_ADDR_HI word*/ 6499a87c32fSHawking Zhang /*define for dst1_addr_63_32 field*/ 6509a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 6519a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 6529a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 6539a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 6549a87c32fSHawking Zhang 6559a87c32fSHawking Zhang /*define for DST2_ADDR_LO word*/ 6569a87c32fSHawking Zhang /*define for dst2_addr_31_0 field*/ 6579a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 6589a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 6599a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 6609a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 6619a87c32fSHawking Zhang 6629a87c32fSHawking Zhang /*define for DST2_ADDR_HI word*/ 6639a87c32fSHawking Zhang /*define for dst2_addr_63_32 field*/ 6649a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 6659a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 6669a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 6679a87c32fSHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 6689a87c32fSHawking Zhang 6699a87c32fSHawking Zhang 6709a87c32fSHawking Zhang /* 6719a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 6729a87c32fSHawking Zhang */ 6739a87c32fSHawking Zhang 6749a87c32fSHawking Zhang /*define for HEADER word*/ 6759a87c32fSHawking Zhang /*define for op field*/ 6769a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 6779a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 6789a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 6799a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 6809a87c32fSHawking Zhang 6819a87c32fSHawking Zhang /*define for sub_op field*/ 6829a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 6839a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 6849a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 6859a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 6869a87c32fSHawking Zhang 6879a87c32fSHawking Zhang /*define for tmz field*/ 6889a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 6899a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 6909a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 6919a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 6929a87c32fSHawking Zhang 6939a87c32fSHawking Zhang /*define for elementsize field*/ 6949a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 6959a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 6969a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 6979a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 6989a87c32fSHawking Zhang 6999a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 7009a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 7019a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 7029a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 7039a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 7049a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 7059a87c32fSHawking Zhang 7069a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 7079a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 7089a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 7099a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 7109a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 7119a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 7129a87c32fSHawking Zhang 7139a87c32fSHawking Zhang /*define for DW_3 word*/ 7149a87c32fSHawking Zhang /*define for src_x field*/ 7159a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 7169a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 7179a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 7189a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 7199a87c32fSHawking Zhang 7209a87c32fSHawking Zhang /*define for src_y field*/ 7219a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 7229a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 7239a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 7249a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 7259a87c32fSHawking Zhang 7269a87c32fSHawking Zhang /*define for DW_4 word*/ 7279a87c32fSHawking Zhang /*define for src_z field*/ 7289a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 7299a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF 7309a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 7319a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 7329a87c32fSHawking Zhang 7339a87c32fSHawking Zhang /*define for src_pitch field*/ 7349a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 7359a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 7369a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 7379a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 7389a87c32fSHawking Zhang 7399a87c32fSHawking Zhang /*define for DW_5 word*/ 7409a87c32fSHawking Zhang /*define for src_slice_pitch field*/ 7419a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 7429a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 7439a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 7449a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 7459a87c32fSHawking Zhang 7469a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 7479a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 7489a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 7499a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 7509a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 7519a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 7529a87c32fSHawking Zhang 7539a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 7549a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 7559a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 7569a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 7579a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 7589a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 7599a87c32fSHawking Zhang 7609a87c32fSHawking Zhang /*define for DW_8 word*/ 7619a87c32fSHawking Zhang /*define for dst_x field*/ 7629a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 7639a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 7649a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 7659a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 7669a87c32fSHawking Zhang 7679a87c32fSHawking Zhang /*define for dst_y field*/ 7689a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 7699a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 7709a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 7719a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 7729a87c32fSHawking Zhang 7739a87c32fSHawking Zhang /*define for DW_9 word*/ 7749a87c32fSHawking Zhang /*define for dst_z field*/ 7759a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 7769a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF 7779a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 7789a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 7799a87c32fSHawking Zhang 7809a87c32fSHawking Zhang /*define for dst_pitch field*/ 7819a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 7829a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 7839a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 7849a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 7859a87c32fSHawking Zhang 7869a87c32fSHawking Zhang /*define for DW_10 word*/ 7879a87c32fSHawking Zhang /*define for dst_slice_pitch field*/ 7889a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 7899a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 7909a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 7919a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 7929a87c32fSHawking Zhang 7939a87c32fSHawking Zhang /*define for DW_11 word*/ 7949a87c32fSHawking Zhang /*define for rect_x field*/ 7959a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 7969a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 7979a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 7989a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 7999a87c32fSHawking Zhang 8009a87c32fSHawking Zhang /*define for rect_y field*/ 8019a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 8029a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 8039a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 8049a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 8059a87c32fSHawking Zhang 8069a87c32fSHawking Zhang /*define for DW_12 word*/ 8079a87c32fSHawking Zhang /*define for rect_z field*/ 8089a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 8099a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF 8109a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 8119a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 8129a87c32fSHawking Zhang 8139a87c32fSHawking Zhang /*define for dst_sw field*/ 8149a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 8159a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 8169a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 8179a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 8189a87c32fSHawking Zhang 8199a87c32fSHawking Zhang /*define for src_sw field*/ 8209a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 8219a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 8229a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 8239a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 8249a87c32fSHawking Zhang 8259a87c32fSHawking Zhang 8269a87c32fSHawking Zhang /* 8279a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet 8289a87c32fSHawking Zhang */ 8299a87c32fSHawking Zhang 8309a87c32fSHawking Zhang /*define for HEADER word*/ 8319a87c32fSHawking Zhang /*define for op field*/ 8329a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 8339a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF 8349a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 8359a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) 8369a87c32fSHawking Zhang 8379a87c32fSHawking Zhang /*define for sub_op field*/ 8389a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 8399a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 8409a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 8419a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) 8429a87c32fSHawking Zhang 8439a87c32fSHawking Zhang /*define for elementsize field*/ 8449a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 8459a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 8469a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 8479a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) 8489a87c32fSHawking Zhang 8499a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 8509a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 8519a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 8529a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 8539a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 8549a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) 8559a87c32fSHawking Zhang 8569a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 8579a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 8589a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 8599a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 8609a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 8619a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) 8629a87c32fSHawking Zhang 8639a87c32fSHawking Zhang /*define for DW_3 word*/ 8649a87c32fSHawking Zhang /*define for src_x field*/ 8659a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 8669a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF 8679a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 8689a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) 8699a87c32fSHawking Zhang 8709a87c32fSHawking Zhang /*define for src_y field*/ 8719a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 8729a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF 8739a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 8749a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) 8759a87c32fSHawking Zhang 8769a87c32fSHawking Zhang /*define for DW_4 word*/ 8779a87c32fSHawking Zhang /*define for src_z field*/ 8789a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 8799a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF 8809a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 8819a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) 8829a87c32fSHawking Zhang 8839a87c32fSHawking Zhang /*define for src_pitch field*/ 8849a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 8859a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF 8869a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 8879a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) 8889a87c32fSHawking Zhang 8899a87c32fSHawking Zhang /*define for DW_5 word*/ 8909a87c32fSHawking Zhang /*define for src_slice_pitch field*/ 8919a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 8929a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF 8939a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 8949a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) 8959a87c32fSHawking Zhang 8969a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 8979a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 8989a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 8999a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 9009a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 9019a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) 9029a87c32fSHawking Zhang 9039a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 9049a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 9059a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 9069a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 9079a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 9089a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) 9099a87c32fSHawking Zhang 9109a87c32fSHawking Zhang /*define for DW_8 word*/ 9119a87c32fSHawking Zhang /*define for dst_x field*/ 9129a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 9139a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF 9149a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 9159a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) 9169a87c32fSHawking Zhang 9179a87c32fSHawking Zhang /*define for dst_y field*/ 9189a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 9199a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF 9209a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 9219a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) 9229a87c32fSHawking Zhang 9239a87c32fSHawking Zhang /*define for DW_9 word*/ 9249a87c32fSHawking Zhang /*define for dst_z field*/ 9259a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 9269a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF 9279a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 9289a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) 9299a87c32fSHawking Zhang 9309a87c32fSHawking Zhang /*define for dst_pitch field*/ 9319a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 9329a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF 9339a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 9349a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) 9359a87c32fSHawking Zhang 9369a87c32fSHawking Zhang /*define for DW_10 word*/ 9379a87c32fSHawking Zhang /*define for dst_slice_pitch field*/ 9389a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 9399a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 9409a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 9419a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) 9429a87c32fSHawking Zhang 9439a87c32fSHawking Zhang /*define for DW_11 word*/ 9449a87c32fSHawking Zhang /*define for rect_x field*/ 9459a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 9469a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF 9479a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 9489a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) 9499a87c32fSHawking Zhang 9509a87c32fSHawking Zhang /*define for rect_y field*/ 9519a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 9529a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF 9539a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 9549a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) 9559a87c32fSHawking Zhang 9569a87c32fSHawking Zhang /*define for DW_12 word*/ 9579a87c32fSHawking Zhang /*define for rect_z field*/ 9589a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 9599a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF 9609a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 9619a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) 9629a87c32fSHawking Zhang 9639a87c32fSHawking Zhang /*define for dst_sw field*/ 9649a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 9659a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 9669a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 9679a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) 9689a87c32fSHawking Zhang 9699a87c32fSHawking Zhang /*define for dst_ha field*/ 9709a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 9719a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 9729a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 22 9739a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) 9749a87c32fSHawking Zhang 9759a87c32fSHawking Zhang /*define for src_sw field*/ 9769a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 9779a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 9789a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 9799a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) 9809a87c32fSHawking Zhang 9819a87c32fSHawking Zhang /*define for src_ha field*/ 9829a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 9839a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 9849a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 30 9859a87c32fSHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) 9869a87c32fSHawking Zhang 9879a87c32fSHawking Zhang 9889a87c32fSHawking Zhang /* 9899a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED packet 9909a87c32fSHawking Zhang */ 9919a87c32fSHawking Zhang 9929a87c32fSHawking Zhang /*define for HEADER word*/ 9939a87c32fSHawking Zhang /*define for op field*/ 9949a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 9959a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 9969a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 9979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 9989a87c32fSHawking Zhang 9999a87c32fSHawking Zhang /*define for sub_op field*/ 10009a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 10019a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 10029a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 10039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 10049a87c32fSHawking Zhang 10059a87c32fSHawking Zhang /*define for encrypt field*/ 10069a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 10079a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 10089a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 10099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 10109a87c32fSHawking Zhang 10119a87c32fSHawking Zhang /*define for tmz field*/ 10129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 10139a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 10149a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 10159a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 10169a87c32fSHawking Zhang 10179a87c32fSHawking Zhang /*define for detile field*/ 10189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 10199a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 10209a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 10219a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 10229a87c32fSHawking Zhang 10239a87c32fSHawking Zhang /*define for TILED_ADDR_LO word*/ 10249a87c32fSHawking Zhang /*define for tiled_addr_31_0 field*/ 10259a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 10269a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 10279a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 10289a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 10299a87c32fSHawking Zhang 10309a87c32fSHawking Zhang /*define for TILED_ADDR_HI word*/ 10319a87c32fSHawking Zhang /*define for tiled_addr_63_32 field*/ 10329a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 10339a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 10349a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 10359a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 10369a87c32fSHawking Zhang 10379a87c32fSHawking Zhang /*define for DW_3 word*/ 10389a87c32fSHawking Zhang /*define for width field*/ 10399a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 10409a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 10419a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 10429a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 10439a87c32fSHawking Zhang 10449a87c32fSHawking Zhang /*define for DW_4 word*/ 10459a87c32fSHawking Zhang /*define for height field*/ 10469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 10479a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 10489a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 10499a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 10509a87c32fSHawking Zhang 10519a87c32fSHawking Zhang /*define for depth field*/ 10529a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 10539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF 10549a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 10559a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 10569a87c32fSHawking Zhang 10579a87c32fSHawking Zhang /*define for DW_5 word*/ 10589a87c32fSHawking Zhang /*define for element_size field*/ 10599a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 10609a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 10619a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 10629a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 10639a87c32fSHawking Zhang 10649a87c32fSHawking Zhang /*define for swizzle_mode field*/ 10659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 10669a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 10679a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 10689a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 10699a87c32fSHawking Zhang 10709a87c32fSHawking Zhang /*define for dimension field*/ 10719a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 10729a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 10739a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 10749a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 10759a87c32fSHawking Zhang 10769a87c32fSHawking Zhang /*define for mip_max field*/ 10779a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 10789a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F 10799a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 10809a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) 10819a87c32fSHawking Zhang 10829a87c32fSHawking Zhang /*define for DW_6 word*/ 10839a87c32fSHawking Zhang /*define for x field*/ 10849a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 10859a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 10869a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 10879a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 10889a87c32fSHawking Zhang 10899a87c32fSHawking Zhang /*define for y field*/ 10909a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 10919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 10929a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 10939a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 10949a87c32fSHawking Zhang 10959a87c32fSHawking Zhang /*define for DW_7 word*/ 10969a87c32fSHawking Zhang /*define for z field*/ 10979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 10989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF 10999a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 11009a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 11019a87c32fSHawking Zhang 11029a87c32fSHawking Zhang /*define for linear_sw field*/ 11039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 11049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 11059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 11069a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 11079a87c32fSHawking Zhang 11089a87c32fSHawking Zhang /*define for linear_cc field*/ 11099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset 7 11109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask 0x00000001 11119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift 20 11129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift) 11139a87c32fSHawking Zhang 11149a87c32fSHawking Zhang /*define for tile_sw field*/ 11159a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 11169a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 11179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 11189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 11199a87c32fSHawking Zhang 11209a87c32fSHawking Zhang /*define for LINEAR_ADDR_LO word*/ 11219a87c32fSHawking Zhang /*define for linear_addr_31_0 field*/ 11229a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 11239a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 11249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 11259a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 11269a87c32fSHawking Zhang 11279a87c32fSHawking Zhang /*define for LINEAR_ADDR_HI word*/ 11289a87c32fSHawking Zhang /*define for linear_addr_63_32 field*/ 11299a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 11309a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 11319a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 11329a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 11339a87c32fSHawking Zhang 11349a87c32fSHawking Zhang /*define for LINEAR_PITCH word*/ 11359a87c32fSHawking Zhang /*define for linear_pitch field*/ 11369a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 11379a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 11389a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 11399a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 11409a87c32fSHawking Zhang 11419a87c32fSHawking Zhang /*define for LINEAR_SLICE_PITCH word*/ 11429a87c32fSHawking Zhang /*define for linear_slice_pitch field*/ 11439a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 11449a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 11459a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 11469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 11479a87c32fSHawking Zhang 11489a87c32fSHawking Zhang /*define for COUNT word*/ 11499a87c32fSHawking Zhang /*define for count field*/ 11509a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 11519a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x003FFFFF 11529a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 11539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 11549a87c32fSHawking Zhang 11559a87c32fSHawking Zhang 11569a87c32fSHawking Zhang /* 11579a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED_BC packet 11589a87c32fSHawking Zhang */ 11599a87c32fSHawking Zhang 11609a87c32fSHawking Zhang /*define for HEADER word*/ 11619a87c32fSHawking Zhang /*define for op field*/ 11629a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 11639a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF 11649a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 11659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) 11669a87c32fSHawking Zhang 11679a87c32fSHawking Zhang /*define for sub_op field*/ 11689a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 11699a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF 11709a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 11719a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) 11729a87c32fSHawking Zhang 11739a87c32fSHawking Zhang /*define for detile field*/ 11749a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 11759a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 11769a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 11779a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) 11789a87c32fSHawking Zhang 11799a87c32fSHawking Zhang /*define for TILED_ADDR_LO word*/ 11809a87c32fSHawking Zhang /*define for tiled_addr_31_0 field*/ 11819a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 11829a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 11839a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 11849a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 11859a87c32fSHawking Zhang 11869a87c32fSHawking Zhang /*define for TILED_ADDR_HI word*/ 11879a87c32fSHawking Zhang /*define for tiled_addr_63_32 field*/ 11889a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 11899a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 11909a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 11919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 11929a87c32fSHawking Zhang 11939a87c32fSHawking Zhang /*define for DW_3 word*/ 11949a87c32fSHawking Zhang /*define for width field*/ 11959a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 11969a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF 11979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 11989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) 11999a87c32fSHawking Zhang 12009a87c32fSHawking Zhang /*define for DW_4 word*/ 12019a87c32fSHawking Zhang /*define for height field*/ 12029a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 12039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF 12049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 12059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) 12069a87c32fSHawking Zhang 12079a87c32fSHawking Zhang /*define for depth field*/ 12089a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 12099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF 12109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 12119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) 12129a87c32fSHawking Zhang 12139a87c32fSHawking Zhang /*define for DW_5 word*/ 12149a87c32fSHawking Zhang /*define for element_size field*/ 12159a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 12169a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 12179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 12189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) 12199a87c32fSHawking Zhang 12209a87c32fSHawking Zhang /*define for array_mode field*/ 12219a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 12229a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F 12239a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 12249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) 12259a87c32fSHawking Zhang 12269a87c32fSHawking Zhang /*define for mit_mode field*/ 12279a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 12289a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 12299a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 12309a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) 12319a87c32fSHawking Zhang 12329a87c32fSHawking Zhang /*define for tilesplit_size field*/ 12339a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 12349a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 12359a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 12369a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) 12379a87c32fSHawking Zhang 12389a87c32fSHawking Zhang /*define for bank_w field*/ 12399a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 12409a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 12419a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 12429a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) 12439a87c32fSHawking Zhang 12449a87c32fSHawking Zhang /*define for bank_h field*/ 12459a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 12469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 12479a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 12489a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) 12499a87c32fSHawking Zhang 12509a87c32fSHawking Zhang /*define for num_bank field*/ 12519a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 12529a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 12539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 12549a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) 12559a87c32fSHawking Zhang 12569a87c32fSHawking Zhang /*define for mat_aspt field*/ 12579a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 12589a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 12599a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 12609a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) 12619a87c32fSHawking Zhang 12629a87c32fSHawking Zhang /*define for pipe_config field*/ 12639a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 12649a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F 12659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 12669a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) 12679a87c32fSHawking Zhang 12689a87c32fSHawking Zhang /*define for DW_6 word*/ 12699a87c32fSHawking Zhang /*define for x field*/ 12709a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 12719a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF 12729a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 12739a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) 12749a87c32fSHawking Zhang 12759a87c32fSHawking Zhang /*define for y field*/ 12769a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 12779a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF 12789a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 12799a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) 12809a87c32fSHawking Zhang 12819a87c32fSHawking Zhang /*define for DW_7 word*/ 12829a87c32fSHawking Zhang /*define for z field*/ 12839a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 12849a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF 12859a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 12869a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) 12879a87c32fSHawking Zhang 12889a87c32fSHawking Zhang /*define for linear_sw field*/ 12899a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 12909a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 12919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 12929a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) 12939a87c32fSHawking Zhang 12949a87c32fSHawking Zhang /*define for tile_sw field*/ 12959a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 12969a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 12979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 12989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) 12999a87c32fSHawking Zhang 13009a87c32fSHawking Zhang /*define for LINEAR_ADDR_LO word*/ 13019a87c32fSHawking Zhang /*define for linear_addr_31_0 field*/ 13029a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 13039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 13049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 13059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 13069a87c32fSHawking Zhang 13079a87c32fSHawking Zhang /*define for LINEAR_ADDR_HI word*/ 13089a87c32fSHawking Zhang /*define for linear_addr_63_32 field*/ 13099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 13109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 13119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 13129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 13139a87c32fSHawking Zhang 13149a87c32fSHawking Zhang /*define for LINEAR_PITCH word*/ 13159a87c32fSHawking Zhang /*define for linear_pitch field*/ 13169a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 13179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 13189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 13199a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) 13209a87c32fSHawking Zhang 13219a87c32fSHawking Zhang /*define for COUNT word*/ 13229a87c32fSHawking Zhang /*define for count field*/ 13239a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 11 13249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF 13259a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 13269a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) 13279a87c32fSHawking Zhang 13289a87c32fSHawking Zhang 13299a87c32fSHawking Zhang /* 13309a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 13319a87c32fSHawking Zhang */ 13329a87c32fSHawking Zhang 13339a87c32fSHawking Zhang /*define for HEADER word*/ 13349a87c32fSHawking Zhang /*define for op field*/ 13359a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 13369a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 13379a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 13389a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 13399a87c32fSHawking Zhang 13409a87c32fSHawking Zhang /*define for sub_op field*/ 13419a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 13429a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 13439a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 13449a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 13459a87c32fSHawking Zhang 13469a87c32fSHawking Zhang /*define for encrypt field*/ 13479a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 13489a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 13499a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 13509a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 13519a87c32fSHawking Zhang 13529a87c32fSHawking Zhang /*define for tmz field*/ 13539a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 13549a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 13559a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 13569a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 13579a87c32fSHawking Zhang 13589a87c32fSHawking Zhang /*define for videocopy field*/ 13599a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 13609a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 13619a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 13629a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 13639a87c32fSHawking Zhang 13649a87c32fSHawking Zhang /*define for broadcast field*/ 13659a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 13669a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 13679a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 13689a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 13699a87c32fSHawking Zhang 13709a87c32fSHawking Zhang /*define for TILED_ADDR_LO_0 word*/ 13719a87c32fSHawking Zhang /*define for tiled_addr0_31_0 field*/ 13729a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 13739a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 13749a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 13759a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 13769a87c32fSHawking Zhang 13779a87c32fSHawking Zhang /*define for TILED_ADDR_HI_0 word*/ 13789a87c32fSHawking Zhang /*define for tiled_addr0_63_32 field*/ 13799a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 13809a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 13819a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 13829a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 13839a87c32fSHawking Zhang 13849a87c32fSHawking Zhang /*define for TILED_ADDR_LO_1 word*/ 13859a87c32fSHawking Zhang /*define for tiled_addr1_31_0 field*/ 13869a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 13879a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 13889a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 13899a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 13909a87c32fSHawking Zhang 13919a87c32fSHawking Zhang /*define for TILED_ADDR_HI_1 word*/ 13929a87c32fSHawking Zhang /*define for tiled_addr1_63_32 field*/ 13939a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 13949a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 13959a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 13969a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 13979a87c32fSHawking Zhang 13989a87c32fSHawking Zhang /*define for DW_5 word*/ 13999a87c32fSHawking Zhang /*define for width field*/ 14009a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 14019a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 14029a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 14039a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 14049a87c32fSHawking Zhang 14059a87c32fSHawking Zhang /*define for DW_6 word*/ 14069a87c32fSHawking Zhang /*define for height field*/ 14079a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 14089a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 14099a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 14109a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 14119a87c32fSHawking Zhang 14129a87c32fSHawking Zhang /*define for depth field*/ 14139a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 14149a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF 14159a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 14169a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 14179a87c32fSHawking Zhang 14189a87c32fSHawking Zhang /*define for DW_7 word*/ 14199a87c32fSHawking Zhang /*define for element_size field*/ 14209a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 14219a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 14229a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 14239a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 14249a87c32fSHawking Zhang 14259a87c32fSHawking Zhang /*define for swizzle_mode field*/ 14269a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 14279a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 14289a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 14299a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 14309a87c32fSHawking Zhang 14319a87c32fSHawking Zhang /*define for dimension field*/ 14329a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 14339a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 14349a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 14359a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 14369a87c32fSHawking Zhang 14379a87c32fSHawking Zhang /*define for mip_max field*/ 14389a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 14399a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F 14409a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 14419a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) 14429a87c32fSHawking Zhang 14439a87c32fSHawking Zhang /*define for DW_8 word*/ 14449a87c32fSHawking Zhang /*define for x field*/ 14459a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 14469a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 14479a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 14489a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 14499a87c32fSHawking Zhang 14509a87c32fSHawking Zhang /*define for y field*/ 14519a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 14529a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 14539a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 14549a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 14559a87c32fSHawking Zhang 14569a87c32fSHawking Zhang /*define for DW_9 word*/ 14579a87c32fSHawking Zhang /*define for z field*/ 14589a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 14599a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF 14609a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 14619a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 14629a87c32fSHawking Zhang 14639a87c32fSHawking Zhang /*define for DW_10 word*/ 14649a87c32fSHawking Zhang /*define for dst2_sw field*/ 14659a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 14669a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 14679a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 14689a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 14699a87c32fSHawking Zhang 14709a87c32fSHawking Zhang /*define for linear_sw field*/ 14719a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 14729a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 14739a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 14749a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 14759a87c32fSHawking Zhang 14769a87c32fSHawking Zhang /*define for tile_sw field*/ 14779a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 14789a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 14799a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 14809a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 14819a87c32fSHawking Zhang 14829a87c32fSHawking Zhang /*define for LINEAR_ADDR_LO word*/ 14839a87c32fSHawking Zhang /*define for linear_addr_31_0 field*/ 14849a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 14859a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 14869a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 14879a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 14889a87c32fSHawking Zhang 14899a87c32fSHawking Zhang /*define for LINEAR_ADDR_HI word*/ 14909a87c32fSHawking Zhang /*define for linear_addr_63_32 field*/ 14919a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 14929a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 14939a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 14949a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 14959a87c32fSHawking Zhang 14969a87c32fSHawking Zhang /*define for LINEAR_PITCH word*/ 14979a87c32fSHawking Zhang /*define for linear_pitch field*/ 14989a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 14999a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 15009a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 15019a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 15029a87c32fSHawking Zhang 15039a87c32fSHawking Zhang /*define for LINEAR_SLICE_PITCH word*/ 15049a87c32fSHawking Zhang /*define for linear_slice_pitch field*/ 15059a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 15069a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 15079a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 15089a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 15099a87c32fSHawking Zhang 15109a87c32fSHawking Zhang /*define for COUNT word*/ 15119a87c32fSHawking Zhang /*define for count field*/ 15129a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 15139a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x003FFFFF 15149a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 15159a87c32fSHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 15169a87c32fSHawking Zhang 15179a87c32fSHawking Zhang 15189a87c32fSHawking Zhang /* 15199a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_T2T packet 15209a87c32fSHawking Zhang */ 15219a87c32fSHawking Zhang 15229a87c32fSHawking Zhang /*define for HEADER word*/ 15239a87c32fSHawking Zhang /*define for op field*/ 15249a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 15259a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 15269a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 15279a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 15289a87c32fSHawking Zhang 15299a87c32fSHawking Zhang /*define for sub_op field*/ 15309a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 15319a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 15329a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 15339a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 15349a87c32fSHawking Zhang 15359a87c32fSHawking Zhang /*define for tmz field*/ 15369a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 15379a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 15389a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 15399a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 15409a87c32fSHawking Zhang 15419a87c32fSHawking Zhang /*define for dcc field*/ 15429a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 15439a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 15449a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 15459a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) 15469a87c32fSHawking Zhang 15479a87c32fSHawking Zhang /*define for dcc_dir field*/ 15489a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 15499a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 15509a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 15519a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) 15529a87c32fSHawking Zhang 15539a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 15549a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 15559a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 15569a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 15579a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 15589a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 15599a87c32fSHawking Zhang 15609a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 15619a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 15629a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 15639a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 15649a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 15659a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 15669a87c32fSHawking Zhang 15679a87c32fSHawking Zhang /*define for DW_3 word*/ 15689a87c32fSHawking Zhang /*define for src_x field*/ 15699a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 15709a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 15719a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 15729a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 15739a87c32fSHawking Zhang 15749a87c32fSHawking Zhang /*define for src_y field*/ 15759a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 15769a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 15779a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 15789a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 15799a87c32fSHawking Zhang 15809a87c32fSHawking Zhang /*define for DW_4 word*/ 15819a87c32fSHawking Zhang /*define for src_z field*/ 15829a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 15839a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF 15849a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 15859a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 15869a87c32fSHawking Zhang 15879a87c32fSHawking Zhang /*define for src_width field*/ 15889a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 15899a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 15909a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 15919a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 15929a87c32fSHawking Zhang 15939a87c32fSHawking Zhang /*define for DW_5 word*/ 15949a87c32fSHawking Zhang /*define for src_height field*/ 15959a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 15969a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 15979a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 15989a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 15999a87c32fSHawking Zhang 16009a87c32fSHawking Zhang /*define for src_depth field*/ 16019a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 16029a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF 16039a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 16049a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 16059a87c32fSHawking Zhang 16069a87c32fSHawking Zhang /*define for DW_6 word*/ 16079a87c32fSHawking Zhang /*define for src_element_size field*/ 16089a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 16099a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 16109a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 16119a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 16129a87c32fSHawking Zhang 16139a87c32fSHawking Zhang /*define for src_swizzle_mode field*/ 16149a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 16159a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 16169a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 16179a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 16189a87c32fSHawking Zhang 16199a87c32fSHawking Zhang /*define for src_dimension field*/ 16209a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 16219a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 16229a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 16239a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 16249a87c32fSHawking Zhang 16259a87c32fSHawking Zhang /*define for src_mip_max field*/ 16269a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 16279a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F 16289a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 16299a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) 16309a87c32fSHawking Zhang 16319a87c32fSHawking Zhang /*define for src_mip_id field*/ 16329a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 16339a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F 16349a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 16359a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) 16369a87c32fSHawking Zhang 16379a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 16389a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 16399a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 16409a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 16419a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 16429a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 16439a87c32fSHawking Zhang 16449a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 16459a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 16469a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 16479a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 16489a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 16499a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 16509a87c32fSHawking Zhang 16519a87c32fSHawking Zhang /*define for DW_9 word*/ 16529a87c32fSHawking Zhang /*define for dst_x field*/ 16539a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 16549a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 16559a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 16569a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 16579a87c32fSHawking Zhang 16589a87c32fSHawking Zhang /*define for dst_y field*/ 16599a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 16609a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 16619a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 16629a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 16639a87c32fSHawking Zhang 16649a87c32fSHawking Zhang /*define for DW_10 word*/ 16659a87c32fSHawking Zhang /*define for dst_z field*/ 16669a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 16679a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF 16689a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 16699a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 16709a87c32fSHawking Zhang 16719a87c32fSHawking Zhang /*define for dst_width field*/ 16729a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 16739a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 16749a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 16759a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 16769a87c32fSHawking Zhang 16779a87c32fSHawking Zhang /*define for DW_11 word*/ 16789a87c32fSHawking Zhang /*define for dst_height field*/ 16799a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 16809a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 16819a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 16829a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 16839a87c32fSHawking Zhang 16849a87c32fSHawking Zhang /*define for dst_depth field*/ 16859a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 16869a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF 16879a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 16889a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 16899a87c32fSHawking Zhang 16909a87c32fSHawking Zhang /*define for DW_12 word*/ 16919a87c32fSHawking Zhang /*define for dst_element_size field*/ 16929a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 16939a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 16949a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 16959a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 16969a87c32fSHawking Zhang 16979a87c32fSHawking Zhang /*define for dst_swizzle_mode field*/ 16989a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 16999a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 17009a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 17019a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 17029a87c32fSHawking Zhang 17039a87c32fSHawking Zhang /*define for dst_dimension field*/ 17049a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 17059a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 17069a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 17079a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 17089a87c32fSHawking Zhang 17099a87c32fSHawking Zhang /*define for dst_mip_max field*/ 17109a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 17119a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F 17129a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 17139a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) 17149a87c32fSHawking Zhang 17159a87c32fSHawking Zhang /*define for dst_mip_id field*/ 17169a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 17179a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F 17189a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 17199a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) 17209a87c32fSHawking Zhang 17219a87c32fSHawking Zhang /*define for DW_13 word*/ 17229a87c32fSHawking Zhang /*define for rect_x field*/ 17239a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 17249a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 17259a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 17269a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 17279a87c32fSHawking Zhang 17289a87c32fSHawking Zhang /*define for rect_y field*/ 17299a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 17309a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 17319a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 17329a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 17339a87c32fSHawking Zhang 17349a87c32fSHawking Zhang /*define for DW_14 word*/ 17359a87c32fSHawking Zhang /*define for rect_z field*/ 17369a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 17379a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF 17389a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 17399a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 17409a87c32fSHawking Zhang 17419a87c32fSHawking Zhang /*define for dst_sw field*/ 17429a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 17439a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 17449a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 17459a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 17469a87c32fSHawking Zhang 17479a87c32fSHawking Zhang /*define for src_sw field*/ 17489a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 17499a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 17509a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 17519a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 17529a87c32fSHawking Zhang 17539a87c32fSHawking Zhang /*define for META_ADDR_LO word*/ 17549a87c32fSHawking Zhang /*define for meta_addr_31_0 field*/ 17559a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 17569a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 17579a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 17589a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) 17599a87c32fSHawking Zhang 17609a87c32fSHawking Zhang /*define for META_ADDR_HI word*/ 17619a87c32fSHawking Zhang /*define for meta_addr_63_32 field*/ 17629a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 17639a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 17649a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 17659a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) 17669a87c32fSHawking Zhang 17679a87c32fSHawking Zhang /*define for META_CONFIG word*/ 17689a87c32fSHawking Zhang /*define for data_format field*/ 17699a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 17709a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F 17719a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 17729a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) 17739a87c32fSHawking Zhang 17749a87c32fSHawking Zhang /*define for color_transform_disable field*/ 17759a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 17769a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 17779a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 17789a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) 17799a87c32fSHawking Zhang 17809a87c32fSHawking Zhang /*define for alpha_is_on_msb field*/ 17819a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 17829a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 17839a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 17849a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) 17859a87c32fSHawking Zhang 17869a87c32fSHawking Zhang /*define for number_type field*/ 17879a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 17889a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 17899a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 17909a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) 17919a87c32fSHawking Zhang 17929a87c32fSHawking Zhang /*define for surface_type field*/ 17939a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 17949a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 17959a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 17969a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) 17979a87c32fSHawking Zhang 17989a87c32fSHawking Zhang /*define for max_comp_block_size field*/ 17999a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 18009a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 18019a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 18029a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) 18039a87c32fSHawking Zhang 18049a87c32fSHawking Zhang /*define for max_uncomp_block_size field*/ 18059a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 18069a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 18079a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 18089a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) 18099a87c32fSHawking Zhang 18109a87c32fSHawking Zhang /*define for write_compress_enable field*/ 18119a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 18129a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 18139a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 18149a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) 18159a87c32fSHawking Zhang 18169a87c32fSHawking Zhang /*define for meta_tmz field*/ 18179a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 18189a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 18199a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 18209a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) 18219a87c32fSHawking Zhang 18229a87c32fSHawking Zhang 18239a87c32fSHawking Zhang /* 18249a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_T2T_BC packet 18259a87c32fSHawking Zhang */ 18269a87c32fSHawking Zhang 18279a87c32fSHawking Zhang /*define for HEADER word*/ 18289a87c32fSHawking Zhang /*define for op field*/ 18299a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 18309a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF 18319a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 18329a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) 18339a87c32fSHawking Zhang 18349a87c32fSHawking Zhang /*define for sub_op field*/ 18359a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 18369a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF 18379a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 18389a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) 18399a87c32fSHawking Zhang 18409a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 18419a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 18429a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 18439a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 18449a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 18459a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) 18469a87c32fSHawking Zhang 18479a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 18489a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 18499a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 18509a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 18519a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 18529a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) 18539a87c32fSHawking Zhang 18549a87c32fSHawking Zhang /*define for DW_3 word*/ 18559a87c32fSHawking Zhang /*define for src_x field*/ 18569a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 18579a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF 18589a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 18599a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) 18609a87c32fSHawking Zhang 18619a87c32fSHawking Zhang /*define for src_y field*/ 18629a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 18639a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF 18649a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 18659a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) 18669a87c32fSHawking Zhang 18679a87c32fSHawking Zhang /*define for DW_4 word*/ 18689a87c32fSHawking Zhang /*define for src_z field*/ 18699a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 18709a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF 18719a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 18729a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) 18739a87c32fSHawking Zhang 18749a87c32fSHawking Zhang /*define for src_width field*/ 18759a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 18769a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF 18779a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 18789a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) 18799a87c32fSHawking Zhang 18809a87c32fSHawking Zhang /*define for DW_5 word*/ 18819a87c32fSHawking Zhang /*define for src_height field*/ 18829a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 18839a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF 18849a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 18859a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) 18869a87c32fSHawking Zhang 18879a87c32fSHawking Zhang /*define for src_depth field*/ 18889a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 18899a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF 18909a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 18919a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) 18929a87c32fSHawking Zhang 18939a87c32fSHawking Zhang /*define for DW_6 word*/ 18949a87c32fSHawking Zhang /*define for src_element_size field*/ 18959a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 18969a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 18979a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 18989a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) 18999a87c32fSHawking Zhang 19009a87c32fSHawking Zhang /*define for src_array_mode field*/ 19019a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 19029a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F 19039a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 19049a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) 19059a87c32fSHawking Zhang 19069a87c32fSHawking Zhang /*define for src_mit_mode field*/ 19079a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 19089a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 19099a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 19109a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) 19119a87c32fSHawking Zhang 19129a87c32fSHawking Zhang /*define for src_tilesplit_size field*/ 19139a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 19149a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 19159a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 19169a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) 19179a87c32fSHawking Zhang 19189a87c32fSHawking Zhang /*define for src_bank_w field*/ 19199a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 19209a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 19219a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 19229a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) 19239a87c32fSHawking Zhang 19249a87c32fSHawking Zhang /*define for src_bank_h field*/ 19259a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 19269a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 19279a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 19289a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) 19299a87c32fSHawking Zhang 19309a87c32fSHawking Zhang /*define for src_num_bank field*/ 19319a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 19329a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 19339a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 19349a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) 19359a87c32fSHawking Zhang 19369a87c32fSHawking Zhang /*define for src_mat_aspt field*/ 19379a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 19389a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 19399a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 19409a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) 19419a87c32fSHawking Zhang 19429a87c32fSHawking Zhang /*define for src_pipe_config field*/ 19439a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 19449a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F 19459a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 19469a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) 19479a87c32fSHawking Zhang 19489a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 19499a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 19509a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 19519a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 19529a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 19539a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) 19549a87c32fSHawking Zhang 19559a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 19569a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 19579a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 19589a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 19599a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 19609a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) 19619a87c32fSHawking Zhang 19629a87c32fSHawking Zhang /*define for DW_9 word*/ 19639a87c32fSHawking Zhang /*define for dst_x field*/ 19649a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 19659a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF 19669a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 19679a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) 19689a87c32fSHawking Zhang 19699a87c32fSHawking Zhang /*define for dst_y field*/ 19709a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 19719a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF 19729a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 19739a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) 19749a87c32fSHawking Zhang 19759a87c32fSHawking Zhang /*define for DW_10 word*/ 19769a87c32fSHawking Zhang /*define for dst_z field*/ 19779a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 19789a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF 19799a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 19809a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) 19819a87c32fSHawking Zhang 19829a87c32fSHawking Zhang /*define for dst_width field*/ 19839a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 19849a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF 19859a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 19869a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) 19879a87c32fSHawking Zhang 19889a87c32fSHawking Zhang /*define for DW_11 word*/ 19899a87c32fSHawking Zhang /*define for dst_height field*/ 19909a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 19919a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF 19929a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 19939a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) 19949a87c32fSHawking Zhang 19959a87c32fSHawking Zhang /*define for dst_depth field*/ 19969a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 19979a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF 19989a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 19999a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) 20009a87c32fSHawking Zhang 20019a87c32fSHawking Zhang /*define for DW_12 word*/ 20029a87c32fSHawking Zhang /*define for dst_element_size field*/ 20039a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 20049a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 20059a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 20069a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) 20079a87c32fSHawking Zhang 20089a87c32fSHawking Zhang /*define for dst_array_mode field*/ 20099a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 20109a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F 20119a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 20129a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) 20139a87c32fSHawking Zhang 20149a87c32fSHawking Zhang /*define for dst_mit_mode field*/ 20159a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 20169a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 20179a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 20189a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) 20199a87c32fSHawking Zhang 20209a87c32fSHawking Zhang /*define for dst_tilesplit_size field*/ 20219a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 20229a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 20239a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 20249a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) 20259a87c32fSHawking Zhang 20269a87c32fSHawking Zhang /*define for dst_bank_w field*/ 20279a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 20289a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 20299a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 20309a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) 20319a87c32fSHawking Zhang 20329a87c32fSHawking Zhang /*define for dst_bank_h field*/ 20339a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 20349a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 20359a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 20369a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) 20379a87c32fSHawking Zhang 20389a87c32fSHawking Zhang /*define for dst_num_bank field*/ 20399a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 20409a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 20419a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 20429a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) 20439a87c32fSHawking Zhang 20449a87c32fSHawking Zhang /*define for dst_mat_aspt field*/ 20459a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 20469a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 20479a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 20489a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) 20499a87c32fSHawking Zhang 20509a87c32fSHawking Zhang /*define for dst_pipe_config field*/ 20519a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 20529a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F 20539a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 20549a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) 20559a87c32fSHawking Zhang 20569a87c32fSHawking Zhang /*define for DW_13 word*/ 20579a87c32fSHawking Zhang /*define for rect_x field*/ 20589a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 20599a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF 20609a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 20619a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) 20629a87c32fSHawking Zhang 20639a87c32fSHawking Zhang /*define for rect_y field*/ 20649a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 20659a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF 20669a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 20679a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) 20689a87c32fSHawking Zhang 20699a87c32fSHawking Zhang /*define for DW_14 word*/ 20709a87c32fSHawking Zhang /*define for rect_z field*/ 20719a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 20729a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF 20739a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 20749a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) 20759a87c32fSHawking Zhang 20769a87c32fSHawking Zhang /*define for dst_sw field*/ 20779a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 20789a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 20799a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 20809a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) 20819a87c32fSHawking Zhang 20829a87c32fSHawking Zhang /*define for src_sw field*/ 20839a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 20849a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 20859a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 20869a87c32fSHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) 20879a87c32fSHawking Zhang 20889a87c32fSHawking Zhang 20899a87c32fSHawking Zhang /* 20909a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 20919a87c32fSHawking Zhang */ 20929a87c32fSHawking Zhang 20939a87c32fSHawking Zhang /*define for HEADER word*/ 20949a87c32fSHawking Zhang /*define for op field*/ 20959a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 20969a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 20979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 20989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 20999a87c32fSHawking Zhang 21009a87c32fSHawking Zhang /*define for sub_op field*/ 21019a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 21029a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 21039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 21049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 21059a87c32fSHawking Zhang 21069a87c32fSHawking Zhang /*define for tmz field*/ 21079a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 21089a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 21099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 21109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 21119a87c32fSHawking Zhang 21129a87c32fSHawking Zhang /*define for dcc field*/ 21139a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 21149a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 21159a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 21169a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) 21179a87c32fSHawking Zhang 21189a87c32fSHawking Zhang /*define for detile field*/ 21199a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 21209a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 21219a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 21229a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 21239a87c32fSHawking Zhang 21249a87c32fSHawking Zhang /*define for TILED_ADDR_LO word*/ 21259a87c32fSHawking Zhang /*define for tiled_addr_31_0 field*/ 21269a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 21279a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 21289a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 21299a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 21309a87c32fSHawking Zhang 21319a87c32fSHawking Zhang /*define for TILED_ADDR_HI word*/ 21329a87c32fSHawking Zhang /*define for tiled_addr_63_32 field*/ 21339a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 21349a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 21359a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 21369a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 21379a87c32fSHawking Zhang 21389a87c32fSHawking Zhang /*define for DW_3 word*/ 21399a87c32fSHawking Zhang /*define for tiled_x field*/ 21409a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 21419a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 21429a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 21439a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 21449a87c32fSHawking Zhang 21459a87c32fSHawking Zhang /*define for tiled_y field*/ 21469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 21479a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 21489a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 21499a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 21509a87c32fSHawking Zhang 21519a87c32fSHawking Zhang /*define for DW_4 word*/ 21529a87c32fSHawking Zhang /*define for tiled_z field*/ 21539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 21549a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF 21559a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 21569a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 21579a87c32fSHawking Zhang 21589a87c32fSHawking Zhang /*define for width field*/ 21599a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 21609a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 21619a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 21629a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 21639a87c32fSHawking Zhang 21649a87c32fSHawking Zhang /*define for DW_5 word*/ 21659a87c32fSHawking Zhang /*define for height field*/ 21669a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 21679a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 21689a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 21699a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 21709a87c32fSHawking Zhang 21719a87c32fSHawking Zhang /*define for depth field*/ 21729a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 21739a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF 21749a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 21759a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 21769a87c32fSHawking Zhang 21779a87c32fSHawking Zhang /*define for DW_6 word*/ 21789a87c32fSHawking Zhang /*define for element_size field*/ 21799a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 21809a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 21819a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 21829a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 21839a87c32fSHawking Zhang 21849a87c32fSHawking Zhang /*define for swizzle_mode field*/ 21859a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 21869a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 21879a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 21889a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 21899a87c32fSHawking Zhang 21909a87c32fSHawking Zhang /*define for dimension field*/ 21919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 21929a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 21939a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 21949a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 21959a87c32fSHawking Zhang 21969a87c32fSHawking Zhang /*define for mip_max field*/ 21979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 21989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F 21999a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 22009a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) 22019a87c32fSHawking Zhang 22029a87c32fSHawking Zhang /*define for mip_id field*/ 22039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 22049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F 22059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 22069a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) 22079a87c32fSHawking Zhang 22089a87c32fSHawking Zhang /*define for LINEAR_ADDR_LO word*/ 22099a87c32fSHawking Zhang /*define for linear_addr_31_0 field*/ 22109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 22119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 22129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 22139a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 22149a87c32fSHawking Zhang 22159a87c32fSHawking Zhang /*define for LINEAR_ADDR_HI word*/ 22169a87c32fSHawking Zhang /*define for linear_addr_63_32 field*/ 22179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 22189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 22199a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 22209a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 22219a87c32fSHawking Zhang 22229a87c32fSHawking Zhang /*define for DW_9 word*/ 22239a87c32fSHawking Zhang /*define for linear_x field*/ 22249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 22259a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 22269a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 22279a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 22289a87c32fSHawking Zhang 22299a87c32fSHawking Zhang /*define for linear_y field*/ 22309a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 22319a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 22329a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 22339a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 22349a87c32fSHawking Zhang 22359a87c32fSHawking Zhang /*define for DW_10 word*/ 22369a87c32fSHawking Zhang /*define for linear_z field*/ 22379a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 22389a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF 22399a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 22409a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 22419a87c32fSHawking Zhang 22429a87c32fSHawking Zhang /*define for linear_pitch field*/ 22439a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 22449a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 22459a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 22469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 22479a87c32fSHawking Zhang 22489a87c32fSHawking Zhang /*define for DW_11 word*/ 22499a87c32fSHawking Zhang /*define for linear_slice_pitch field*/ 22509a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 22519a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 22529a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 22539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 22549a87c32fSHawking Zhang 22559a87c32fSHawking Zhang /*define for DW_12 word*/ 22569a87c32fSHawking Zhang /*define for rect_x field*/ 22579a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 22589a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 22599a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 22609a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 22619a87c32fSHawking Zhang 22629a87c32fSHawking Zhang /*define for rect_y field*/ 22639a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 22649a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 22659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 22669a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 22679a87c32fSHawking Zhang 22689a87c32fSHawking Zhang /*define for DW_13 word*/ 22699a87c32fSHawking Zhang /*define for rect_z field*/ 22709a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 22719a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF 22729a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 22739a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 22749a87c32fSHawking Zhang 22759a87c32fSHawking Zhang /*define for linear_sw field*/ 22769a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 22779a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 22789a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 22799a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 22809a87c32fSHawking Zhang 22819a87c32fSHawking Zhang /*define for tile_sw field*/ 22829a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 22839a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 22849a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 22859a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 22869a87c32fSHawking Zhang 22879a87c32fSHawking Zhang /*define for META_ADDR_LO word*/ 22889a87c32fSHawking Zhang /*define for meta_addr_31_0 field*/ 22899a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 22909a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 22919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 22929a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) 22939a87c32fSHawking Zhang 22949a87c32fSHawking Zhang /*define for META_ADDR_HI word*/ 22959a87c32fSHawking Zhang /*define for meta_addr_63_32 field*/ 22969a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 22979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 22989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 22999a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) 23009a87c32fSHawking Zhang 23019a87c32fSHawking Zhang /*define for META_CONFIG word*/ 23029a87c32fSHawking Zhang /*define for data_format field*/ 23039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 23049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F 23059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 23069a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) 23079a87c32fSHawking Zhang 23089a87c32fSHawking Zhang /*define for color_transform_disable field*/ 23099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 23109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 23119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 23129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) 23139a87c32fSHawking Zhang 23149a87c32fSHawking Zhang /*define for alpha_is_on_msb field*/ 23159a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 23169a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 23179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 23189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) 23199a87c32fSHawking Zhang 23209a87c32fSHawking Zhang /*define for number_type field*/ 23219a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 23229a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 23239a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 23249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) 23259a87c32fSHawking Zhang 23269a87c32fSHawking Zhang /*define for surface_type field*/ 23279a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 23289a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 23299a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 23309a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) 23319a87c32fSHawking Zhang 23329a87c32fSHawking Zhang /*define for max_comp_block_size field*/ 23339a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 23349a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 23359a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 23369a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) 23379a87c32fSHawking Zhang 23389a87c32fSHawking Zhang /*define for max_uncomp_block_size field*/ 23399a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 23409a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 23419a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 23429a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) 23439a87c32fSHawking Zhang 23449a87c32fSHawking Zhang /*define for write_compress_enable field*/ 23459a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 23469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 23479a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 23489a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) 23499a87c32fSHawking Zhang 23509a87c32fSHawking Zhang /*define for meta_tmz field*/ 23519a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 23529a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 23539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 23549a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) 23559a87c32fSHawking Zhang 23569a87c32fSHawking Zhang 23579a87c32fSHawking Zhang /* 23589a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet 23599a87c32fSHawking Zhang */ 23609a87c32fSHawking Zhang 23619a87c32fSHawking Zhang /*define for HEADER word*/ 23629a87c32fSHawking Zhang /*define for op field*/ 23639a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 23649a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF 23659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 23669a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) 23679a87c32fSHawking Zhang 23689a87c32fSHawking Zhang /*define for sub_op field*/ 23699a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 23709a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 23719a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 23729a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) 23739a87c32fSHawking Zhang 23749a87c32fSHawking Zhang /*define for detile field*/ 23759a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 23769a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 23779a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 23789a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) 23799a87c32fSHawking Zhang 23809a87c32fSHawking Zhang /*define for TILED_ADDR_LO word*/ 23819a87c32fSHawking Zhang /*define for tiled_addr_31_0 field*/ 23829a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 23839a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 23849a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 23859a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 23869a87c32fSHawking Zhang 23879a87c32fSHawking Zhang /*define for TILED_ADDR_HI word*/ 23889a87c32fSHawking Zhang /*define for tiled_addr_63_32 field*/ 23899a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 23909a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 23919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 23929a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 23939a87c32fSHawking Zhang 23949a87c32fSHawking Zhang /*define for DW_3 word*/ 23959a87c32fSHawking Zhang /*define for tiled_x field*/ 23969a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 23979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF 23989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 23999a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) 24009a87c32fSHawking Zhang 24019a87c32fSHawking Zhang /*define for tiled_y field*/ 24029a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 24039a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF 24049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 24059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) 24069a87c32fSHawking Zhang 24079a87c32fSHawking Zhang /*define for DW_4 word*/ 24089a87c32fSHawking Zhang /*define for tiled_z field*/ 24099a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 24109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF 24119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 24129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) 24139a87c32fSHawking Zhang 24149a87c32fSHawking Zhang /*define for width field*/ 24159a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 24169a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF 24179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 24189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) 24199a87c32fSHawking Zhang 24209a87c32fSHawking Zhang /*define for DW_5 word*/ 24219a87c32fSHawking Zhang /*define for height field*/ 24229a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 24239a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF 24249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 24259a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) 24269a87c32fSHawking Zhang 24279a87c32fSHawking Zhang /*define for depth field*/ 24289a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 24299a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF 24309a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 24319a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) 24329a87c32fSHawking Zhang 24339a87c32fSHawking Zhang /*define for DW_6 word*/ 24349a87c32fSHawking Zhang /*define for element_size field*/ 24359a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 24369a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 24379a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 24389a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) 24399a87c32fSHawking Zhang 24409a87c32fSHawking Zhang /*define for array_mode field*/ 24419a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 24429a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F 24439a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 24449a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) 24459a87c32fSHawking Zhang 24469a87c32fSHawking Zhang /*define for mit_mode field*/ 24479a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 24489a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 24499a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 24509a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) 24519a87c32fSHawking Zhang 24529a87c32fSHawking Zhang /*define for tilesplit_size field*/ 24539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 24549a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 24559a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 24569a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) 24579a87c32fSHawking Zhang 24589a87c32fSHawking Zhang /*define for bank_w field*/ 24599a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 24609a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 24619a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 24629a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) 24639a87c32fSHawking Zhang 24649a87c32fSHawking Zhang /*define for bank_h field*/ 24659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 24669a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 24679a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 24689a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) 24699a87c32fSHawking Zhang 24709a87c32fSHawking Zhang /*define for num_bank field*/ 24719a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 24729a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 24739a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 24749a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) 24759a87c32fSHawking Zhang 24769a87c32fSHawking Zhang /*define for mat_aspt field*/ 24779a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 24789a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 24799a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 24809a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) ((x & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) 24819a87c32fSHawking Zhang 24829a87c32fSHawking Zhang /*define for pipe_config field*/ 24839a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 24849a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F 24859a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 24869a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) 24879a87c32fSHawking Zhang 24889a87c32fSHawking Zhang /*define for LINEAR_ADDR_LO word*/ 24899a87c32fSHawking Zhang /*define for linear_addr_31_0 field*/ 24909a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 24919a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 24929a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 24939a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 24949a87c32fSHawking Zhang 24959a87c32fSHawking Zhang /*define for LINEAR_ADDR_HI word*/ 24969a87c32fSHawking Zhang /*define for linear_addr_63_32 field*/ 24979a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 24989a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 24999a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 25009a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 25019a87c32fSHawking Zhang 25029a87c32fSHawking Zhang /*define for DW_9 word*/ 25039a87c32fSHawking Zhang /*define for linear_x field*/ 25049a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 25059a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF 25069a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 25079a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) 25089a87c32fSHawking Zhang 25099a87c32fSHawking Zhang /*define for linear_y field*/ 25109a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 25119a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF 25129a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 25139a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) 25149a87c32fSHawking Zhang 25159a87c32fSHawking Zhang /*define for DW_10 word*/ 25169a87c32fSHawking Zhang /*define for linear_z field*/ 25179a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 25189a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF 25199a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 25209a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) 25219a87c32fSHawking Zhang 25229a87c32fSHawking Zhang /*define for linear_pitch field*/ 25239a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 25249a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF 25259a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 25269a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) 25279a87c32fSHawking Zhang 25289a87c32fSHawking Zhang /*define for DW_11 word*/ 25299a87c32fSHawking Zhang /*define for linear_slice_pitch field*/ 25309a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 25319a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 25329a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 25339a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) 25349a87c32fSHawking Zhang 25359a87c32fSHawking Zhang /*define for DW_12 word*/ 25369a87c32fSHawking Zhang /*define for rect_x field*/ 25379a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 25389a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF 25399a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 25409a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) 25419a87c32fSHawking Zhang 25429a87c32fSHawking Zhang /*define for rect_y field*/ 25439a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 25449a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF 25459a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 25469a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) 25479a87c32fSHawking Zhang 25489a87c32fSHawking Zhang /*define for DW_13 word*/ 25499a87c32fSHawking Zhang /*define for rect_z field*/ 25509a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 25519a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF 25529a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 25539a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) 25549a87c32fSHawking Zhang 25559a87c32fSHawking Zhang /*define for linear_sw field*/ 25569a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 25579a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 25589a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 25599a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) 25609a87c32fSHawking Zhang 25619a87c32fSHawking Zhang /*define for tile_sw field*/ 25629a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 25639a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 25649a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 25659a87c32fSHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) 25669a87c32fSHawking Zhang 25679a87c32fSHawking Zhang 25689a87c32fSHawking Zhang /* 25699a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COPY_STRUCT packet 25709a87c32fSHawking Zhang */ 25719a87c32fSHawking Zhang 25729a87c32fSHawking Zhang /*define for HEADER word*/ 25739a87c32fSHawking Zhang /*define for op field*/ 25749a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 25759a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 25769a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 25779a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 25789a87c32fSHawking Zhang 25799a87c32fSHawking Zhang /*define for sub_op field*/ 25809a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 25819a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 25829a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 25839a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 25849a87c32fSHawking Zhang 25859a87c32fSHawking Zhang /*define for tmz field*/ 25869a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 25879a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 25889a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 25899a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 25909a87c32fSHawking Zhang 25919a87c32fSHawking Zhang /*define for detile field*/ 25929a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 25939a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 25949a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 25959a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 25969a87c32fSHawking Zhang 25979a87c32fSHawking Zhang /*define for SB_ADDR_LO word*/ 25989a87c32fSHawking Zhang /*define for sb_addr_31_0 field*/ 25999a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 26009a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 26019a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 26029a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 26039a87c32fSHawking Zhang 26049a87c32fSHawking Zhang /*define for SB_ADDR_HI word*/ 26059a87c32fSHawking Zhang /*define for sb_addr_63_32 field*/ 26069a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 26079a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 26089a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 26099a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 26109a87c32fSHawking Zhang 26119a87c32fSHawking Zhang /*define for START_INDEX word*/ 26129a87c32fSHawking Zhang /*define for start_index field*/ 26139a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 26149a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 26159a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 26169a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 26179a87c32fSHawking Zhang 26189a87c32fSHawking Zhang /*define for COUNT word*/ 26199a87c32fSHawking Zhang /*define for count field*/ 26209a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 26219a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 26229a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 26239a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 26249a87c32fSHawking Zhang 26259a87c32fSHawking Zhang /*define for DW_5 word*/ 26269a87c32fSHawking Zhang /*define for stride field*/ 26279a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 26289a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 26299a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 26309a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 26319a87c32fSHawking Zhang 26329a87c32fSHawking Zhang /*define for linear_sw field*/ 26339a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 26349a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 26359a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 26369a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 26379a87c32fSHawking Zhang 26389a87c32fSHawking Zhang /*define for struct_sw field*/ 26399a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 26409a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 26419a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 26429a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 26439a87c32fSHawking Zhang 26449a87c32fSHawking Zhang /*define for LINEAR_ADDR_LO word*/ 26459a87c32fSHawking Zhang /*define for linear_addr_31_0 field*/ 26469a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 26479a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 26489a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 26499a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 26509a87c32fSHawking Zhang 26519a87c32fSHawking Zhang /*define for LINEAR_ADDR_HI word*/ 26529a87c32fSHawking Zhang /*define for linear_addr_63_32 field*/ 26539a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 26549a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 26559a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 26569a87c32fSHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 26579a87c32fSHawking Zhang 26589a87c32fSHawking Zhang 26599a87c32fSHawking Zhang /* 26609a87c32fSHawking Zhang ** Definitions for SDMA_PKT_WRITE_UNTILED packet 26619a87c32fSHawking Zhang */ 26629a87c32fSHawking Zhang 26639a87c32fSHawking Zhang /*define for HEADER word*/ 26649a87c32fSHawking Zhang /*define for op field*/ 26659a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 26669a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 26679a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 26689a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 26699a87c32fSHawking Zhang 26709a87c32fSHawking Zhang /*define for sub_op field*/ 26719a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 26729a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 26739a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 26749a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 26759a87c32fSHawking Zhang 26769a87c32fSHawking Zhang /*define for encrypt field*/ 26779a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 26789a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 26799a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 26809a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 26819a87c32fSHawking Zhang 26829a87c32fSHawking Zhang /*define for tmz field*/ 26839a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 26849a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 26859a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 26869a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 26879a87c32fSHawking Zhang 26889a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 26899a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 26909a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 26919a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 26929a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 26939a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 26949a87c32fSHawking Zhang 26959a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 26969a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 26979a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 26989a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 26999a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 27009a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 27019a87c32fSHawking Zhang 27029a87c32fSHawking Zhang /*define for DW_3 word*/ 27039a87c32fSHawking Zhang /*define for count field*/ 27049a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 27059a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 27069a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 27079a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 27089a87c32fSHawking Zhang 27099a87c32fSHawking Zhang /*define for sw field*/ 27109a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 27119a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 27129a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 27139a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 27149a87c32fSHawking Zhang 27159a87c32fSHawking Zhang /*define for DATA0 word*/ 27169a87c32fSHawking Zhang /*define for data0 field*/ 27179a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 27189a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 27199a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 27209a87c32fSHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 27219a87c32fSHawking Zhang 27229a87c32fSHawking Zhang 27239a87c32fSHawking Zhang /* 27249a87c32fSHawking Zhang ** Definitions for SDMA_PKT_WRITE_TILED packet 27259a87c32fSHawking Zhang */ 27269a87c32fSHawking Zhang 27279a87c32fSHawking Zhang /*define for HEADER word*/ 27289a87c32fSHawking Zhang /*define for op field*/ 27299a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 27309a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 27319a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 27329a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 27339a87c32fSHawking Zhang 27349a87c32fSHawking Zhang /*define for sub_op field*/ 27359a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 27369a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 27379a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 27389a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 27399a87c32fSHawking Zhang 27409a87c32fSHawking Zhang /*define for encrypt field*/ 27419a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 27429a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 27439a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 27449a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 27459a87c32fSHawking Zhang 27469a87c32fSHawking Zhang /*define for tmz field*/ 27479a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 27489a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 27499a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 27509a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 27519a87c32fSHawking Zhang 27529a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 27539a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 27549a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 27559a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 27569a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 27579a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 27589a87c32fSHawking Zhang 27599a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 27609a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 27619a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 27629a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 27639a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 27649a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 27659a87c32fSHawking Zhang 27669a87c32fSHawking Zhang /*define for DW_3 word*/ 27679a87c32fSHawking Zhang /*define for width field*/ 27689a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 27699a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 27709a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 27719a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 27729a87c32fSHawking Zhang 27739a87c32fSHawking Zhang /*define for DW_4 word*/ 27749a87c32fSHawking Zhang /*define for height field*/ 27759a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 27769a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 27779a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 27789a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 27799a87c32fSHawking Zhang 27809a87c32fSHawking Zhang /*define for depth field*/ 27819a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 27829a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF 27839a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 27849a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 27859a87c32fSHawking Zhang 27869a87c32fSHawking Zhang /*define for DW_5 word*/ 27879a87c32fSHawking Zhang /*define for element_size field*/ 27889a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 27899a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 27909a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 27919a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 27929a87c32fSHawking Zhang 27939a87c32fSHawking Zhang /*define for swizzle_mode field*/ 27949a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 27959a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 27969a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 27979a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 27989a87c32fSHawking Zhang 27999a87c32fSHawking Zhang /*define for dimension field*/ 28009a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 28019a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 28029a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 28039a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 28049a87c32fSHawking Zhang 28059a87c32fSHawking Zhang /*define for mip_max field*/ 28069a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 28079a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F 28089a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 28099a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) 28109a87c32fSHawking Zhang 28119a87c32fSHawking Zhang /*define for DW_6 word*/ 28129a87c32fSHawking Zhang /*define for x field*/ 28139a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 28149a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 28159a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 28169a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 28179a87c32fSHawking Zhang 28189a87c32fSHawking Zhang /*define for y field*/ 28199a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 28209a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 28219a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 28229a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 28239a87c32fSHawking Zhang 28249a87c32fSHawking Zhang /*define for DW_7 word*/ 28259a87c32fSHawking Zhang /*define for z field*/ 28269a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 28279a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF 28289a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 28299a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 28309a87c32fSHawking Zhang 28319a87c32fSHawking Zhang /*define for sw field*/ 28329a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 28339a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 28349a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 28359a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 28369a87c32fSHawking Zhang 28379a87c32fSHawking Zhang /*define for COUNT word*/ 28389a87c32fSHawking Zhang /*define for count field*/ 28399a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 28409a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 28419a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 28429a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 28439a87c32fSHawking Zhang 28449a87c32fSHawking Zhang /*define for DATA0 word*/ 28459a87c32fSHawking Zhang /*define for data0 field*/ 28469a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 28479a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 28489a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 28499a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 28509a87c32fSHawking Zhang 28519a87c32fSHawking Zhang 28529a87c32fSHawking Zhang /* 28539a87c32fSHawking Zhang ** Definitions for SDMA_PKT_WRITE_TILED_BC packet 28549a87c32fSHawking Zhang */ 28559a87c32fSHawking Zhang 28569a87c32fSHawking Zhang /*define for HEADER word*/ 28579a87c32fSHawking Zhang /*define for op field*/ 28589a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 28599a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF 28609a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 28619a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) 28629a87c32fSHawking Zhang 28639a87c32fSHawking Zhang /*define for sub_op field*/ 28649a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 28659a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF 28669a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 28679a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) 28689a87c32fSHawking Zhang 28699a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 28709a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 28719a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 28729a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 28739a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 28749a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) 28759a87c32fSHawking Zhang 28769a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 28779a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 28789a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 28799a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 28809a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 28819a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) 28829a87c32fSHawking Zhang 28839a87c32fSHawking Zhang /*define for DW_3 word*/ 28849a87c32fSHawking Zhang /*define for width field*/ 28859a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 28869a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF 28879a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 28889a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) 28899a87c32fSHawking Zhang 28909a87c32fSHawking Zhang /*define for DW_4 word*/ 28919a87c32fSHawking Zhang /*define for height field*/ 28929a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 28939a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF 28949a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 28959a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) 28969a87c32fSHawking Zhang 28979a87c32fSHawking Zhang /*define for depth field*/ 28989a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 28999a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF 29009a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 29019a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) 29029a87c32fSHawking Zhang 29039a87c32fSHawking Zhang /*define for DW_5 word*/ 29049a87c32fSHawking Zhang /*define for element_size field*/ 29059a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 29069a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 29079a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 29089a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) 29099a87c32fSHawking Zhang 29109a87c32fSHawking Zhang /*define for array_mode field*/ 29119a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 29129a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F 29139a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 29149a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) 29159a87c32fSHawking Zhang 29169a87c32fSHawking Zhang /*define for mit_mode field*/ 29179a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 29189a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 29199a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 29209a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) 29219a87c32fSHawking Zhang 29229a87c32fSHawking Zhang /*define for tilesplit_size field*/ 29239a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 29249a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 29259a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 29269a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) 29279a87c32fSHawking Zhang 29289a87c32fSHawking Zhang /*define for bank_w field*/ 29299a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 29309a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 29319a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 29329a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) 29339a87c32fSHawking Zhang 29349a87c32fSHawking Zhang /*define for bank_h field*/ 29359a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 29369a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 29379a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 29389a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) 29399a87c32fSHawking Zhang 29409a87c32fSHawking Zhang /*define for num_bank field*/ 29419a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 29429a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 29439a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 29449a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) 29459a87c32fSHawking Zhang 29469a87c32fSHawking Zhang /*define for mat_aspt field*/ 29479a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 29489a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 29499a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 29509a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) 29519a87c32fSHawking Zhang 29529a87c32fSHawking Zhang /*define for pipe_config field*/ 29539a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 29549a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F 29559a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 29569a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) 29579a87c32fSHawking Zhang 29589a87c32fSHawking Zhang /*define for DW_6 word*/ 29599a87c32fSHawking Zhang /*define for x field*/ 29609a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 29619a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF 29629a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 29639a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) 29649a87c32fSHawking Zhang 29659a87c32fSHawking Zhang /*define for y field*/ 29669a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 29679a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF 29689a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 29699a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) 29709a87c32fSHawking Zhang 29719a87c32fSHawking Zhang /*define for DW_7 word*/ 29729a87c32fSHawking Zhang /*define for z field*/ 29739a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 29749a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF 29759a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 29769a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) 29779a87c32fSHawking Zhang 29789a87c32fSHawking Zhang /*define for sw field*/ 29799a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 29809a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 29819a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 29829a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) 29839a87c32fSHawking Zhang 29849a87c32fSHawking Zhang /*define for COUNT word*/ 29859a87c32fSHawking Zhang /*define for count field*/ 29869a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 29879a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF 29889a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 29899a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) 29909a87c32fSHawking Zhang 29919a87c32fSHawking Zhang /*define for DATA0 word*/ 29929a87c32fSHawking Zhang /*define for data0 field*/ 29939a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 29949a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF 29959a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 29969a87c32fSHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) 29979a87c32fSHawking Zhang 29989a87c32fSHawking Zhang 29999a87c32fSHawking Zhang /* 30009a87c32fSHawking Zhang ** Definitions for SDMA_PKT_PTEPDE_COPY packet 30019a87c32fSHawking Zhang */ 30029a87c32fSHawking Zhang 30039a87c32fSHawking Zhang /*define for HEADER word*/ 30049a87c32fSHawking Zhang /*define for op field*/ 30059a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 30069a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 30079a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 30089a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 30099a87c32fSHawking Zhang 30109a87c32fSHawking Zhang /*define for sub_op field*/ 30119a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 30129a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 30139a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 30149a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 30159a87c32fSHawking Zhang 30169a87c32fSHawking Zhang /*define for tmz field*/ 30179a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 30189a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 30199a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 30209a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) 30219a87c32fSHawking Zhang 30229a87c32fSHawking Zhang /*define for ptepde_op field*/ 30239a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 30249a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 30259a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 30269a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 30279a87c32fSHawking Zhang 30289a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 30299a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 30309a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 30319a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 30329a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 30339a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 30349a87c32fSHawking Zhang 30359a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 30369a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 30379a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 30389a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 30399a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 30409a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 30419a87c32fSHawking Zhang 30429a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 30439a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 30449a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 30459a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 30469a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 30479a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 30489a87c32fSHawking Zhang 30499a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 30509a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 30519a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 30529a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 30539a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 30549a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 30559a87c32fSHawking Zhang 30569a87c32fSHawking Zhang /*define for MASK_DW0 word*/ 30579a87c32fSHawking Zhang /*define for mask_dw0 field*/ 30589a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 30599a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 30609a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 30619a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 30629a87c32fSHawking Zhang 30639a87c32fSHawking Zhang /*define for MASK_DW1 word*/ 30649a87c32fSHawking Zhang /*define for mask_dw1 field*/ 30659a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 30669a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 30679a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 30689a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 30699a87c32fSHawking Zhang 30709a87c32fSHawking Zhang /*define for COUNT word*/ 30719a87c32fSHawking Zhang /*define for count field*/ 30729a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 30739a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 30749a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 30759a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 30769a87c32fSHawking Zhang 30779a87c32fSHawking Zhang 30789a87c32fSHawking Zhang /* 30799a87c32fSHawking Zhang ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 30809a87c32fSHawking Zhang */ 30819a87c32fSHawking Zhang 30829a87c32fSHawking Zhang /*define for HEADER word*/ 30839a87c32fSHawking Zhang /*define for op field*/ 30849a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 30859a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 30869a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 30879a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 30889a87c32fSHawking Zhang 30899a87c32fSHawking Zhang /*define for sub_op field*/ 30909a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 30919a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 30929a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 30939a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 30949a87c32fSHawking Zhang 30959a87c32fSHawking Zhang /*define for pte_size field*/ 30969a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 30979a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 30989a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 30999a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 31009a87c32fSHawking Zhang 31019a87c32fSHawking Zhang /*define for direction field*/ 31029a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 31039a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 31049a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 31059a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 31069a87c32fSHawking Zhang 31079a87c32fSHawking Zhang /*define for ptepde_op field*/ 31089a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 31099a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 31109a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 31119a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 31129a87c32fSHawking Zhang 31139a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 31149a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 31159a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 31169a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 31179a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 31189a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 31199a87c32fSHawking Zhang 31209a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 31219a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 31229a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 31239a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 31249a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 31259a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 31269a87c32fSHawking Zhang 31279a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 31289a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 31299a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 31309a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 31319a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 31329a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 31339a87c32fSHawking Zhang 31349a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 31359a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 31369a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 31379a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 31389a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 31399a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 31409a87c32fSHawking Zhang 31419a87c32fSHawking Zhang /*define for MASK_BIT_FOR_DW word*/ 31429a87c32fSHawking Zhang /*define for mask_first_xfer field*/ 31439a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 31449a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 31459a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 31469a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 31479a87c32fSHawking Zhang 31489a87c32fSHawking Zhang /*define for mask_last_xfer field*/ 31499a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 31509a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 31519a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 31529a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 31539a87c32fSHawking Zhang 31549a87c32fSHawking Zhang /*define for COUNT_IN_32B_XFER word*/ 31559a87c32fSHawking Zhang /*define for count field*/ 31569a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 31579a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 31589a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 31599a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 31609a87c32fSHawking Zhang 31619a87c32fSHawking Zhang 31629a87c32fSHawking Zhang /* 31639a87c32fSHawking Zhang ** Definitions for SDMA_PKT_PTEPDE_RMW packet 31649a87c32fSHawking Zhang */ 31659a87c32fSHawking Zhang 31669a87c32fSHawking Zhang /*define for HEADER word*/ 31679a87c32fSHawking Zhang /*define for op field*/ 31689a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 31699a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 31709a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 31719a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 31729a87c32fSHawking Zhang 31739a87c32fSHawking Zhang /*define for sub_op field*/ 31749a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 31759a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 31769a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 31779a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 31789a87c32fSHawking Zhang 31799a87c32fSHawking Zhang /*define for mtype field*/ 31809a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 31819a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 31829a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 31839a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) 31849a87c32fSHawking Zhang 31859a87c32fSHawking Zhang /*define for gcc field*/ 31869a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 31879a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 31889a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 31899a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 31909a87c32fSHawking Zhang 31919a87c32fSHawking Zhang /*define for sys field*/ 31929a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 31939a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 31949a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 31959a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 31969a87c32fSHawking Zhang 31979a87c32fSHawking Zhang /*define for snp field*/ 31989a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 31999a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 32009a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 32019a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 32029a87c32fSHawking Zhang 32039a87c32fSHawking Zhang /*define for gpa field*/ 32049a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 32059a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 32069a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 32079a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 32089a87c32fSHawking Zhang 32099a87c32fSHawking Zhang /*define for l2_policy field*/ 32109a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 32119a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 32129a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 32139a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) 32149a87c32fSHawking Zhang 32159a87c32fSHawking Zhang /*define for ADDR_LO word*/ 32169a87c32fSHawking Zhang /*define for addr_31_0 field*/ 32179a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 32189a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 32199a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 32209a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 32219a87c32fSHawking Zhang 32229a87c32fSHawking Zhang /*define for ADDR_HI word*/ 32239a87c32fSHawking Zhang /*define for addr_63_32 field*/ 32249a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 32259a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 32269a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 32279a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 32289a87c32fSHawking Zhang 32299a87c32fSHawking Zhang /*define for MASK_LO word*/ 32309a87c32fSHawking Zhang /*define for mask_31_0 field*/ 32319a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 32329a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 32339a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 32349a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 32359a87c32fSHawking Zhang 32369a87c32fSHawking Zhang /*define for MASK_HI word*/ 32379a87c32fSHawking Zhang /*define for mask_63_32 field*/ 32389a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 32399a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 32409a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 32419a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 32429a87c32fSHawking Zhang 32439a87c32fSHawking Zhang /*define for VALUE_LO word*/ 32449a87c32fSHawking Zhang /*define for value_31_0 field*/ 32459a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 32469a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 32479a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 32489a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 32499a87c32fSHawking Zhang 32509a87c32fSHawking Zhang /*define for VALUE_HI word*/ 32519a87c32fSHawking Zhang /*define for value_63_32 field*/ 32529a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 32539a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 32549a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 32559a87c32fSHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 32569a87c32fSHawking Zhang 32579a87c32fSHawking Zhang 32589a87c32fSHawking Zhang /* 32599a87c32fSHawking Zhang ** Definitions for SDMA_PKT_WRITE_INCR packet 32609a87c32fSHawking Zhang */ 32619a87c32fSHawking Zhang 32629a87c32fSHawking Zhang /*define for HEADER word*/ 32639a87c32fSHawking Zhang /*define for op field*/ 32649a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 32659a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 32669a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 32679a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 32689a87c32fSHawking Zhang 32699a87c32fSHawking Zhang /*define for sub_op field*/ 32709a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 32719a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 32729a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 32739a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 32749a87c32fSHawking Zhang 32759a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 32769a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 32779a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 32789a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 32799a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 32809a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 32819a87c32fSHawking Zhang 32829a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 32839a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 32849a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 32859a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 32869a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 32879a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 32889a87c32fSHawking Zhang 32899a87c32fSHawking Zhang /*define for MASK_DW0 word*/ 32909a87c32fSHawking Zhang /*define for mask_dw0 field*/ 32919a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 32929a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 32939a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 32949a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 32959a87c32fSHawking Zhang 32969a87c32fSHawking Zhang /*define for MASK_DW1 word*/ 32979a87c32fSHawking Zhang /*define for mask_dw1 field*/ 32989a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 32999a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 33009a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 33019a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 33029a87c32fSHawking Zhang 33039a87c32fSHawking Zhang /*define for INIT_DW0 word*/ 33049a87c32fSHawking Zhang /*define for init_dw0 field*/ 33059a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 33069a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 33079a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 33089a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 33099a87c32fSHawking Zhang 33109a87c32fSHawking Zhang /*define for INIT_DW1 word*/ 33119a87c32fSHawking Zhang /*define for init_dw1 field*/ 33129a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 33139a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 33149a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 33159a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 33169a87c32fSHawking Zhang 33179a87c32fSHawking Zhang /*define for INCR_DW0 word*/ 33189a87c32fSHawking Zhang /*define for incr_dw0 field*/ 33199a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 33209a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 33219a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 33229a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 33239a87c32fSHawking Zhang 33249a87c32fSHawking Zhang /*define for INCR_DW1 word*/ 33259a87c32fSHawking Zhang /*define for incr_dw1 field*/ 33269a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 33279a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 33289a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 33299a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 33309a87c32fSHawking Zhang 33319a87c32fSHawking Zhang /*define for COUNT word*/ 33329a87c32fSHawking Zhang /*define for count field*/ 33339a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 33349a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 33359a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 33369a87c32fSHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 33379a87c32fSHawking Zhang 33389a87c32fSHawking Zhang 33399a87c32fSHawking Zhang /* 33409a87c32fSHawking Zhang ** Definitions for SDMA_PKT_INDIRECT packet 33419a87c32fSHawking Zhang */ 33429a87c32fSHawking Zhang 33439a87c32fSHawking Zhang /*define for HEADER word*/ 33449a87c32fSHawking Zhang /*define for op field*/ 33459a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 33469a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 33479a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 33489a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 33499a87c32fSHawking Zhang 33509a87c32fSHawking Zhang /*define for sub_op field*/ 33519a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 33529a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 33539a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 33549a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 33559a87c32fSHawking Zhang 33569a87c32fSHawking Zhang /*define for vmid field*/ 33579a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 33589a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 33599a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 33609a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 33619a87c32fSHawking Zhang 33629a87c32fSHawking Zhang /*define for priv field*/ 33639a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 33649a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 33659a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 33669a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) 33679a87c32fSHawking Zhang 33689a87c32fSHawking Zhang /*define for BASE_LO word*/ 33699a87c32fSHawking Zhang /*define for ib_base_31_0 field*/ 33709a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 33719a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 33729a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 33739a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 33749a87c32fSHawking Zhang 33759a87c32fSHawking Zhang /*define for BASE_HI word*/ 33769a87c32fSHawking Zhang /*define for ib_base_63_32 field*/ 33779a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 33789a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 33799a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 33809a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 33819a87c32fSHawking Zhang 33829a87c32fSHawking Zhang /*define for IB_SIZE word*/ 33839a87c32fSHawking Zhang /*define for ib_size field*/ 33849a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 33859a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 33869a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 33879a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 33889a87c32fSHawking Zhang 33899a87c32fSHawking Zhang /*define for CSA_ADDR_LO word*/ 33909a87c32fSHawking Zhang /*define for csa_addr_31_0 field*/ 33919a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 33929a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 33939a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 33949a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 33959a87c32fSHawking Zhang 33969a87c32fSHawking Zhang /*define for CSA_ADDR_HI word*/ 33979a87c32fSHawking Zhang /*define for csa_addr_63_32 field*/ 33989a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 33999a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 34009a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 34019a87c32fSHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 34029a87c32fSHawking Zhang 34039a87c32fSHawking Zhang 34049a87c32fSHawking Zhang /* 34059a87c32fSHawking Zhang ** Definitions for SDMA_PKT_SEMAPHORE packet 34069a87c32fSHawking Zhang */ 34079a87c32fSHawking Zhang 34089a87c32fSHawking Zhang /*define for HEADER word*/ 34099a87c32fSHawking Zhang /*define for op field*/ 34109a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 34119a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 34129a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 34139a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 34149a87c32fSHawking Zhang 34159a87c32fSHawking Zhang /*define for sub_op field*/ 34169a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 34179a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 34189a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 34199a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 34209a87c32fSHawking Zhang 34219a87c32fSHawking Zhang /*define for write_one field*/ 34229a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 34239a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 34249a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 34259a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 34269a87c32fSHawking Zhang 34279a87c32fSHawking Zhang /*define for signal field*/ 34289a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 34299a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 34309a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 34319a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 34329a87c32fSHawking Zhang 34339a87c32fSHawking Zhang /*define for mailbox field*/ 34349a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 34359a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 34369a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 34379a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 34389a87c32fSHawking Zhang 34399a87c32fSHawking Zhang /*define for ADDR_LO word*/ 34409a87c32fSHawking Zhang /*define for addr_31_0 field*/ 34419a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 34429a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 34439a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 34449a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 34459a87c32fSHawking Zhang 34469a87c32fSHawking Zhang /*define for ADDR_HI word*/ 34479a87c32fSHawking Zhang /*define for addr_63_32 field*/ 34489a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 34499a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 34509a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 34519a87c32fSHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 34529a87c32fSHawking Zhang 34539a87c32fSHawking Zhang 34549a87c32fSHawking Zhang /* 34559a87c32fSHawking Zhang ** Definitions for SDMA_PKT_FENCE packet 34569a87c32fSHawking Zhang */ 34579a87c32fSHawking Zhang 34589a87c32fSHawking Zhang /*define for HEADER word*/ 34599a87c32fSHawking Zhang /*define for op field*/ 34609a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_op_offset 0 34619a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 34629a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_op_shift 0 34639a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 34649a87c32fSHawking Zhang 34659a87c32fSHawking Zhang /*define for sub_op field*/ 34669a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 34679a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 34689a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 34699a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 34709a87c32fSHawking Zhang 34719a87c32fSHawking Zhang /*define for mtype field*/ 34729a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_mtype_offset 0 34739a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 34749a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_mtype_shift 16 34759a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) 34769a87c32fSHawking Zhang 34779a87c32fSHawking Zhang /*define for gcc field*/ 34789a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_gcc_offset 0 34799a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 34809a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_gcc_shift 19 34819a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) 34829a87c32fSHawking Zhang 34839a87c32fSHawking Zhang /*define for sys field*/ 34849a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_sys_offset 0 34859a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 34869a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_sys_shift 20 34879a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) 34889a87c32fSHawking Zhang 34899a87c32fSHawking Zhang /*define for snp field*/ 34909a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_snp_offset 0 34919a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 34929a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_snp_shift 22 34939a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) 34949a87c32fSHawking Zhang 34959a87c32fSHawking Zhang /*define for gpa field*/ 34969a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_gpa_offset 0 34979a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 34989a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_gpa_shift 23 34999a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) 35009a87c32fSHawking Zhang 35019a87c32fSHawking Zhang /*define for l2_policy field*/ 35029a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 35039a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 35049a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 35059a87c32fSHawking Zhang #define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) 35069a87c32fSHawking Zhang 35079a87c32fSHawking Zhang /*define for ADDR_LO word*/ 35089a87c32fSHawking Zhang /*define for addr_31_0 field*/ 35099a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 35109a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 35119a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 35129a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 35139a87c32fSHawking Zhang 35149a87c32fSHawking Zhang /*define for ADDR_HI word*/ 35159a87c32fSHawking Zhang /*define for addr_63_32 field*/ 35169a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 35179a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 35189a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 35199a87c32fSHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 35209a87c32fSHawking Zhang 35219a87c32fSHawking Zhang /*define for DATA word*/ 35229a87c32fSHawking Zhang /*define for data field*/ 35239a87c32fSHawking Zhang #define SDMA_PKT_FENCE_DATA_data_offset 3 35249a87c32fSHawking Zhang #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 35259a87c32fSHawking Zhang #define SDMA_PKT_FENCE_DATA_data_shift 0 35269a87c32fSHawking Zhang #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 35279a87c32fSHawking Zhang 35289a87c32fSHawking Zhang 35299a87c32fSHawking Zhang /* 35309a87c32fSHawking Zhang ** Definitions for SDMA_PKT_SRBM_WRITE packet 35319a87c32fSHawking Zhang */ 35329a87c32fSHawking Zhang 35339a87c32fSHawking Zhang /*define for HEADER word*/ 35349a87c32fSHawking Zhang /*define for op field*/ 35359a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 35369a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 35379a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 35389a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 35399a87c32fSHawking Zhang 35409a87c32fSHawking Zhang /*define for sub_op field*/ 35419a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 35429a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 35439a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 35449a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 35459a87c32fSHawking Zhang 35469a87c32fSHawking Zhang /*define for byte_en field*/ 35479a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 35489a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 35499a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 35509a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 35519a87c32fSHawking Zhang 35529a87c32fSHawking Zhang /*define for ADDR word*/ 35539a87c32fSHawking Zhang /*define for addr field*/ 35549a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 35559a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 35569a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 35579a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 35589a87c32fSHawking Zhang 35599a87c32fSHawking Zhang /*define for apertureid field*/ 35609a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 35619a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF 35629a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 35639a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) 35649a87c32fSHawking Zhang 35659a87c32fSHawking Zhang /*define for DATA word*/ 35669a87c32fSHawking Zhang /*define for data field*/ 35679a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 35689a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 35699a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 35709a87c32fSHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 35719a87c32fSHawking Zhang 35729a87c32fSHawking Zhang 35739a87c32fSHawking Zhang /* 35749a87c32fSHawking Zhang ** Definitions for SDMA_PKT_PRE_EXE packet 35759a87c32fSHawking Zhang */ 35769a87c32fSHawking Zhang 35779a87c32fSHawking Zhang /*define for HEADER word*/ 35789a87c32fSHawking Zhang /*define for op field*/ 35799a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 35809a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 35819a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 35829a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 35839a87c32fSHawking Zhang 35849a87c32fSHawking Zhang /*define for sub_op field*/ 35859a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 35869a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 35879a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 35889a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 35899a87c32fSHawking Zhang 35909a87c32fSHawking Zhang /*define for dev_sel field*/ 35919a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 35929a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 35939a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 35949a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 35959a87c32fSHawking Zhang 35969a87c32fSHawking Zhang /*define for EXEC_COUNT word*/ 35979a87c32fSHawking Zhang /*define for exec_count field*/ 35989a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 35999a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 36009a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 36019a87c32fSHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 36029a87c32fSHawking Zhang 36039a87c32fSHawking Zhang 36049a87c32fSHawking Zhang /* 36059a87c32fSHawking Zhang ** Definitions for SDMA_PKT_COND_EXE packet 36069a87c32fSHawking Zhang */ 36079a87c32fSHawking Zhang 36089a87c32fSHawking Zhang /*define for HEADER word*/ 36099a87c32fSHawking Zhang /*define for op field*/ 36109a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 36119a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 36129a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 36139a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 36149a87c32fSHawking Zhang 36159a87c32fSHawking Zhang /*define for sub_op field*/ 36169a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 36179a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 36189a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 36199a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 36209a87c32fSHawking Zhang 36219a87c32fSHawking Zhang /*define for ADDR_LO word*/ 36229a87c32fSHawking Zhang /*define for addr_31_0 field*/ 36239a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 36249a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 36259a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 36269a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 36279a87c32fSHawking Zhang 36289a87c32fSHawking Zhang /*define for ADDR_HI word*/ 36299a87c32fSHawking Zhang /*define for addr_63_32 field*/ 36309a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 36319a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 36329a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 36339a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 36349a87c32fSHawking Zhang 36359a87c32fSHawking Zhang /*define for REFERENCE word*/ 36369a87c32fSHawking Zhang /*define for reference field*/ 36379a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 36389a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 36399a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 36409a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 36419a87c32fSHawking Zhang 36429a87c32fSHawking Zhang /*define for EXEC_COUNT word*/ 36439a87c32fSHawking Zhang /*define for exec_count field*/ 36449a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 36459a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 36469a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 36479a87c32fSHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 36489a87c32fSHawking Zhang 36499a87c32fSHawking Zhang 36509a87c32fSHawking Zhang /* 36519a87c32fSHawking Zhang ** Definitions for SDMA_PKT_CONSTANT_FILL packet 36529a87c32fSHawking Zhang */ 36539a87c32fSHawking Zhang 36549a87c32fSHawking Zhang /*define for HEADER word*/ 36559a87c32fSHawking Zhang /*define for op field*/ 36569a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 36579a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 36589a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 36599a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 36609a87c32fSHawking Zhang 36619a87c32fSHawking Zhang /*define for sub_op field*/ 36629a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 36639a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 36649a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 36659a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 36669a87c32fSHawking Zhang 36679a87c32fSHawking Zhang /*define for sw field*/ 36689a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 36699a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 36709a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 36719a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 36729a87c32fSHawking Zhang 36739a87c32fSHawking Zhang /*define for fillsize field*/ 36749a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 36759a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 36769a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 36779a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 36789a87c32fSHawking Zhang 36799a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 36809a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 36819a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 36829a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 36839a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 36849a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 36859a87c32fSHawking Zhang 36869a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 36879a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 36889a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 36899a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 36909a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 36919a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 36929a87c32fSHawking Zhang 36939a87c32fSHawking Zhang /*define for DATA word*/ 36949a87c32fSHawking Zhang /*define for src_data_31_0 field*/ 36959a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 36969a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 36979a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 36989a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 36999a87c32fSHawking Zhang 37009a87c32fSHawking Zhang /*define for COUNT word*/ 37019a87c32fSHawking Zhang /*define for count field*/ 37029a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 37039a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 37049a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 37059a87c32fSHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 37069a87c32fSHawking Zhang 37079a87c32fSHawking Zhang 37089a87c32fSHawking Zhang /* 37099a87c32fSHawking Zhang ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 37109a87c32fSHawking Zhang */ 37119a87c32fSHawking Zhang 37129a87c32fSHawking Zhang /*define for HEADER word*/ 37139a87c32fSHawking Zhang /*define for op field*/ 37149a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 37159a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 37169a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 37179a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 37189a87c32fSHawking Zhang 37199a87c32fSHawking Zhang /*define for sub_op field*/ 37209a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 37219a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 37229a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 37239a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 37249a87c32fSHawking Zhang 37259a87c32fSHawking Zhang /*define for memlog_clr field*/ 37269a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 37279a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 37289a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 37299a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 37309a87c32fSHawking Zhang 37319a87c32fSHawking Zhang /*define for BYTE_STRIDE word*/ 37329a87c32fSHawking Zhang /*define for byte_stride field*/ 37339a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 37349a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 37359a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 37369a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 37379a87c32fSHawking Zhang 37389a87c32fSHawking Zhang /*define for DMA_COUNT word*/ 37399a87c32fSHawking Zhang /*define for dma_count field*/ 37409a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 37419a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 37429a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 37439a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 37449a87c32fSHawking Zhang 37459a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 37469a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 37479a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 37489a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 37499a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 37509a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 37519a87c32fSHawking Zhang 37529a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 37539a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 37549a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 37559a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 37569a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 37579a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 37589a87c32fSHawking Zhang 37599a87c32fSHawking Zhang /*define for BYTE_COUNT word*/ 37609a87c32fSHawking Zhang /*define for count field*/ 37619a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 37629a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 37639a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 37649a87c32fSHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 37659a87c32fSHawking Zhang 37669a87c32fSHawking Zhang 37679a87c32fSHawking Zhang /* 37689a87c32fSHawking Zhang ** Definitions for SDMA_PKT_POLL_REGMEM packet 37699a87c32fSHawking Zhang */ 37709a87c32fSHawking Zhang 37719a87c32fSHawking Zhang /*define for HEADER word*/ 37729a87c32fSHawking Zhang /*define for op field*/ 37739a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 37749a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 37759a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 37769a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 37779a87c32fSHawking Zhang 37789a87c32fSHawking Zhang /*define for sub_op field*/ 37799a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 37809a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 37819a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 37829a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 37839a87c32fSHawking Zhang 37849a87c32fSHawking Zhang /*define for hdp_flush field*/ 37859a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 37869a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 37879a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 37889a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 37899a87c32fSHawking Zhang 37909a87c32fSHawking Zhang /*define for func field*/ 37919a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 37929a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 37939a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 37949a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 37959a87c32fSHawking Zhang 37969a87c32fSHawking Zhang /*define for mem_poll field*/ 37979a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 37989a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 37999a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 38009a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 38019a87c32fSHawking Zhang 38029a87c32fSHawking Zhang /*define for ADDR_LO word*/ 38039a87c32fSHawking Zhang /*define for addr_31_0 field*/ 38049a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 38059a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 38069a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 38079a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 38089a87c32fSHawking Zhang 38099a87c32fSHawking Zhang /*define for ADDR_HI word*/ 38109a87c32fSHawking Zhang /*define for addr_63_32 field*/ 38119a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 38129a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 38139a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 38149a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 38159a87c32fSHawking Zhang 38169a87c32fSHawking Zhang /*define for VALUE word*/ 38179a87c32fSHawking Zhang /*define for value field*/ 38189a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 38199a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 38209a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 38219a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 38229a87c32fSHawking Zhang 38239a87c32fSHawking Zhang /*define for MASK word*/ 38249a87c32fSHawking Zhang /*define for mask field*/ 38259a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 38269a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 38279a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 38289a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 38299a87c32fSHawking Zhang 38309a87c32fSHawking Zhang /*define for DW5 word*/ 38319a87c32fSHawking Zhang /*define for interval field*/ 38329a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 38339a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 38349a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 38359a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 38369a87c32fSHawking Zhang 38379a87c32fSHawking Zhang /*define for retry_count field*/ 38389a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 38399a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 38409a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 38419a87c32fSHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 38429a87c32fSHawking Zhang 38439a87c32fSHawking Zhang 38449a87c32fSHawking Zhang /* 38459a87c32fSHawking Zhang ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 38469a87c32fSHawking Zhang */ 38479a87c32fSHawking Zhang 38489a87c32fSHawking Zhang /*define for HEADER word*/ 38499a87c32fSHawking Zhang /*define for op field*/ 38509a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 38519a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 38529a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 38539a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 38549a87c32fSHawking Zhang 38559a87c32fSHawking Zhang /*define for sub_op field*/ 38569a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 38579a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 38589a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 38599a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 38609a87c32fSHawking Zhang 38619a87c32fSHawking Zhang /*define for SRC_ADDR word*/ 38629a87c32fSHawking Zhang /*define for addr_31_2 field*/ 38639a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 38649a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 38659a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 38669a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 38679a87c32fSHawking Zhang 38689a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 38699a87c32fSHawking Zhang /*define for addr_31_0 field*/ 38709a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 38719a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 38729a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 38739a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 38749a87c32fSHawking Zhang 38759a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 38769a87c32fSHawking Zhang /*define for addr_63_32 field*/ 38779a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 38789a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 38799a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 38809a87c32fSHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 38819a87c32fSHawking Zhang 38829a87c32fSHawking Zhang 38839a87c32fSHawking Zhang /* 38849a87c32fSHawking Zhang ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 38859a87c32fSHawking Zhang */ 38869a87c32fSHawking Zhang 38879a87c32fSHawking Zhang /*define for HEADER word*/ 38889a87c32fSHawking Zhang /*define for op field*/ 38899a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 38909a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 38919a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 38929a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 38939a87c32fSHawking Zhang 38949a87c32fSHawking Zhang /*define for sub_op field*/ 38959a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 38969a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 38979a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 38989a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 38999a87c32fSHawking Zhang 39009a87c32fSHawking Zhang /*define for ea field*/ 39019a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 39029a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 39039a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 39049a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 39059a87c32fSHawking Zhang 39069a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 39079a87c32fSHawking Zhang /*define for addr_31_0 field*/ 39089a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 39099a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 39109a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 39119a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 39129a87c32fSHawking Zhang 39139a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 39149a87c32fSHawking Zhang /*define for addr_63_32 field*/ 39159a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 39169a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 39179a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 39189a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 39199a87c32fSHawking Zhang 39209a87c32fSHawking Zhang /*define for START_PAGE word*/ 39219a87c32fSHawking Zhang /*define for addr_31_4 field*/ 39229a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 39239a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 39249a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 39259a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 39269a87c32fSHawking Zhang 39279a87c32fSHawking Zhang /*define for PAGE_NUM word*/ 39289a87c32fSHawking Zhang /*define for page_num_31_0 field*/ 39299a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 39309a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 39319a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 39329a87c32fSHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 39339a87c32fSHawking Zhang 39349a87c32fSHawking Zhang 39359a87c32fSHawking Zhang /* 39369a87c32fSHawking Zhang ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 39379a87c32fSHawking Zhang */ 39389a87c32fSHawking Zhang 39399a87c32fSHawking Zhang /*define for HEADER word*/ 39409a87c32fSHawking Zhang /*define for op field*/ 39419a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 39429a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 39439a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 39449a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 39459a87c32fSHawking Zhang 39469a87c32fSHawking Zhang /*define for sub_op field*/ 39479a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 39489a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 39499a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 39509a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 39519a87c32fSHawking Zhang 39529a87c32fSHawking Zhang /*define for mode field*/ 39539a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 39549a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 39559a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 39569a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 39579a87c32fSHawking Zhang 39589a87c32fSHawking Zhang /*define for PATTERN word*/ 39599a87c32fSHawking Zhang /*define for pattern field*/ 39609a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 39619a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 39629a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 39639a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 39649a87c32fSHawking Zhang 39659a87c32fSHawking Zhang /*define for CMP0_ADDR_START_LO word*/ 39669a87c32fSHawking Zhang /*define for cmp0_start_31_0 field*/ 39679a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 39689a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 39699a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 39709a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 39719a87c32fSHawking Zhang 39729a87c32fSHawking Zhang /*define for CMP0_ADDR_START_HI word*/ 39739a87c32fSHawking Zhang /*define for cmp0_start_63_32 field*/ 39749a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 39759a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 39769a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 39779a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 39789a87c32fSHawking Zhang 39799a87c32fSHawking Zhang /*define for CMP0_ADDR_END_LO word*/ 39809a87c32fSHawking Zhang /*define for cmp1_end_31_0 field*/ 39819a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 39829a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 39839a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 39849a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) 39859a87c32fSHawking Zhang 39869a87c32fSHawking Zhang /*define for CMP0_ADDR_END_HI word*/ 39879a87c32fSHawking Zhang /*define for cmp1_end_63_32 field*/ 39889a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 39899a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 39909a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 39919a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) 39929a87c32fSHawking Zhang 39939a87c32fSHawking Zhang /*define for CMP1_ADDR_START_LO word*/ 39949a87c32fSHawking Zhang /*define for cmp1_start_31_0 field*/ 39959a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 39969a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 39979a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 39989a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 39999a87c32fSHawking Zhang 40009a87c32fSHawking Zhang /*define for CMP1_ADDR_START_HI word*/ 40019a87c32fSHawking Zhang /*define for cmp1_start_63_32 field*/ 40029a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 40039a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 40049a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 40059a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 40069a87c32fSHawking Zhang 40079a87c32fSHawking Zhang /*define for CMP1_ADDR_END_LO word*/ 40089a87c32fSHawking Zhang /*define for cmp1_end_31_0 field*/ 40099a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 40109a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 40119a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 40129a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 40139a87c32fSHawking Zhang 40149a87c32fSHawking Zhang /*define for CMP1_ADDR_END_HI word*/ 40159a87c32fSHawking Zhang /*define for cmp1_end_63_32 field*/ 40169a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 40179a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 40189a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 40199a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 40209a87c32fSHawking Zhang 40219a87c32fSHawking Zhang /*define for REC_ADDR_LO word*/ 40229a87c32fSHawking Zhang /*define for rec_31_0 field*/ 40239a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 40249a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 40259a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 40269a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 40279a87c32fSHawking Zhang 40289a87c32fSHawking Zhang /*define for REC_ADDR_HI word*/ 40299a87c32fSHawking Zhang /*define for rec_63_32 field*/ 40309a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 40319a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 40329a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 40339a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 40349a87c32fSHawking Zhang 40359a87c32fSHawking Zhang /*define for RESERVED word*/ 40369a87c32fSHawking Zhang /*define for reserved field*/ 40379a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 40389a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 40399a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 40409a87c32fSHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 40419a87c32fSHawking Zhang 40429a87c32fSHawking Zhang 40439a87c32fSHawking Zhang /* 40449a87c32fSHawking Zhang ** Definitions for SDMA_PKT_ATOMIC packet 40459a87c32fSHawking Zhang */ 40469a87c32fSHawking Zhang 40479a87c32fSHawking Zhang /*define for HEADER word*/ 40489a87c32fSHawking Zhang /*define for op field*/ 40499a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 40509a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 40519a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 40529a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 40539a87c32fSHawking Zhang 40549a87c32fSHawking Zhang /*define for loop field*/ 40559a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 40569a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 40579a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 40589a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 40599a87c32fSHawking Zhang 40609a87c32fSHawking Zhang /*define for tmz field*/ 40619a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 40629a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 40639a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 40649a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 40659a87c32fSHawking Zhang 40669a87c32fSHawking Zhang /*define for atomic_op field*/ 40679a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 40689a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 40699a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 40709a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 40719a87c32fSHawking Zhang 40729a87c32fSHawking Zhang /*define for ADDR_LO word*/ 40739a87c32fSHawking Zhang /*define for addr_31_0 field*/ 40749a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 40759a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 40769a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 40779a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 40789a87c32fSHawking Zhang 40799a87c32fSHawking Zhang /*define for ADDR_HI word*/ 40809a87c32fSHawking Zhang /*define for addr_63_32 field*/ 40819a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 40829a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 40839a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 40849a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 40859a87c32fSHawking Zhang 40869a87c32fSHawking Zhang /*define for SRC_DATA_LO word*/ 40879a87c32fSHawking Zhang /*define for src_data_31_0 field*/ 40889a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 40899a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 40909a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 40919a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 40929a87c32fSHawking Zhang 40939a87c32fSHawking Zhang /*define for SRC_DATA_HI word*/ 40949a87c32fSHawking Zhang /*define for src_data_63_32 field*/ 40959a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 40969a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 40979a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 40989a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 40999a87c32fSHawking Zhang 41009a87c32fSHawking Zhang /*define for CMP_DATA_LO word*/ 41019a87c32fSHawking Zhang /*define for cmp_data_31_0 field*/ 41029a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 41039a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 41049a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 41059a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 41069a87c32fSHawking Zhang 41079a87c32fSHawking Zhang /*define for CMP_DATA_HI word*/ 41089a87c32fSHawking Zhang /*define for cmp_data_63_32 field*/ 41099a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 41109a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 41119a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 41129a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 41139a87c32fSHawking Zhang 41149a87c32fSHawking Zhang /*define for LOOP_INTERVAL word*/ 41159a87c32fSHawking Zhang /*define for loop_interval field*/ 41169a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 41179a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 41189a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 41199a87c32fSHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 41209a87c32fSHawking Zhang 41219a87c32fSHawking Zhang 41229a87c32fSHawking Zhang /* 41239a87c32fSHawking Zhang ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 41249a87c32fSHawking Zhang */ 41259a87c32fSHawking Zhang 41269a87c32fSHawking Zhang /*define for HEADER word*/ 41279a87c32fSHawking Zhang /*define for op field*/ 41289a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 41299a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 41309a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 41319a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 41329a87c32fSHawking Zhang 41339a87c32fSHawking Zhang /*define for sub_op field*/ 41349a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 41359a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 41369a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 41379a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 41389a87c32fSHawking Zhang 41399a87c32fSHawking Zhang /*define for INIT_DATA_LO word*/ 41409a87c32fSHawking Zhang /*define for init_data_31_0 field*/ 41419a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 41429a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 41439a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 41449a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 41459a87c32fSHawking Zhang 41469a87c32fSHawking Zhang /*define for INIT_DATA_HI word*/ 41479a87c32fSHawking Zhang /*define for init_data_63_32 field*/ 41489a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 41499a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 41509a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 41519a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 41529a87c32fSHawking Zhang 41539a87c32fSHawking Zhang 41549a87c32fSHawking Zhang /* 41559a87c32fSHawking Zhang ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 41569a87c32fSHawking Zhang */ 41579a87c32fSHawking Zhang 41589a87c32fSHawking Zhang /*define for HEADER word*/ 41599a87c32fSHawking Zhang /*define for op field*/ 41609a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 41619a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 41629a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 41639a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 41649a87c32fSHawking Zhang 41659a87c32fSHawking Zhang /*define for sub_op field*/ 41669a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 41679a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 41689a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 41699a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 41709a87c32fSHawking Zhang 41719a87c32fSHawking Zhang /*define for WRITE_ADDR_LO word*/ 41729a87c32fSHawking Zhang /*define for write_addr_31_3 field*/ 41739a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 41749a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 41759a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 41769a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 41779a87c32fSHawking Zhang 41789a87c32fSHawking Zhang /*define for WRITE_ADDR_HI word*/ 41799a87c32fSHawking Zhang /*define for write_addr_63_32 field*/ 41809a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 41819a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 41829a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 41839a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 41849a87c32fSHawking Zhang 41859a87c32fSHawking Zhang 41869a87c32fSHawking Zhang /* 41879a87c32fSHawking Zhang ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 41889a87c32fSHawking Zhang */ 41899a87c32fSHawking Zhang 41909a87c32fSHawking Zhang /*define for HEADER word*/ 41919a87c32fSHawking Zhang /*define for op field*/ 41929a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 41939a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 41949a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 41959a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 41969a87c32fSHawking Zhang 41979a87c32fSHawking Zhang /*define for sub_op field*/ 41989a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 41999a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 42009a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 42019a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 42029a87c32fSHawking Zhang 42039a87c32fSHawking Zhang /*define for WRITE_ADDR_LO word*/ 42049a87c32fSHawking Zhang /*define for write_addr_31_3 field*/ 42059a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 42069a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 42079a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 42089a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 42099a87c32fSHawking Zhang 42109a87c32fSHawking Zhang /*define for WRITE_ADDR_HI word*/ 42119a87c32fSHawking Zhang /*define for write_addr_63_32 field*/ 42129a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 42139a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 42149a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 42159a87c32fSHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 42169a87c32fSHawking Zhang 42179a87c32fSHawking Zhang 42189a87c32fSHawking Zhang /* 42199a87c32fSHawking Zhang ** Definitions for SDMA_PKT_TRAP packet 42209a87c32fSHawking Zhang */ 42219a87c32fSHawking Zhang 42229a87c32fSHawking Zhang /*define for HEADER word*/ 42239a87c32fSHawking Zhang /*define for op field*/ 42249a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_op_offset 0 42259a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 42269a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_op_shift 0 42279a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 42289a87c32fSHawking Zhang 42299a87c32fSHawking Zhang /*define for sub_op field*/ 42309a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 42319a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 42329a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 42339a87c32fSHawking Zhang #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 42349a87c32fSHawking Zhang 42359a87c32fSHawking Zhang /*define for INT_CONTEXT word*/ 42369a87c32fSHawking Zhang /*define for int_context field*/ 42379a87c32fSHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 42389a87c32fSHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 42399a87c32fSHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 42409a87c32fSHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 42419a87c32fSHawking Zhang 42429a87c32fSHawking Zhang 42439a87c32fSHawking Zhang /* 42449a87c32fSHawking Zhang ** Definitions for SDMA_PKT_DUMMY_TRAP packet 42459a87c32fSHawking Zhang */ 42469a87c32fSHawking Zhang 42479a87c32fSHawking Zhang /*define for HEADER word*/ 42489a87c32fSHawking Zhang /*define for op field*/ 42499a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 42509a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 42519a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 42529a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 42539a87c32fSHawking Zhang 42549a87c32fSHawking Zhang /*define for sub_op field*/ 42559a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 42569a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 42579a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 42589a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 42599a87c32fSHawking Zhang 42609a87c32fSHawking Zhang /*define for INT_CONTEXT word*/ 42619a87c32fSHawking Zhang /*define for int_context field*/ 42629a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 42639a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 42649a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 42659a87c32fSHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 42669a87c32fSHawking Zhang 42679a87c32fSHawking Zhang 42689a87c32fSHawking Zhang /* 42699a87c32fSHawking Zhang ** Definitions for SDMA_PKT_GPUVM_INV packet 42709a87c32fSHawking Zhang */ 42719a87c32fSHawking Zhang 42729a87c32fSHawking Zhang /*define for HEADER word*/ 42739a87c32fSHawking Zhang /*define for op field*/ 42749a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 42759a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF 42769a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 42779a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) 42789a87c32fSHawking Zhang 42799a87c32fSHawking Zhang /*define for sub_op field*/ 42809a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 42819a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF 42829a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 42839a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) 42849a87c32fSHawking Zhang 42859a87c32fSHawking Zhang /*define for PAYLOAD1 word*/ 42869a87c32fSHawking Zhang /*define for per_vmid_inv_req field*/ 42879a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 42889a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF 42899a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 42909a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) 42919a87c32fSHawking Zhang 42929a87c32fSHawking Zhang /*define for flush_type field*/ 42939a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 42949a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 42959a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 42969a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) 42979a87c32fSHawking Zhang 42989a87c32fSHawking Zhang /*define for l2_ptes field*/ 42999a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 43009a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 43019a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 43029a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) 43039a87c32fSHawking Zhang 43049a87c32fSHawking Zhang /*define for l2_pde0 field*/ 43059a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 43069a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 43079a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 43089a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) 43099a87c32fSHawking Zhang 43109a87c32fSHawking Zhang /*define for l2_pde1 field*/ 43119a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 43129a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 43139a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 43149a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) 43159a87c32fSHawking Zhang 43169a87c32fSHawking Zhang /*define for l2_pde2 field*/ 43179a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 43189a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 43199a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 43209a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) 43219a87c32fSHawking Zhang 43229a87c32fSHawking Zhang /*define for l1_ptes field*/ 43239a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 43249a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 43259a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 43269a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) 43279a87c32fSHawking Zhang 43289a87c32fSHawking Zhang /*define for clr_protection_fault_status_addr field*/ 43299a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 43309a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 43319a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 43329a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) 43339a87c32fSHawking Zhang 43349a87c32fSHawking Zhang /*define for log_request field*/ 43359a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 43369a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 43379a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 43389a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) 43399a87c32fSHawking Zhang 43409a87c32fSHawking Zhang /*define for four_kilobytes field*/ 43419a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 43429a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 43439a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 43449a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) 43459a87c32fSHawking Zhang 43469a87c32fSHawking Zhang /*define for PAYLOAD2 word*/ 43479a87c32fSHawking Zhang /*define for s field*/ 43489a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 43499a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 43509a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 43519a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) 43529a87c32fSHawking Zhang 43539a87c32fSHawking Zhang /*define for page_va_42_12 field*/ 43549a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 43559a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF 43569a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 43579a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) 43589a87c32fSHawking Zhang 43599a87c32fSHawking Zhang /*define for PAYLOAD3 word*/ 43609a87c32fSHawking Zhang /*define for page_va_47_43 field*/ 43619a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 43629a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F 43639a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 43649a87c32fSHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) 43659a87c32fSHawking Zhang 43669a87c32fSHawking Zhang 43679a87c32fSHawking Zhang /* 43689a87c32fSHawking Zhang ** Definitions for SDMA_PKT_GCR_REQ packet 43699a87c32fSHawking Zhang */ 43709a87c32fSHawking Zhang 43719a87c32fSHawking Zhang /*define for HEADER word*/ 43729a87c32fSHawking Zhang /*define for op field*/ 43739a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 43749a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF 43759a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 43769a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) 43779a87c32fSHawking Zhang 43789a87c32fSHawking Zhang /*define for sub_op field*/ 43799a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 43809a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF 43819a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 43829a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) 43839a87c32fSHawking Zhang 43849a87c32fSHawking Zhang /*define for PAYLOAD1 word*/ 43859a87c32fSHawking Zhang /*define for base_va_31_7 field*/ 43869a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 43879a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF 43889a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 43899a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) 43909a87c32fSHawking Zhang 43919a87c32fSHawking Zhang /*define for PAYLOAD2 word*/ 43929a87c32fSHawking Zhang /*define for base_va_47_32 field*/ 43939a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 43949a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF 43959a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 43969a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) 43979a87c32fSHawking Zhang 43989a87c32fSHawking Zhang /*define for gcr_control_15_0 field*/ 43999a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 44009a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF 44019a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 44029a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) 44039a87c32fSHawking Zhang 44049a87c32fSHawking Zhang /*define for PAYLOAD3 word*/ 44059a87c32fSHawking Zhang /*define for gcr_control_18_16 field*/ 44069a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 44079a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 44089a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 44099a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) 44109a87c32fSHawking Zhang 44119a87c32fSHawking Zhang /*define for limit_va_31_7 field*/ 44129a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 44139a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF 44149a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 44159a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) 44169a87c32fSHawking Zhang 44179a87c32fSHawking Zhang /*define for PAYLOAD4 word*/ 44189a87c32fSHawking Zhang /*define for limit_va_47_32 field*/ 44199a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 44209a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF 44219a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 44229a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) 44239a87c32fSHawking Zhang 44249a87c32fSHawking Zhang /*define for vmid field*/ 44259a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 44269a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F 44279a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 44289a87c32fSHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) 44299a87c32fSHawking Zhang 44309a87c32fSHawking Zhang 44319a87c32fSHawking Zhang /* 44329a87c32fSHawking Zhang ** Definitions for SDMA_PKT_NOP packet 44339a87c32fSHawking Zhang */ 44349a87c32fSHawking Zhang 44359a87c32fSHawking Zhang /*define for HEADER word*/ 44369a87c32fSHawking Zhang /*define for op field*/ 44379a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_op_offset 0 44389a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 44399a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_op_shift 0 44409a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 44419a87c32fSHawking Zhang 44429a87c32fSHawking Zhang /*define for sub_op field*/ 44439a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 44449a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 44459a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 44469a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 44479a87c32fSHawking Zhang 44489a87c32fSHawking Zhang /*define for count field*/ 44499a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_count_offset 0 44509a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 44519a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_count_shift 16 44529a87c32fSHawking Zhang #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 44539a87c32fSHawking Zhang 44549a87c32fSHawking Zhang /*define for DATA0 word*/ 44559a87c32fSHawking Zhang /*define for data0 field*/ 44569a87c32fSHawking Zhang #define SDMA_PKT_NOP_DATA0_data0_offset 1 44579a87c32fSHawking Zhang #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 44589a87c32fSHawking Zhang #define SDMA_PKT_NOP_DATA0_data0_shift 0 44599a87c32fSHawking Zhang #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 44609a87c32fSHawking Zhang 44619a87c32fSHawking Zhang 44629a87c32fSHawking Zhang /* 44639a87c32fSHawking Zhang ** Definitions for SDMA_AQL_PKT_HEADER packet 44649a87c32fSHawking Zhang */ 44659a87c32fSHawking Zhang 44669a87c32fSHawking Zhang /*define for HEADER word*/ 44679a87c32fSHawking Zhang /*define for format field*/ 44689a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 44699a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 44709a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 44719a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 44729a87c32fSHawking Zhang 44739a87c32fSHawking Zhang /*define for barrier field*/ 44749a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 44759a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 44769a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 44779a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 44789a87c32fSHawking Zhang 44799a87c32fSHawking Zhang /*define for acquire_fence_scope field*/ 44809a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 44819a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 44829a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 44839a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 44849a87c32fSHawking Zhang 44859a87c32fSHawking Zhang /*define for release_fence_scope field*/ 44869a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 44879a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 44889a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 44899a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 44909a87c32fSHawking Zhang 44919a87c32fSHawking Zhang /*define for reserved field*/ 44929a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 44939a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 44949a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 44959a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 44969a87c32fSHawking Zhang 44979a87c32fSHawking Zhang /*define for op field*/ 44989a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 44999a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 45009a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 45019a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 45029a87c32fSHawking Zhang 45039a87c32fSHawking Zhang /*define for subop field*/ 45049a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 45059a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 45069a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 45079a87c32fSHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 45089a87c32fSHawking Zhang 45099a87c32fSHawking Zhang 45109a87c32fSHawking Zhang /* 45119a87c32fSHawking Zhang ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 45129a87c32fSHawking Zhang */ 45139a87c32fSHawking Zhang 45149a87c32fSHawking Zhang /*define for HEADER word*/ 45159a87c32fSHawking Zhang /*define for format field*/ 45169a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 45179a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 45189a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 45199a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 45209a87c32fSHawking Zhang 45219a87c32fSHawking Zhang /*define for barrier field*/ 45229a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 45239a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 45249a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 45259a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 45269a87c32fSHawking Zhang 45279a87c32fSHawking Zhang /*define for acquire_fence_scope field*/ 45289a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 45299a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 45309a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 45319a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 45329a87c32fSHawking Zhang 45339a87c32fSHawking Zhang /*define for release_fence_scope field*/ 45349a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 45359a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 45369a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 45379a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 45389a87c32fSHawking Zhang 45399a87c32fSHawking Zhang /*define for reserved field*/ 45409a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 45419a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 45429a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 45439a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 45449a87c32fSHawking Zhang 45459a87c32fSHawking Zhang /*define for op field*/ 45469a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 45479a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 45489a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 45499a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 45509a87c32fSHawking Zhang 45519a87c32fSHawking Zhang /*define for subop field*/ 45529a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 45539a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 45549a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 45559a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 45569a87c32fSHawking Zhang 45579a87c32fSHawking Zhang /*define for RESERVED_DW1 word*/ 45589a87c32fSHawking Zhang /*define for reserved_dw1 field*/ 45599a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 45609a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 45619a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 45629a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 45639a87c32fSHawking Zhang 45649a87c32fSHawking Zhang /*define for RETURN_ADDR_LO word*/ 45659a87c32fSHawking Zhang /*define for return_addr_31_0 field*/ 45669a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 45679a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 45689a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 45699a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 45709a87c32fSHawking Zhang 45719a87c32fSHawking Zhang /*define for RETURN_ADDR_HI word*/ 45729a87c32fSHawking Zhang /*define for return_addr_63_32 field*/ 45739a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 45749a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 45759a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 45769a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 45779a87c32fSHawking Zhang 45789a87c32fSHawking Zhang /*define for COUNT word*/ 45799a87c32fSHawking Zhang /*define for count field*/ 45809a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 45819a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 45829a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 45839a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 45849a87c32fSHawking Zhang 45859a87c32fSHawking Zhang /*define for PARAMETER word*/ 45869a87c32fSHawking Zhang /*define for dst_sw field*/ 45879a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 45889a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 45899a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 45909a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 45919a87c32fSHawking Zhang 45929a87c32fSHawking Zhang /*define for src_sw field*/ 45939a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 45949a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 45959a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 45969a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 45979a87c32fSHawking Zhang 45989a87c32fSHawking Zhang /*define for SRC_ADDR_LO word*/ 45999a87c32fSHawking Zhang /*define for src_addr_31_0 field*/ 46009a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 46019a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 46029a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 46039a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 46049a87c32fSHawking Zhang 46059a87c32fSHawking Zhang /*define for SRC_ADDR_HI word*/ 46069a87c32fSHawking Zhang /*define for src_addr_63_32 field*/ 46079a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 46089a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 46099a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 46109a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 46119a87c32fSHawking Zhang 46129a87c32fSHawking Zhang /*define for DST_ADDR_LO word*/ 46139a87c32fSHawking Zhang /*define for dst_addr_31_0 field*/ 46149a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 46159a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 46169a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 46179a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 46189a87c32fSHawking Zhang 46199a87c32fSHawking Zhang /*define for DST_ADDR_HI word*/ 46209a87c32fSHawking Zhang /*define for dst_addr_63_32 field*/ 46219a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 46229a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 46239a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 46249a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 46259a87c32fSHawking Zhang 46269a87c32fSHawking Zhang /*define for RESERVED_DW10 word*/ 46279a87c32fSHawking Zhang /*define for reserved_dw10 field*/ 46289a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 46299a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 46309a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 46319a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 46329a87c32fSHawking Zhang 46339a87c32fSHawking Zhang /*define for RESERVED_DW11 word*/ 46349a87c32fSHawking Zhang /*define for reserved_dw11 field*/ 46359a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 46369a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 46379a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 46389a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 46399a87c32fSHawking Zhang 46409a87c32fSHawking Zhang /*define for RESERVED_DW12 word*/ 46419a87c32fSHawking Zhang /*define for reserved_dw12 field*/ 46429a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 46439a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 46449a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 46459a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 46469a87c32fSHawking Zhang 46479a87c32fSHawking Zhang /*define for RESERVED_DW13 word*/ 46489a87c32fSHawking Zhang /*define for reserved_dw13 field*/ 46499a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 46509a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 46519a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 46529a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 46539a87c32fSHawking Zhang 46549a87c32fSHawking Zhang /*define for COMPLETION_SIGNAL_LO word*/ 46559a87c32fSHawking Zhang /*define for completion_signal_31_0 field*/ 46569a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 46579a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 46589a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 46599a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 46609a87c32fSHawking Zhang 46619a87c32fSHawking Zhang /*define for COMPLETION_SIGNAL_HI word*/ 46629a87c32fSHawking Zhang /*define for completion_signal_63_32 field*/ 46639a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 46649a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 46659a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 46669a87c32fSHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 46679a87c32fSHawking Zhang 46689a87c32fSHawking Zhang 46699a87c32fSHawking Zhang /* 46709a87c32fSHawking Zhang ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 46719a87c32fSHawking Zhang */ 46729a87c32fSHawking Zhang 46739a87c32fSHawking Zhang /*define for HEADER word*/ 46749a87c32fSHawking Zhang /*define for format field*/ 46759a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 46769a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 46779a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 46789a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 46799a87c32fSHawking Zhang 46809a87c32fSHawking Zhang /*define for barrier field*/ 46819a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 46829a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 46839a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 46849a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 46859a87c32fSHawking Zhang 46869a87c32fSHawking Zhang /*define for acquire_fence_scope field*/ 46879a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 46889a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 46899a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 46909a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 46919a87c32fSHawking Zhang 46929a87c32fSHawking Zhang /*define for release_fence_scope field*/ 46939a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 46949a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 46959a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 46969a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 46979a87c32fSHawking Zhang 46989a87c32fSHawking Zhang /*define for reserved field*/ 46999a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 47009a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 47019a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 47029a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 47039a87c32fSHawking Zhang 47049a87c32fSHawking Zhang /*define for op field*/ 47059a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 47069a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 47079a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 47089a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 47099a87c32fSHawking Zhang 47109a87c32fSHawking Zhang /*define for subop field*/ 47119a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 47129a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 47139a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 47149a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 47159a87c32fSHawking Zhang 47169a87c32fSHawking Zhang /*define for RESERVED_DW1 word*/ 47179a87c32fSHawking Zhang /*define for reserved_dw1 field*/ 47189a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 47199a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 47209a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 47219a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 47229a87c32fSHawking Zhang 47239a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_0_LO word*/ 47249a87c32fSHawking Zhang /*define for dependent_addr_0_31_0 field*/ 47259a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 47269a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 47279a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 47289a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 47299a87c32fSHawking Zhang 47309a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_0_HI word*/ 47319a87c32fSHawking Zhang /*define for dependent_addr_0_63_32 field*/ 47329a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 47339a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 47349a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 47359a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 47369a87c32fSHawking Zhang 47379a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_1_LO word*/ 47389a87c32fSHawking Zhang /*define for dependent_addr_1_31_0 field*/ 47399a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 47409a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 47419a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 47429a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 47439a87c32fSHawking Zhang 47449a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_1_HI word*/ 47459a87c32fSHawking Zhang /*define for dependent_addr_1_63_32 field*/ 47469a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 47479a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 47489a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 47499a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 47509a87c32fSHawking Zhang 47519a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_2_LO word*/ 47529a87c32fSHawking Zhang /*define for dependent_addr_2_31_0 field*/ 47539a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 47549a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 47559a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 47569a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 47579a87c32fSHawking Zhang 47589a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_2_HI word*/ 47599a87c32fSHawking Zhang /*define for dependent_addr_2_63_32 field*/ 47609a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 47619a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 47629a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 47639a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 47649a87c32fSHawking Zhang 47659a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_3_LO word*/ 47669a87c32fSHawking Zhang /*define for dependent_addr_3_31_0 field*/ 47679a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 47689a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 47699a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 47709a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 47719a87c32fSHawking Zhang 47729a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_3_HI word*/ 47739a87c32fSHawking Zhang /*define for dependent_addr_3_63_32 field*/ 47749a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 47759a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 47769a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 47779a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 47789a87c32fSHawking Zhang 47799a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_4_LO word*/ 47809a87c32fSHawking Zhang /*define for dependent_addr_4_31_0 field*/ 47819a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 47829a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 47839a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 47849a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 47859a87c32fSHawking Zhang 47869a87c32fSHawking Zhang /*define for DEPENDENT_ADDR_4_HI word*/ 47879a87c32fSHawking Zhang /*define for dependent_addr_4_63_32 field*/ 47889a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 47899a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 47909a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 47919a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 47929a87c32fSHawking Zhang 47939a87c32fSHawking Zhang /*define for RESERVED_DW12 word*/ 47949a87c32fSHawking Zhang /*define for reserved_dw12 field*/ 47959a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 47969a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 47979a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 47989a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) 47999a87c32fSHawking Zhang 48009a87c32fSHawking Zhang /*define for RESERVED_DW13 word*/ 48019a87c32fSHawking Zhang /*define for reserved_dw13 field*/ 48029a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 48039a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 48049a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 48059a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 48069a87c32fSHawking Zhang 48079a87c32fSHawking Zhang /*define for COMPLETION_SIGNAL_LO word*/ 48089a87c32fSHawking Zhang /*define for completion_signal_31_0 field*/ 48099a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 48109a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 48119a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 48129a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 48139a87c32fSHawking Zhang 48149a87c32fSHawking Zhang /*define for COMPLETION_SIGNAL_HI word*/ 48159a87c32fSHawking Zhang /*define for completion_signal_63_32 field*/ 48169a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 48179a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 48189a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 48199a87c32fSHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 48209a87c32fSHawking Zhang 48219a87c32fSHawking Zhang 48229a87c32fSHawking Zhang #endif /* __NAVI10_SDMA_PKT_OPEN_H_ */ 4823