190df1d55SAlex Deucher /* 290df1d55SAlex Deucher * Copyright (C) 2016 Advanced Micro Devices, Inc. 390df1d55SAlex Deucher * 490df1d55SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 590df1d55SAlex Deucher * copy of this software and associated documentation files (the "Software"), 690df1d55SAlex Deucher * to deal in the Software without restriction, including without limitation 790df1d55SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 890df1d55SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 990df1d55SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1090df1d55SAlex Deucher * 1190df1d55SAlex Deucher * The above copyright notice and this permission notice shall be included 1290df1d55SAlex Deucher * in all copies or substantial portions of the Software. 1390df1d55SAlex Deucher * 1490df1d55SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1590df1d55SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1690df1d55SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1790df1d55SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 1890df1d55SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1990df1d55SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2090df1d55SAlex Deucher * 2190df1d55SAlex Deucher */ 2290df1d55SAlex Deucher 2390df1d55SAlex Deucher #ifndef __VEGA10_SDMA_PKT_OPEN_H_ 2490df1d55SAlex Deucher #define __VEGA10_SDMA_PKT_OPEN_H_ 2590df1d55SAlex Deucher 2690df1d55SAlex Deucher #define SDMA_OP_NOP 0 2790df1d55SAlex Deucher #define SDMA_OP_COPY 1 2890df1d55SAlex Deucher #define SDMA_OP_WRITE 2 2990df1d55SAlex Deucher #define SDMA_OP_INDIRECT 4 3090df1d55SAlex Deucher #define SDMA_OP_FENCE 5 3190df1d55SAlex Deucher #define SDMA_OP_TRAP 6 3290df1d55SAlex Deucher #define SDMA_OP_SEM 7 3390df1d55SAlex Deucher #define SDMA_OP_POLL_REGMEM 8 3490df1d55SAlex Deucher #define SDMA_OP_COND_EXE 9 3590df1d55SAlex Deucher #define SDMA_OP_ATOMIC 10 3690df1d55SAlex Deucher #define SDMA_OP_CONST_FILL 11 3790df1d55SAlex Deucher #define SDMA_OP_PTEPDE 12 3890df1d55SAlex Deucher #define SDMA_OP_TIMESTAMP 13 3990df1d55SAlex Deucher #define SDMA_OP_SRBM_WRITE 14 4090df1d55SAlex Deucher #define SDMA_OP_PRE_EXE 15 4190df1d55SAlex Deucher #define SDMA_OP_DUMMY_TRAP 16 4290df1d55SAlex Deucher #define SDMA_SUBOP_TIMESTAMP_SET 0 4390df1d55SAlex Deucher #define SDMA_SUBOP_TIMESTAMP_GET 1 4490df1d55SAlex Deucher #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 4590df1d55SAlex Deucher #define SDMA_SUBOP_COPY_LINEAR 0 4690df1d55SAlex Deucher #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 4790df1d55SAlex Deucher #define SDMA_SUBOP_COPY_TILED 1 4890df1d55SAlex Deucher #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 4990df1d55SAlex Deucher #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 5090df1d55SAlex Deucher #define SDMA_SUBOP_COPY_SOA 3 5190df1d55SAlex Deucher #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 5290df1d55SAlex Deucher #define SDMA_SUBOP_COPY_LINEAR_PHY 8 5390df1d55SAlex Deucher #define SDMA_SUBOP_WRITE_LINEAR 0 5490df1d55SAlex Deucher #define SDMA_SUBOP_WRITE_TILED 1 5590df1d55SAlex Deucher #define SDMA_SUBOP_PTEPDE_GEN 0 5690df1d55SAlex Deucher #define SDMA_SUBOP_PTEPDE_COPY 1 5790df1d55SAlex Deucher #define SDMA_SUBOP_PTEPDE_RMW 2 5890df1d55SAlex Deucher #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 5990df1d55SAlex Deucher #define SDMA_SUBOP_DATA_FILL_MULTI 1 6090df1d55SAlex Deucher #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 6190df1d55SAlex Deucher #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 6290df1d55SAlex Deucher #define SDMA_SUBOP_POLL_MEM_VERIFY 3 6390df1d55SAlex Deucher #define HEADER_AGENT_DISPATCH 4 6490df1d55SAlex Deucher #define HEADER_BARRIER 5 6590df1d55SAlex Deucher #define SDMA_OP_AQL_COPY 0 6690df1d55SAlex Deucher #define SDMA_OP_AQL_BARRIER_OR 0 6790df1d55SAlex Deucher 6890df1d55SAlex Deucher /*define for op field*/ 6990df1d55SAlex Deucher #define SDMA_PKT_HEADER_op_offset 0 7090df1d55SAlex Deucher #define SDMA_PKT_HEADER_op_mask 0x000000FF 7190df1d55SAlex Deucher #define SDMA_PKT_HEADER_op_shift 0 7290df1d55SAlex Deucher #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 7390df1d55SAlex Deucher 7490df1d55SAlex Deucher /*define for sub_op field*/ 7590df1d55SAlex Deucher #define SDMA_PKT_HEADER_sub_op_offset 0 7690df1d55SAlex Deucher #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 7790df1d55SAlex Deucher #define SDMA_PKT_HEADER_sub_op_shift 8 7890df1d55SAlex Deucher #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 7990df1d55SAlex Deucher 8090df1d55SAlex Deucher 8190df1d55SAlex Deucher /* 8290df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_LINEAR packet 8390df1d55SAlex Deucher */ 8490df1d55SAlex Deucher 8590df1d55SAlex Deucher /*define for HEADER word*/ 8690df1d55SAlex Deucher /*define for op field*/ 8790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 8890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 8990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 9090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 9190df1d55SAlex Deucher 9290df1d55SAlex Deucher /*define for sub_op field*/ 9390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 9490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 9590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 9690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 9790df1d55SAlex Deucher 9890df1d55SAlex Deucher /*define for encrypt field*/ 9990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 10090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 10190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 10290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 10390df1d55SAlex Deucher 10490df1d55SAlex Deucher /*define for tmz field*/ 10590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 10690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 10790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 10890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 10990df1d55SAlex Deucher 11090df1d55SAlex Deucher /*define for broadcast field*/ 11190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 11290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 11390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 11490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 11590df1d55SAlex Deucher 11690df1d55SAlex Deucher /*define for COUNT word*/ 11790df1d55SAlex Deucher /*define for count field*/ 11890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 11990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 12090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 12190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 12290df1d55SAlex Deucher 12390df1d55SAlex Deucher /*define for PARAMETER word*/ 12490df1d55SAlex Deucher /*define for dst_sw field*/ 12590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 12690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 12790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 12890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 12990df1d55SAlex Deucher 13090df1d55SAlex Deucher /*define for src_sw field*/ 13190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 13290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 13390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 13490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 13590df1d55SAlex Deucher 13690df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 13790df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 13890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 13990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 14090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 14190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 14290df1d55SAlex Deucher 14390df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 14490df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 14590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 14690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 14790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 14890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 14990df1d55SAlex Deucher 15090df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 15190df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 15290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 15390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 15490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 15590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 15690df1d55SAlex Deucher 15790df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 15890df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 15990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 16090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 16190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 16290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 16390df1d55SAlex Deucher 16490df1d55SAlex Deucher 16590df1d55SAlex Deucher /* 16690df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 16790df1d55SAlex Deucher */ 16890df1d55SAlex Deucher 16990df1d55SAlex Deucher /*define for HEADER word*/ 17090df1d55SAlex Deucher /*define for op field*/ 17190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 17290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 17390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 17490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 17590df1d55SAlex Deucher 17690df1d55SAlex Deucher /*define for sub_op field*/ 17790df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 17890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 17990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 18090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 18190df1d55SAlex Deucher 18290df1d55SAlex Deucher /*define for tmz field*/ 18390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 18490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 18590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 18690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 18790df1d55SAlex Deucher 18890df1d55SAlex Deucher /*define for all field*/ 18990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 19090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 19190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 19290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 19390df1d55SAlex Deucher 19490df1d55SAlex Deucher /*define for COUNT word*/ 19590df1d55SAlex Deucher /*define for count field*/ 19690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 19790df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 19890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 19990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 20090df1d55SAlex Deucher 20190df1d55SAlex Deucher /*define for PARAMETER word*/ 20290df1d55SAlex Deucher /*define for dst_sw field*/ 20390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 20490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 20590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 20690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 20790df1d55SAlex Deucher 20890df1d55SAlex Deucher /*define for dst_gcc field*/ 20990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 21090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 21190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 21290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 21390df1d55SAlex Deucher 21490df1d55SAlex Deucher /*define for dst_sys field*/ 21590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 21690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 21790df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 21890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 21990df1d55SAlex Deucher 22090df1d55SAlex Deucher /*define for dst_snoop field*/ 22190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 22290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 22390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 22490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 22590df1d55SAlex Deucher 22690df1d55SAlex Deucher /*define for dst_gpa field*/ 22790df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 22890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 22990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 23090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 23190df1d55SAlex Deucher 23290df1d55SAlex Deucher /*define for src_sw field*/ 23390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 23490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 23590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 23690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 23790df1d55SAlex Deucher 23890df1d55SAlex Deucher /*define for src_sys field*/ 23990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 24090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 24190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 24290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 24390df1d55SAlex Deucher 24490df1d55SAlex Deucher /*define for src_snoop field*/ 24590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 24690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 24790df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 24890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 24990df1d55SAlex Deucher 25090df1d55SAlex Deucher /*define for src_gpa field*/ 25190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 25290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 25390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 25490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 25590df1d55SAlex Deucher 25690df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 25790df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 25890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 25990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 26090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 26190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 26290df1d55SAlex Deucher 26390df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 26490df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 26590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 26690df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 26790df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 26890df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 26990df1d55SAlex Deucher 27090df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 27190df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 27290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 27390df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 27490df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 27590df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 27690df1d55SAlex Deucher 27790df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 27890df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 27990df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 28090df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 28190df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 28290df1d55SAlex Deucher #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 28390df1d55SAlex Deucher 28490df1d55SAlex Deucher 28590df1d55SAlex Deucher /* 28690df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 28790df1d55SAlex Deucher */ 28890df1d55SAlex Deucher 28990df1d55SAlex Deucher /*define for HEADER word*/ 29090df1d55SAlex Deucher /*define for op field*/ 29190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 29290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 29390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 29490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 29590df1d55SAlex Deucher 29690df1d55SAlex Deucher /*define for sub_op field*/ 29790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 29890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 29990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 30090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 30190df1d55SAlex Deucher 30290df1d55SAlex Deucher /*define for tmz field*/ 30390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 30490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 30590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 30690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 30790df1d55SAlex Deucher 30890df1d55SAlex Deucher /*define for COUNT word*/ 30990df1d55SAlex Deucher /*define for count field*/ 31090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 31190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 31290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 31390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 31490df1d55SAlex Deucher 31590df1d55SAlex Deucher /*define for PARAMETER word*/ 31690df1d55SAlex Deucher /*define for dst_sw field*/ 31790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 31890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 31990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 32090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 32190df1d55SAlex Deucher 32290df1d55SAlex Deucher /*define for dst_gcc field*/ 32390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 32490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 32590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 32690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 32790df1d55SAlex Deucher 32890df1d55SAlex Deucher /*define for dst_sys field*/ 32990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 33090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 33190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 33290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 33390df1d55SAlex Deucher 33490df1d55SAlex Deucher /*define for dst_log field*/ 33590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 33690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 33790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 33890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 33990df1d55SAlex Deucher 34090df1d55SAlex Deucher /*define for dst_snoop field*/ 34190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 34290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 34390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 34490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 34590df1d55SAlex Deucher 34690df1d55SAlex Deucher /*define for dst_gpa field*/ 34790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 34890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 34990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 35090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 35190df1d55SAlex Deucher 35290df1d55SAlex Deucher /*define for src_sw field*/ 35390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 35490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 35590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 35690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 35790df1d55SAlex Deucher 35890df1d55SAlex Deucher /*define for src_gcc field*/ 35990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 36090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 36190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 36290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 36390df1d55SAlex Deucher 36490df1d55SAlex Deucher /*define for src_sys field*/ 36590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 36690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 36790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 36890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 36990df1d55SAlex Deucher 37090df1d55SAlex Deucher /*define for src_snoop field*/ 37190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 37290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 37390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 37490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 37590df1d55SAlex Deucher 37690df1d55SAlex Deucher /*define for src_gpa field*/ 37790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 37890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 37990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 38090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 38190df1d55SAlex Deucher 38290df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 38390df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 38490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 38590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 38690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 38790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 38890df1d55SAlex Deucher 38990df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 39090df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 39190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 39290df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 39390df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 39490df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 39590df1d55SAlex Deucher 39690df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 39790df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 39890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 39990df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 40090df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 40190df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 40290df1d55SAlex Deucher 40390df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 40490df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 40590df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 40690df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 40790df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 40890df1d55SAlex Deucher #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 40990df1d55SAlex Deucher 41090df1d55SAlex Deucher 41190df1d55SAlex Deucher /* 41290df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 41390df1d55SAlex Deucher */ 41490df1d55SAlex Deucher 41590df1d55SAlex Deucher /*define for HEADER word*/ 41690df1d55SAlex Deucher /*define for op field*/ 41790df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 41890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 41990df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 42090df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 42190df1d55SAlex Deucher 42290df1d55SAlex Deucher /*define for sub_op field*/ 42390df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 42490df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 42590df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 42690df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 42790df1d55SAlex Deucher 42890df1d55SAlex Deucher /*define for encrypt field*/ 42990df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 43090df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 43190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 43290df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 43390df1d55SAlex Deucher 43490df1d55SAlex Deucher /*define for tmz field*/ 43590df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 43690df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 43790df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 43890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 43990df1d55SAlex Deucher 44090df1d55SAlex Deucher /*define for broadcast field*/ 44190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 44290df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 44390df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 44490df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 44590df1d55SAlex Deucher 44690df1d55SAlex Deucher /*define for COUNT word*/ 44790df1d55SAlex Deucher /*define for count field*/ 44890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 44990df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 45090df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 45190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 45290df1d55SAlex Deucher 45390df1d55SAlex Deucher /*define for PARAMETER word*/ 45490df1d55SAlex Deucher /*define for dst2_sw field*/ 45590df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 45690df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 45790df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 45890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 45990df1d55SAlex Deucher 46090df1d55SAlex Deucher /*define for dst1_sw field*/ 46190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 46290df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 46390df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 46490df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 46590df1d55SAlex Deucher 46690df1d55SAlex Deucher /*define for src_sw field*/ 46790df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 46890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 46990df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 47090df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 47190df1d55SAlex Deucher 47290df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 47390df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 47490df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 47590df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 47690df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 47790df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 47890df1d55SAlex Deucher 47990df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 48090df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 48190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 48290df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 48390df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 48490df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 48590df1d55SAlex Deucher 48690df1d55SAlex Deucher /*define for DST1_ADDR_LO word*/ 48790df1d55SAlex Deucher /*define for dst1_addr_31_0 field*/ 48890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 48990df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 49090df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 49190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 49290df1d55SAlex Deucher 49390df1d55SAlex Deucher /*define for DST1_ADDR_HI word*/ 49490df1d55SAlex Deucher /*define for dst1_addr_63_32 field*/ 49590df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 49690df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 49790df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 49890df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 49990df1d55SAlex Deucher 50090df1d55SAlex Deucher /*define for DST2_ADDR_LO word*/ 50190df1d55SAlex Deucher /*define for dst2_addr_31_0 field*/ 50290df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 50390df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 50490df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 50590df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 50690df1d55SAlex Deucher 50790df1d55SAlex Deucher /*define for DST2_ADDR_HI word*/ 50890df1d55SAlex Deucher /*define for dst2_addr_63_32 field*/ 50990df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 51090df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 51190df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 51290df1d55SAlex Deucher #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 51390df1d55SAlex Deucher 51490df1d55SAlex Deucher 51590df1d55SAlex Deucher /* 51690df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 51790df1d55SAlex Deucher */ 51890df1d55SAlex Deucher 51990df1d55SAlex Deucher /*define for HEADER word*/ 52090df1d55SAlex Deucher /*define for op field*/ 52190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 52290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 52390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 52490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 52590df1d55SAlex Deucher 52690df1d55SAlex Deucher /*define for sub_op field*/ 52790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 52890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 52990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 53090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 53190df1d55SAlex Deucher 53290df1d55SAlex Deucher /*define for tmz field*/ 53390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 53490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 53590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 53690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 53790df1d55SAlex Deucher 53890df1d55SAlex Deucher /*define for elementsize field*/ 53990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 54090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 54190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 54290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 54390df1d55SAlex Deucher 54490df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 54590df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 54690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 54790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 54890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 54990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 55090df1d55SAlex Deucher 55190df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 55290df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 55390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 55490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 55590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 55690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 55790df1d55SAlex Deucher 55890df1d55SAlex Deucher /*define for DW_3 word*/ 55990df1d55SAlex Deucher /*define for src_x field*/ 56090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 56190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 56290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 56390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 56490df1d55SAlex Deucher 56590df1d55SAlex Deucher /*define for src_y field*/ 56690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 56790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 56890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 56990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 57090df1d55SAlex Deucher 57190df1d55SAlex Deucher /*define for DW_4 word*/ 57290df1d55SAlex Deucher /*define for src_z field*/ 57390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 57490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF 57590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 57690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 57790df1d55SAlex Deucher 57890df1d55SAlex Deucher /*define for src_pitch field*/ 57990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 58090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 58190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 58290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 58390df1d55SAlex Deucher 58490df1d55SAlex Deucher /*define for DW_5 word*/ 58590df1d55SAlex Deucher /*define for src_slice_pitch field*/ 58690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 58790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 58890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 58990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 59090df1d55SAlex Deucher 59190df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 59290df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 59390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 59490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 59590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 59690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 59790df1d55SAlex Deucher 59890df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 59990df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 60090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 60190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 60290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 60390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 60490df1d55SAlex Deucher 60590df1d55SAlex Deucher /*define for DW_8 word*/ 60690df1d55SAlex Deucher /*define for dst_x field*/ 60790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 60890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 60990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 61090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 61190df1d55SAlex Deucher 61290df1d55SAlex Deucher /*define for dst_y field*/ 61390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 61490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 61590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 61690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 61790df1d55SAlex Deucher 61890df1d55SAlex Deucher /*define for DW_9 word*/ 61990df1d55SAlex Deucher /*define for dst_z field*/ 62090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 62190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF 62290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 62390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 62490df1d55SAlex Deucher 62590df1d55SAlex Deucher /*define for dst_pitch field*/ 62690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 62790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 62890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 62990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 63090df1d55SAlex Deucher 63190df1d55SAlex Deucher /*define for DW_10 word*/ 63290df1d55SAlex Deucher /*define for dst_slice_pitch field*/ 63390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 63490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 63590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 63690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 63790df1d55SAlex Deucher 63890df1d55SAlex Deucher /*define for DW_11 word*/ 63990df1d55SAlex Deucher /*define for rect_x field*/ 64090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 64190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 64290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 64390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 64490df1d55SAlex Deucher 64590df1d55SAlex Deucher /*define for rect_y field*/ 64690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 64790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 64890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 64990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 65090df1d55SAlex Deucher 65190df1d55SAlex Deucher /*define for DW_12 word*/ 65290df1d55SAlex Deucher /*define for rect_z field*/ 65390df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 65490df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF 65590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 65690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 65790df1d55SAlex Deucher 65890df1d55SAlex Deucher /*define for dst_sw field*/ 65990df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 66090df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 66190df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 66290df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 66390df1d55SAlex Deucher 66490df1d55SAlex Deucher /*define for src_sw field*/ 66590df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 66690df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 66790df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 66890df1d55SAlex Deucher #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 66990df1d55SAlex Deucher 67090df1d55SAlex Deucher 67190df1d55SAlex Deucher /* 67290df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_TILED packet 67390df1d55SAlex Deucher */ 67490df1d55SAlex Deucher 67590df1d55SAlex Deucher /*define for HEADER word*/ 67690df1d55SAlex Deucher /*define for op field*/ 67790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 67890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 67990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 68090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 68190df1d55SAlex Deucher 68290df1d55SAlex Deucher /*define for sub_op field*/ 68390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 68490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 68590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 68690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 68790df1d55SAlex Deucher 68890df1d55SAlex Deucher /*define for encrypt field*/ 68990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 69090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 69190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 69290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 69390df1d55SAlex Deucher 69490df1d55SAlex Deucher /*define for tmz field*/ 69590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 69690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 69790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 69890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 69990df1d55SAlex Deucher 70090df1d55SAlex Deucher /*define for mip_max field*/ 70190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0 70290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F 70390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20 70490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift) 70590df1d55SAlex Deucher 70690df1d55SAlex Deucher /*define for detile field*/ 70790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 70890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 70990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 71090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 71190df1d55SAlex Deucher 71290df1d55SAlex Deucher /*define for TILED_ADDR_LO word*/ 71390df1d55SAlex Deucher /*define for tiled_addr_31_0 field*/ 71490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 71590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 71690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 71790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 71890df1d55SAlex Deucher 71990df1d55SAlex Deucher /*define for TILED_ADDR_HI word*/ 72090df1d55SAlex Deucher /*define for tiled_addr_63_32 field*/ 72190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 72290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 72390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 72490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 72590df1d55SAlex Deucher 72690df1d55SAlex Deucher /*define for DW_3 word*/ 72790df1d55SAlex Deucher /*define for width field*/ 72890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 72990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 73090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 73190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 73290df1d55SAlex Deucher 73390df1d55SAlex Deucher /*define for DW_4 word*/ 73490df1d55SAlex Deucher /*define for height field*/ 73590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 73690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 73790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 73890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 73990df1d55SAlex Deucher 74090df1d55SAlex Deucher /*define for depth field*/ 74190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 74290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF 74390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 74490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 74590df1d55SAlex Deucher 74690df1d55SAlex Deucher /*define for DW_5 word*/ 74790df1d55SAlex Deucher /*define for element_size field*/ 74890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 74990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 75090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 75190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 75290df1d55SAlex Deucher 75390df1d55SAlex Deucher /*define for swizzle_mode field*/ 75490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 75590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 75690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 75790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 75890df1d55SAlex Deucher 75990df1d55SAlex Deucher /*define for dimension field*/ 76090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 76190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 76290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 76390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 76490df1d55SAlex Deucher 76590df1d55SAlex Deucher /*define for epitch field*/ 76690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5 76790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF 76890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16 76990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift) 77090df1d55SAlex Deucher 77190df1d55SAlex Deucher /*define for DW_6 word*/ 77290df1d55SAlex Deucher /*define for x field*/ 77390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 77490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 77590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 77690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 77790df1d55SAlex Deucher 77890df1d55SAlex Deucher /*define for y field*/ 77990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 78090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 78190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 78290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 78390df1d55SAlex Deucher 78490df1d55SAlex Deucher /*define for DW_7 word*/ 78590df1d55SAlex Deucher /*define for z field*/ 78690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 78790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF 78890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 78990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 79090df1d55SAlex Deucher 79190df1d55SAlex Deucher /*define for linear_sw field*/ 79290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 79390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 79490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 79590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 79690df1d55SAlex Deucher 79790df1d55SAlex Deucher /*define for tile_sw field*/ 79890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 79990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 80090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 80190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 80290df1d55SAlex Deucher 80390df1d55SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 80490df1d55SAlex Deucher /*define for linear_addr_31_0 field*/ 80590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 80690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 80790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 80890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 80990df1d55SAlex Deucher 81090df1d55SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 81190df1d55SAlex Deucher /*define for linear_addr_63_32 field*/ 81290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 81390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 81490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 81590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 81690df1d55SAlex Deucher 81790df1d55SAlex Deucher /*define for LINEAR_PITCH word*/ 81890df1d55SAlex Deucher /*define for linear_pitch field*/ 81990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 82090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 82190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 82290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 82390df1d55SAlex Deucher 82490df1d55SAlex Deucher /*define for LINEAR_SLICE_PITCH word*/ 82590df1d55SAlex Deucher /*define for linear_slice_pitch field*/ 82690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 82790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 82890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 82990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 83090df1d55SAlex Deucher 83190df1d55SAlex Deucher /*define for COUNT word*/ 83290df1d55SAlex Deucher /*define for count field*/ 83390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 83490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF 83590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 83690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 83790df1d55SAlex Deucher 83890df1d55SAlex Deucher 83990df1d55SAlex Deucher /* 84090df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 84190df1d55SAlex Deucher */ 84290df1d55SAlex Deucher 84390df1d55SAlex Deucher /*define for HEADER word*/ 84490df1d55SAlex Deucher /*define for op field*/ 84590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 84690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 84790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 84890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 84990df1d55SAlex Deucher 85090df1d55SAlex Deucher /*define for sub_op field*/ 85190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 85290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 85390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 85490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 85590df1d55SAlex Deucher 85690df1d55SAlex Deucher /*define for encrypt field*/ 85790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 85890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 85990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 86090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 86190df1d55SAlex Deucher 86290df1d55SAlex Deucher /*define for tmz field*/ 86390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 86490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 86590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 86690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 86790df1d55SAlex Deucher 86890df1d55SAlex Deucher /*define for mip_max field*/ 86990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0 87090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F 87190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20 87290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift) 87390df1d55SAlex Deucher 87490df1d55SAlex Deucher /*define for videocopy field*/ 87590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 87690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 87790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 87890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 87990df1d55SAlex Deucher 88090df1d55SAlex Deucher /*define for broadcast field*/ 88190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 88290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 88390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 88490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 88590df1d55SAlex Deucher 88690df1d55SAlex Deucher /*define for TILED_ADDR_LO_0 word*/ 88790df1d55SAlex Deucher /*define for tiled_addr0_31_0 field*/ 88890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 88990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 89090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 89190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 89290df1d55SAlex Deucher 89390df1d55SAlex Deucher /*define for TILED_ADDR_HI_0 word*/ 89490df1d55SAlex Deucher /*define for tiled_addr0_63_32 field*/ 89590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 89690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 89790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 89890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 89990df1d55SAlex Deucher 90090df1d55SAlex Deucher /*define for TILED_ADDR_LO_1 word*/ 90190df1d55SAlex Deucher /*define for tiled_addr1_31_0 field*/ 90290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 90390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 90490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 90590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 90690df1d55SAlex Deucher 90790df1d55SAlex Deucher /*define for TILED_ADDR_HI_1 word*/ 90890df1d55SAlex Deucher /*define for tiled_addr1_63_32 field*/ 90990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 91090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 91190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 91290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 91390df1d55SAlex Deucher 91490df1d55SAlex Deucher /*define for DW_5 word*/ 91590df1d55SAlex Deucher /*define for width field*/ 91690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 91790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 91890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 91990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 92090df1d55SAlex Deucher 92190df1d55SAlex Deucher /*define for DW_6 word*/ 92290df1d55SAlex Deucher /*define for height field*/ 92390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 92490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 92590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 92690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 92790df1d55SAlex Deucher 92890df1d55SAlex Deucher /*define for depth field*/ 92990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 93090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF 93190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 93290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 93390df1d55SAlex Deucher 93490df1d55SAlex Deucher /*define for DW_7 word*/ 93590df1d55SAlex Deucher /*define for element_size field*/ 93690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 93790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 93890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 93990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 94090df1d55SAlex Deucher 94190df1d55SAlex Deucher /*define for swizzle_mode field*/ 94290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 94390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 94490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 94590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 94690df1d55SAlex Deucher 94790df1d55SAlex Deucher /*define for dimension field*/ 94890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 94990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 95090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 95190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 95290df1d55SAlex Deucher 95390df1d55SAlex Deucher /*define for epitch field*/ 95490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7 95590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF 95690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16 95790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift) 95890df1d55SAlex Deucher 95990df1d55SAlex Deucher /*define for DW_8 word*/ 96090df1d55SAlex Deucher /*define for x field*/ 96190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 96290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 96390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 96490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 96590df1d55SAlex Deucher 96690df1d55SAlex Deucher /*define for y field*/ 96790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 96890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 96990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 97090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 97190df1d55SAlex Deucher 97290df1d55SAlex Deucher /*define for DW_9 word*/ 97390df1d55SAlex Deucher /*define for z field*/ 97490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 97590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF 97690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 97790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 97890df1d55SAlex Deucher 97990df1d55SAlex Deucher /*define for DW_10 word*/ 98090df1d55SAlex Deucher /*define for dst2_sw field*/ 98190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 98290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 98390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 98490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 98590df1d55SAlex Deucher 98690df1d55SAlex Deucher /*define for linear_sw field*/ 98790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 98890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 98990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 99090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 99190df1d55SAlex Deucher 99290df1d55SAlex Deucher /*define for tile_sw field*/ 99390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 99490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 99590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 99690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 99790df1d55SAlex Deucher 99890df1d55SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 99990df1d55SAlex Deucher /*define for linear_addr_31_0 field*/ 100090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 100190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 100290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 100390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 100490df1d55SAlex Deucher 100590df1d55SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 100690df1d55SAlex Deucher /*define for linear_addr_63_32 field*/ 100790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 100890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 100990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 101090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 101190df1d55SAlex Deucher 101290df1d55SAlex Deucher /*define for LINEAR_PITCH word*/ 101390df1d55SAlex Deucher /*define for linear_pitch field*/ 101490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 101590df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 101690df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 101790df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 101890df1d55SAlex Deucher 101990df1d55SAlex Deucher /*define for LINEAR_SLICE_PITCH word*/ 102090df1d55SAlex Deucher /*define for linear_slice_pitch field*/ 102190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 102290df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 102390df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 102490df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 102590df1d55SAlex Deucher 102690df1d55SAlex Deucher /*define for COUNT word*/ 102790df1d55SAlex Deucher /*define for count field*/ 102890df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 102990df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF 103090df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 103190df1d55SAlex Deucher #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 103290df1d55SAlex Deucher 103390df1d55SAlex Deucher 103490df1d55SAlex Deucher /* 103590df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_T2T packet 103690df1d55SAlex Deucher */ 103790df1d55SAlex Deucher 103890df1d55SAlex Deucher /*define for HEADER word*/ 103990df1d55SAlex Deucher /*define for op field*/ 104090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 104190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 104290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 104390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 104490df1d55SAlex Deucher 104590df1d55SAlex Deucher /*define for sub_op field*/ 104690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 104790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 104890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 104990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 105090df1d55SAlex Deucher 105190df1d55SAlex Deucher /*define for tmz field*/ 105290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 105390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 105490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 105590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 105690df1d55SAlex Deucher 105790df1d55SAlex Deucher /*define for mip_max field*/ 105890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0 105990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F 106090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 20 106190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift) 106290df1d55SAlex Deucher 106390df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 106490df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 106590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 106690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 106790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 106890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 106990df1d55SAlex Deucher 107090df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 107190df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 107290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 107390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 107490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 107590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 107690df1d55SAlex Deucher 107790df1d55SAlex Deucher /*define for DW_3 word*/ 107890df1d55SAlex Deucher /*define for src_x field*/ 107990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 108090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 108190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 108290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 108390df1d55SAlex Deucher 108490df1d55SAlex Deucher /*define for src_y field*/ 108590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 108690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 108790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 108890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 108990df1d55SAlex Deucher 109090df1d55SAlex Deucher /*define for DW_4 word*/ 109190df1d55SAlex Deucher /*define for src_z field*/ 109290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 109390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF 109490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 109590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 109690df1d55SAlex Deucher 109790df1d55SAlex Deucher /*define for src_width field*/ 109890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 109990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 110090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 110190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 110290df1d55SAlex Deucher 110390df1d55SAlex Deucher /*define for DW_5 word*/ 110490df1d55SAlex Deucher /*define for src_height field*/ 110590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 110690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 110790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 110890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 110990df1d55SAlex Deucher 111090df1d55SAlex Deucher /*define for src_depth field*/ 111190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 111290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF 111390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 111490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 111590df1d55SAlex Deucher 111690df1d55SAlex Deucher /*define for DW_6 word*/ 111790df1d55SAlex Deucher /*define for src_element_size field*/ 111890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 111990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 112090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 112190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 112290df1d55SAlex Deucher 112390df1d55SAlex Deucher /*define for src_swizzle_mode field*/ 112490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 112590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 112690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 112790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 112890df1d55SAlex Deucher 112990df1d55SAlex Deucher /*define for src_dimension field*/ 113090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 113190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 113290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 113390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 113490df1d55SAlex Deucher 113590df1d55SAlex Deucher /*define for src_epitch field*/ 113690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 6 113790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF 113890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 16 113990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift) 114090df1d55SAlex Deucher 114190df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 114290df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 114390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 114490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 114590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 114690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 114790df1d55SAlex Deucher 114890df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 114990df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 115090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 115190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 115290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 115390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 115490df1d55SAlex Deucher 115590df1d55SAlex Deucher /*define for DW_9 word*/ 115690df1d55SAlex Deucher /*define for dst_x field*/ 115790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 115890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 115990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 116090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 116190df1d55SAlex Deucher 116290df1d55SAlex Deucher /*define for dst_y field*/ 116390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 116490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 116590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 116690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 116790df1d55SAlex Deucher 116890df1d55SAlex Deucher /*define for DW_10 word*/ 116990df1d55SAlex Deucher /*define for dst_z field*/ 117090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 117190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF 117290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 117390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 117490df1d55SAlex Deucher 117590df1d55SAlex Deucher /*define for dst_width field*/ 117690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 117790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 117890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 117990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 118090df1d55SAlex Deucher 118190df1d55SAlex Deucher /*define for DW_11 word*/ 118290df1d55SAlex Deucher /*define for dst_height field*/ 118390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 118490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 118590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 118690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 118790df1d55SAlex Deucher 118890df1d55SAlex Deucher /*define for dst_depth field*/ 118990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 119090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF 119190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 119290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 119390df1d55SAlex Deucher 119490df1d55SAlex Deucher /*define for DW_12 word*/ 119590df1d55SAlex Deucher /*define for dst_element_size field*/ 119690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 119790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 119890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 119990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 120090df1d55SAlex Deucher 120190df1d55SAlex Deucher /*define for dst_swizzle_mode field*/ 120290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 120390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 120490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 120590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 120690df1d55SAlex Deucher 120790df1d55SAlex Deucher /*define for dst_dimension field*/ 120890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 120990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 121090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 121190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 121290df1d55SAlex Deucher 121390df1d55SAlex Deucher /*define for dst_epitch field*/ 121490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 12 121590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF 121690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 16 121790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift) 121890df1d55SAlex Deucher 121990df1d55SAlex Deucher /*define for DW_13 word*/ 122090df1d55SAlex Deucher /*define for rect_x field*/ 122190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 122290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 122390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 122490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 122590df1d55SAlex Deucher 122690df1d55SAlex Deucher /*define for rect_y field*/ 122790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 122890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 122990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 123090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 123190df1d55SAlex Deucher 123290df1d55SAlex Deucher /*define for DW_14 word*/ 123390df1d55SAlex Deucher /*define for rect_z field*/ 123490df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 123590df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF 123690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 123790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 123890df1d55SAlex Deucher 123990df1d55SAlex Deucher /*define for dst_sw field*/ 124090df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 124190df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 124290df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 124390df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 124490df1d55SAlex Deucher 124590df1d55SAlex Deucher /*define for src_sw field*/ 124690df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 124790df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 124890df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 124990df1d55SAlex Deucher #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 125090df1d55SAlex Deucher 125190df1d55SAlex Deucher 125290df1d55SAlex Deucher /* 125390df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 125490df1d55SAlex Deucher */ 125590df1d55SAlex Deucher 125690df1d55SAlex Deucher /*define for HEADER word*/ 125790df1d55SAlex Deucher /*define for op field*/ 125890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 125990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 126090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 126190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 126290df1d55SAlex Deucher 126390df1d55SAlex Deucher /*define for sub_op field*/ 126490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 126590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 126690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 126790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 126890df1d55SAlex Deucher 126990df1d55SAlex Deucher /*define for tmz field*/ 127090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 127190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 127290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 127390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 127490df1d55SAlex Deucher 127590df1d55SAlex Deucher /*define for mip_max field*/ 127690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0 127790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F 127890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 20 127990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift) 128090df1d55SAlex Deucher 128190df1d55SAlex Deucher /*define for mip_id field*/ 128290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0 128390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F 128490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 24 128590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift) 128690df1d55SAlex Deucher 128790df1d55SAlex Deucher /*define for detile field*/ 128890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 128990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 129090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 129190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 129290df1d55SAlex Deucher 129390df1d55SAlex Deucher /*define for TILED_ADDR_LO word*/ 129490df1d55SAlex Deucher /*define for tiled_addr_31_0 field*/ 129590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 129690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 129790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 129890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 129990df1d55SAlex Deucher 130090df1d55SAlex Deucher /*define for TILED_ADDR_HI word*/ 130190df1d55SAlex Deucher /*define for tiled_addr_63_32 field*/ 130290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 130390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 130490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 130590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 130690df1d55SAlex Deucher 130790df1d55SAlex Deucher /*define for DW_3 word*/ 130890df1d55SAlex Deucher /*define for tiled_x field*/ 130990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 131090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 131190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 131290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 131390df1d55SAlex Deucher 131490df1d55SAlex Deucher /*define for tiled_y field*/ 131590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 131690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 131790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 131890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 131990df1d55SAlex Deucher 132090df1d55SAlex Deucher /*define for DW_4 word*/ 132190df1d55SAlex Deucher /*define for tiled_z field*/ 132290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 132390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF 132490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 132590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 132690df1d55SAlex Deucher 132790df1d55SAlex Deucher /*define for width field*/ 132890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 132990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 133090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 133190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 133290df1d55SAlex Deucher 133390df1d55SAlex Deucher /*define for DW_5 word*/ 133490df1d55SAlex Deucher /*define for height field*/ 133590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 133690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 133790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 133890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 133990df1d55SAlex Deucher 134090df1d55SAlex Deucher /*define for depth field*/ 134190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 134290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF 134390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 134490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 134590df1d55SAlex Deucher 134690df1d55SAlex Deucher /*define for DW_6 word*/ 134790df1d55SAlex Deucher /*define for element_size field*/ 134890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 134990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 135090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 135190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 135290df1d55SAlex Deucher 135390df1d55SAlex Deucher /*define for swizzle_mode field*/ 135490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 135590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 135690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 135790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 135890df1d55SAlex Deucher 135990df1d55SAlex Deucher /*define for dimension field*/ 136090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 136190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 136290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 136390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 136490df1d55SAlex Deucher 136590df1d55SAlex Deucher /*define for epitch field*/ 136690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 6 136790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF 136890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 16 136990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift) 137090df1d55SAlex Deucher 137190df1d55SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 137290df1d55SAlex Deucher /*define for linear_addr_31_0 field*/ 137390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 137490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 137590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 137690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 137790df1d55SAlex Deucher 137890df1d55SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 137990df1d55SAlex Deucher /*define for linear_addr_63_32 field*/ 138090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 138190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 138290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 138390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 138490df1d55SAlex Deucher 138590df1d55SAlex Deucher /*define for DW_9 word*/ 138690df1d55SAlex Deucher /*define for linear_x field*/ 138790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 138890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 138990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 139090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 139190df1d55SAlex Deucher 139290df1d55SAlex Deucher /*define for linear_y field*/ 139390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 139490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 139590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 139690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 139790df1d55SAlex Deucher 139890df1d55SAlex Deucher /*define for DW_10 word*/ 139990df1d55SAlex Deucher /*define for linear_z field*/ 140090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 140190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF 140290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 140390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 140490df1d55SAlex Deucher 140590df1d55SAlex Deucher /*define for linear_pitch field*/ 140690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 140790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 140890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 140990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 141090df1d55SAlex Deucher 141190df1d55SAlex Deucher /*define for DW_11 word*/ 141290df1d55SAlex Deucher /*define for linear_slice_pitch field*/ 141390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 141490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 141590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 141690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 141790df1d55SAlex Deucher 141890df1d55SAlex Deucher /*define for DW_12 word*/ 141990df1d55SAlex Deucher /*define for rect_x field*/ 142090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 142190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 142290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 142390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 142490df1d55SAlex Deucher 142590df1d55SAlex Deucher /*define for rect_y field*/ 142690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 142790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 142890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 142990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 143090df1d55SAlex Deucher 143190df1d55SAlex Deucher /*define for DW_13 word*/ 143290df1d55SAlex Deucher /*define for rect_z field*/ 143390df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 143490df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF 143590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 143690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 143790df1d55SAlex Deucher 143890df1d55SAlex Deucher /*define for linear_sw field*/ 143990df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 144090df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 144190df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 144290df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 144390df1d55SAlex Deucher 144490df1d55SAlex Deucher /*define for tile_sw field*/ 144590df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 144690df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 144790df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 144890df1d55SAlex Deucher #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 144990df1d55SAlex Deucher 145090df1d55SAlex Deucher 145190df1d55SAlex Deucher /* 145290df1d55SAlex Deucher ** Definitions for SDMA_PKT_COPY_STRUCT packet 145390df1d55SAlex Deucher */ 145490df1d55SAlex Deucher 145590df1d55SAlex Deucher /*define for HEADER word*/ 145690df1d55SAlex Deucher /*define for op field*/ 145790df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 145890df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 145990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 146090df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 146190df1d55SAlex Deucher 146290df1d55SAlex Deucher /*define for sub_op field*/ 146390df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 146490df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 146590df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 146690df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 146790df1d55SAlex Deucher 146890df1d55SAlex Deucher /*define for tmz field*/ 146990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 147090df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 147190df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 147290df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 147390df1d55SAlex Deucher 147490df1d55SAlex Deucher /*define for detile field*/ 147590df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 147690df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 147790df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 147890df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 147990df1d55SAlex Deucher 148090df1d55SAlex Deucher /*define for SB_ADDR_LO word*/ 148190df1d55SAlex Deucher /*define for sb_addr_31_0 field*/ 148290df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 148390df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 148490df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 148590df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 148690df1d55SAlex Deucher 148790df1d55SAlex Deucher /*define for SB_ADDR_HI word*/ 148890df1d55SAlex Deucher /*define for sb_addr_63_32 field*/ 148990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 149090df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 149190df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 149290df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 149390df1d55SAlex Deucher 149490df1d55SAlex Deucher /*define for START_INDEX word*/ 149590df1d55SAlex Deucher /*define for start_index field*/ 149690df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 149790df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 149890df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 149990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 150090df1d55SAlex Deucher 150190df1d55SAlex Deucher /*define for COUNT word*/ 150290df1d55SAlex Deucher /*define for count field*/ 150390df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 150490df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 150590df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 150690df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 150790df1d55SAlex Deucher 150890df1d55SAlex Deucher /*define for DW_5 word*/ 150990df1d55SAlex Deucher /*define for stride field*/ 151090df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 151190df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 151290df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 151390df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 151490df1d55SAlex Deucher 151590df1d55SAlex Deucher /*define for linear_sw field*/ 151690df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 151790df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 151890df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 151990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 152090df1d55SAlex Deucher 152190df1d55SAlex Deucher /*define for struct_sw field*/ 152290df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 152390df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 152490df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 152590df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 152690df1d55SAlex Deucher 152790df1d55SAlex Deucher /*define for LINEAR_ADDR_LO word*/ 152890df1d55SAlex Deucher /*define for linear_addr_31_0 field*/ 152990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 153090df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 153190df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 153290df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 153390df1d55SAlex Deucher 153490df1d55SAlex Deucher /*define for LINEAR_ADDR_HI word*/ 153590df1d55SAlex Deucher /*define for linear_addr_63_32 field*/ 153690df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 153790df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 153890df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 153990df1d55SAlex Deucher #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 154090df1d55SAlex Deucher 154190df1d55SAlex Deucher 154290df1d55SAlex Deucher /* 154390df1d55SAlex Deucher ** Definitions for SDMA_PKT_WRITE_UNTILED packet 154490df1d55SAlex Deucher */ 154590df1d55SAlex Deucher 154690df1d55SAlex Deucher /*define for HEADER word*/ 154790df1d55SAlex Deucher /*define for op field*/ 154890df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 154990df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 155090df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 155190df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 155290df1d55SAlex Deucher 155390df1d55SAlex Deucher /*define for sub_op field*/ 155490df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 155590df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 155690df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 155790df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 155890df1d55SAlex Deucher 155990df1d55SAlex Deucher /*define for encrypt field*/ 156090df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 156190df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 156290df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 156390df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 156490df1d55SAlex Deucher 156590df1d55SAlex Deucher /*define for tmz field*/ 156690df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 156790df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 156890df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 156990df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 157090df1d55SAlex Deucher 157190df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 157290df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 157390df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 157490df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 157590df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 157690df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 157790df1d55SAlex Deucher 157890df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 157990df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 158090df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 158190df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 158290df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 158390df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 158490df1d55SAlex Deucher 158590df1d55SAlex Deucher /*define for DW_3 word*/ 158690df1d55SAlex Deucher /*define for count field*/ 158790df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 158890df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 158990df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 159090df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 159190df1d55SAlex Deucher 159290df1d55SAlex Deucher /*define for sw field*/ 159390df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 159490df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 159590df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 159690df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 159790df1d55SAlex Deucher 159890df1d55SAlex Deucher /*define for DATA0 word*/ 159990df1d55SAlex Deucher /*define for data0 field*/ 160090df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 160190df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 160290df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 160390df1d55SAlex Deucher #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 160490df1d55SAlex Deucher 160590df1d55SAlex Deucher 160690df1d55SAlex Deucher /* 160790df1d55SAlex Deucher ** Definitions for SDMA_PKT_WRITE_TILED packet 160890df1d55SAlex Deucher */ 160990df1d55SAlex Deucher 161090df1d55SAlex Deucher /*define for HEADER word*/ 161190df1d55SAlex Deucher /*define for op field*/ 161290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 161390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 161490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 161590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 161690df1d55SAlex Deucher 161790df1d55SAlex Deucher /*define for sub_op field*/ 161890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 161990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 162090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 162190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 162290df1d55SAlex Deucher 162390df1d55SAlex Deucher /*define for encrypt field*/ 162490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 162590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 162690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 162790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 162890df1d55SAlex Deucher 162990df1d55SAlex Deucher /*define for tmz field*/ 163090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 163190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 163290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 163390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 163490df1d55SAlex Deucher 163590df1d55SAlex Deucher /*define for mip_max field*/ 163690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0 163790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F 163890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 20 163990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift) 164090df1d55SAlex Deucher 164190df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 164290df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 164390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 164490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 164590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 164690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 164790df1d55SAlex Deucher 164890df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 164990df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 165090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 165190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 165290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 165390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 165490df1d55SAlex Deucher 165590df1d55SAlex Deucher /*define for DW_3 word*/ 165690df1d55SAlex Deucher /*define for width field*/ 165790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 165890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 165990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 166090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 166190df1d55SAlex Deucher 166290df1d55SAlex Deucher /*define for DW_4 word*/ 166390df1d55SAlex Deucher /*define for height field*/ 166490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 166590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 166690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 166790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 166890df1d55SAlex Deucher 166990df1d55SAlex Deucher /*define for depth field*/ 167090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 167190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF 167290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 167390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 167490df1d55SAlex Deucher 167590df1d55SAlex Deucher /*define for DW_5 word*/ 167690df1d55SAlex Deucher /*define for element_size field*/ 167790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 167890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 167990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 168090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 168190df1d55SAlex Deucher 168290df1d55SAlex Deucher /*define for swizzle_mode field*/ 168390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 168490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 168590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 168690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 168790df1d55SAlex Deucher 168890df1d55SAlex Deucher /*define for dimension field*/ 168990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 169090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 169190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 169290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 169390df1d55SAlex Deucher 169490df1d55SAlex Deucher /*define for epitch field*/ 169590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 5 169690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF 169790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 16 169890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift) 169990df1d55SAlex Deucher 170090df1d55SAlex Deucher /*define for DW_6 word*/ 170190df1d55SAlex Deucher /*define for x field*/ 170290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 170390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 170490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 170590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 170690df1d55SAlex Deucher 170790df1d55SAlex Deucher /*define for y field*/ 170890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 170990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 171090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 171190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 171290df1d55SAlex Deucher 171390df1d55SAlex Deucher /*define for DW_7 word*/ 171490df1d55SAlex Deucher /*define for z field*/ 171590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 171690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF 171790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 171890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 171990df1d55SAlex Deucher 172090df1d55SAlex Deucher /*define for sw field*/ 172190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 172290df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 172390df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 172490df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 172590df1d55SAlex Deucher 172690df1d55SAlex Deucher /*define for COUNT word*/ 172790df1d55SAlex Deucher /*define for count field*/ 172890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 172990df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 173090df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 173190df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 173290df1d55SAlex Deucher 173390df1d55SAlex Deucher /*define for DATA0 word*/ 173490df1d55SAlex Deucher /*define for data0 field*/ 173590df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 173690df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 173790df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 173890df1d55SAlex Deucher #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 173990df1d55SAlex Deucher 174090df1d55SAlex Deucher 174190df1d55SAlex Deucher /* 174290df1d55SAlex Deucher ** Definitions for SDMA_PKT_PTEPDE_COPY packet 174390df1d55SAlex Deucher */ 174490df1d55SAlex Deucher 174590df1d55SAlex Deucher /*define for HEADER word*/ 174690df1d55SAlex Deucher /*define for op field*/ 174790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 174890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 174990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 175090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 175190df1d55SAlex Deucher 175290df1d55SAlex Deucher /*define for sub_op field*/ 175390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 175490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 175590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 175690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 175790df1d55SAlex Deucher 175890df1d55SAlex Deucher /*define for ptepde_op field*/ 175990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 176090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 176190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 176290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 176390df1d55SAlex Deucher 176490df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 176590df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 176690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 176790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 176890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 176990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 177090df1d55SAlex Deucher 177190df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 177290df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 177390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 177490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 177590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 177690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 177790df1d55SAlex Deucher 177890df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 177990df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 178090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 178190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 178290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 178390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 178490df1d55SAlex Deucher 178590df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 178690df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 178790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 178890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 178990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 179090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 179190df1d55SAlex Deucher 179290df1d55SAlex Deucher /*define for MASK_DW0 word*/ 179390df1d55SAlex Deucher /*define for mask_dw0 field*/ 179490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 179590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 179690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 179790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 179890df1d55SAlex Deucher 179990df1d55SAlex Deucher /*define for MASK_DW1 word*/ 180090df1d55SAlex Deucher /*define for mask_dw1 field*/ 180190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 180290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 180390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 180490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 180590df1d55SAlex Deucher 180690df1d55SAlex Deucher /*define for COUNT word*/ 180790df1d55SAlex Deucher /*define for count field*/ 180890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 180990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 181090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 181190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 181290df1d55SAlex Deucher 181390df1d55SAlex Deucher 181490df1d55SAlex Deucher /* 181590df1d55SAlex Deucher ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 181690df1d55SAlex Deucher */ 181790df1d55SAlex Deucher 181890df1d55SAlex Deucher /*define for HEADER word*/ 181990df1d55SAlex Deucher /*define for op field*/ 182090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 182190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 182290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 182390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 182490df1d55SAlex Deucher 182590df1d55SAlex Deucher /*define for sub_op field*/ 182690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 182790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 182890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 182990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 183090df1d55SAlex Deucher 183190df1d55SAlex Deucher /*define for pte_size field*/ 183290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 183390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 183490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 183590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 183690df1d55SAlex Deucher 183790df1d55SAlex Deucher /*define for direction field*/ 183890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 183990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 184090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 184190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 184290df1d55SAlex Deucher 184390df1d55SAlex Deucher /*define for ptepde_op field*/ 184490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 184590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 184690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 184790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 184890df1d55SAlex Deucher 184990df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 185090df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 185190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 185290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 185390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 185490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 185590df1d55SAlex Deucher 185690df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 185790df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 185890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 185990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 186090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 186190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 186290df1d55SAlex Deucher 186390df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 186490df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 186590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 186690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 186790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 186890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 186990df1d55SAlex Deucher 187090df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 187190df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 187290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 187390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 187490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 187590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 187690df1d55SAlex Deucher 187790df1d55SAlex Deucher /*define for MASK_BIT_FOR_DW word*/ 187890df1d55SAlex Deucher /*define for mask_first_xfer field*/ 187990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 188090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 188190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 188290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 188390df1d55SAlex Deucher 188490df1d55SAlex Deucher /*define for mask_last_xfer field*/ 188590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 188690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 188790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 188890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 188990df1d55SAlex Deucher 189090df1d55SAlex Deucher /*define for COUNT_IN_32B_XFER word*/ 189190df1d55SAlex Deucher /*define for count field*/ 189290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 189390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 189490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 189590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 189690df1d55SAlex Deucher 189790df1d55SAlex Deucher 189890df1d55SAlex Deucher /* 189990df1d55SAlex Deucher ** Definitions for SDMA_PKT_PTEPDE_RMW packet 190090df1d55SAlex Deucher */ 190190df1d55SAlex Deucher 190290df1d55SAlex Deucher /*define for HEADER word*/ 190390df1d55SAlex Deucher /*define for op field*/ 190490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 190590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 190690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 190790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 190890df1d55SAlex Deucher 190990df1d55SAlex Deucher /*define for sub_op field*/ 191090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 191190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 191290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 191390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 191490df1d55SAlex Deucher 191590df1d55SAlex Deucher /*define for gcc field*/ 191690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 191790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 191890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 191990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 192090df1d55SAlex Deucher 192190df1d55SAlex Deucher /*define for sys field*/ 192290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 192390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 192490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 192590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 192690df1d55SAlex Deucher 192790df1d55SAlex Deucher /*define for snp field*/ 192890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 192990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 193090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 193190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 193290df1d55SAlex Deucher 193390df1d55SAlex Deucher /*define for gpa field*/ 193490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 193590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 193690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 193790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 193890df1d55SAlex Deucher 193990df1d55SAlex Deucher /*define for ADDR_LO word*/ 194090df1d55SAlex Deucher /*define for addr_31_0 field*/ 194190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 194290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 194390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 194490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 194590df1d55SAlex Deucher 194690df1d55SAlex Deucher /*define for ADDR_HI word*/ 194790df1d55SAlex Deucher /*define for addr_63_32 field*/ 194890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 194990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 195090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 195190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 195290df1d55SAlex Deucher 195390df1d55SAlex Deucher /*define for MASK_LO word*/ 195490df1d55SAlex Deucher /*define for mask_31_0 field*/ 195590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 195690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 195790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 195890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 195990df1d55SAlex Deucher 196090df1d55SAlex Deucher /*define for MASK_HI word*/ 196190df1d55SAlex Deucher /*define for mask_63_32 field*/ 196290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 196390df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 196490df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 196590df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 196690df1d55SAlex Deucher 196790df1d55SAlex Deucher /*define for VALUE_LO word*/ 196890df1d55SAlex Deucher /*define for value_31_0 field*/ 196990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 197090df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 197190df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 197290df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 197390df1d55SAlex Deucher 197490df1d55SAlex Deucher /*define for VALUE_HI word*/ 197590df1d55SAlex Deucher /*define for value_63_32 field*/ 197690df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 197790df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 197890df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 197990df1d55SAlex Deucher #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 198090df1d55SAlex Deucher 198190df1d55SAlex Deucher 198290df1d55SAlex Deucher /* 198390df1d55SAlex Deucher ** Definitions for SDMA_PKT_WRITE_INCR packet 198490df1d55SAlex Deucher */ 198590df1d55SAlex Deucher 198690df1d55SAlex Deucher /*define for HEADER word*/ 198790df1d55SAlex Deucher /*define for op field*/ 198890df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 198990df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 199090df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 199190df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 199290df1d55SAlex Deucher 199390df1d55SAlex Deucher /*define for sub_op field*/ 199490df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 199590df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 199690df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 199790df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 199890df1d55SAlex Deucher 199990df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 200090df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 200190df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 200290df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 200390df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 200490df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 200590df1d55SAlex Deucher 200690df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 200790df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 200890df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 200990df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 201090df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 201190df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 201290df1d55SAlex Deucher 201390df1d55SAlex Deucher /*define for MASK_DW0 word*/ 201490df1d55SAlex Deucher /*define for mask_dw0 field*/ 201590df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 201690df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 201790df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 201890df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 201990df1d55SAlex Deucher 202090df1d55SAlex Deucher /*define for MASK_DW1 word*/ 202190df1d55SAlex Deucher /*define for mask_dw1 field*/ 202290df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 202390df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 202490df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 202590df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 202690df1d55SAlex Deucher 202790df1d55SAlex Deucher /*define for INIT_DW0 word*/ 202890df1d55SAlex Deucher /*define for init_dw0 field*/ 202990df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 203090df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 203190df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 203290df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 203390df1d55SAlex Deucher 203490df1d55SAlex Deucher /*define for INIT_DW1 word*/ 203590df1d55SAlex Deucher /*define for init_dw1 field*/ 203690df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 203790df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 203890df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 203990df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 204090df1d55SAlex Deucher 204190df1d55SAlex Deucher /*define for INCR_DW0 word*/ 204290df1d55SAlex Deucher /*define for incr_dw0 field*/ 204390df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 204490df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 204590df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 204690df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 204790df1d55SAlex Deucher 204890df1d55SAlex Deucher /*define for INCR_DW1 word*/ 204990df1d55SAlex Deucher /*define for incr_dw1 field*/ 205090df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 205190df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 205290df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 205390df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 205490df1d55SAlex Deucher 205590df1d55SAlex Deucher /*define for COUNT word*/ 205690df1d55SAlex Deucher /*define for count field*/ 205790df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 205890df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 205990df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 206090df1d55SAlex Deucher #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 206190df1d55SAlex Deucher 206290df1d55SAlex Deucher 206390df1d55SAlex Deucher /* 206490df1d55SAlex Deucher ** Definitions for SDMA_PKT_INDIRECT packet 206590df1d55SAlex Deucher */ 206690df1d55SAlex Deucher 206790df1d55SAlex Deucher /*define for HEADER word*/ 206890df1d55SAlex Deucher /*define for op field*/ 206990df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 207090df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 207190df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 207290df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 207390df1d55SAlex Deucher 207490df1d55SAlex Deucher /*define for sub_op field*/ 207590df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 207690df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 207790df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 207890df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 207990df1d55SAlex Deucher 208090df1d55SAlex Deucher /*define for vmid field*/ 208190df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 208290df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 208390df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 208490df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 208590df1d55SAlex Deucher 208690df1d55SAlex Deucher /*define for BASE_LO word*/ 208790df1d55SAlex Deucher /*define for ib_base_31_0 field*/ 208890df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 208990df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 209090df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 209190df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 209290df1d55SAlex Deucher 209390df1d55SAlex Deucher /*define for BASE_HI word*/ 209490df1d55SAlex Deucher /*define for ib_base_63_32 field*/ 209590df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 209690df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 209790df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 209890df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 209990df1d55SAlex Deucher 210090df1d55SAlex Deucher /*define for IB_SIZE word*/ 210190df1d55SAlex Deucher /*define for ib_size field*/ 210290df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 210390df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 210490df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 210590df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 210690df1d55SAlex Deucher 210790df1d55SAlex Deucher /*define for CSA_ADDR_LO word*/ 210890df1d55SAlex Deucher /*define for csa_addr_31_0 field*/ 210990df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 211090df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 211190df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 211290df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 211390df1d55SAlex Deucher 211490df1d55SAlex Deucher /*define for CSA_ADDR_HI word*/ 211590df1d55SAlex Deucher /*define for csa_addr_63_32 field*/ 211690df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 211790df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 211890df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 211990df1d55SAlex Deucher #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 212090df1d55SAlex Deucher 212190df1d55SAlex Deucher 212290df1d55SAlex Deucher /* 212390df1d55SAlex Deucher ** Definitions for SDMA_PKT_SEMAPHORE packet 212490df1d55SAlex Deucher */ 212590df1d55SAlex Deucher 212690df1d55SAlex Deucher /*define for HEADER word*/ 212790df1d55SAlex Deucher /*define for op field*/ 212890df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 212990df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 213090df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 213190df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 213290df1d55SAlex Deucher 213390df1d55SAlex Deucher /*define for sub_op field*/ 213490df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 213590df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 213690df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 213790df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 213890df1d55SAlex Deucher 213990df1d55SAlex Deucher /*define for write_one field*/ 214090df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 214190df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 214290df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 214390df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 214490df1d55SAlex Deucher 214590df1d55SAlex Deucher /*define for signal field*/ 214690df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 214790df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 214890df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 214990df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 215090df1d55SAlex Deucher 215190df1d55SAlex Deucher /*define for mailbox field*/ 215290df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 215390df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 215490df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 215590df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 215690df1d55SAlex Deucher 215790df1d55SAlex Deucher /*define for ADDR_LO word*/ 215890df1d55SAlex Deucher /*define for addr_31_0 field*/ 215990df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 216090df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 216190df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 216290df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 216390df1d55SAlex Deucher 216490df1d55SAlex Deucher /*define for ADDR_HI word*/ 216590df1d55SAlex Deucher /*define for addr_63_32 field*/ 216690df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 216790df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 216890df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 216990df1d55SAlex Deucher #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 217090df1d55SAlex Deucher 217190df1d55SAlex Deucher 217290df1d55SAlex Deucher /* 217390df1d55SAlex Deucher ** Definitions for SDMA_PKT_FENCE packet 217490df1d55SAlex Deucher */ 217590df1d55SAlex Deucher 217690df1d55SAlex Deucher /*define for HEADER word*/ 217790df1d55SAlex Deucher /*define for op field*/ 217890df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_op_offset 0 217990df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 218090df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_op_shift 0 218190df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 218290df1d55SAlex Deucher 218390df1d55SAlex Deucher /*define for sub_op field*/ 218490df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 218590df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 218690df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 218790df1d55SAlex Deucher #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 218890df1d55SAlex Deucher 218990df1d55SAlex Deucher /*define for ADDR_LO word*/ 219090df1d55SAlex Deucher /*define for addr_31_0 field*/ 219190df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 219290df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 219390df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 219490df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 219590df1d55SAlex Deucher 219690df1d55SAlex Deucher /*define for ADDR_HI word*/ 219790df1d55SAlex Deucher /*define for addr_63_32 field*/ 219890df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 219990df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 220090df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 220190df1d55SAlex Deucher #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 220290df1d55SAlex Deucher 220390df1d55SAlex Deucher /*define for DATA word*/ 220490df1d55SAlex Deucher /*define for data field*/ 220590df1d55SAlex Deucher #define SDMA_PKT_FENCE_DATA_data_offset 3 220690df1d55SAlex Deucher #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 220790df1d55SAlex Deucher #define SDMA_PKT_FENCE_DATA_data_shift 0 220890df1d55SAlex Deucher #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 220990df1d55SAlex Deucher 221090df1d55SAlex Deucher 221190df1d55SAlex Deucher /* 221290df1d55SAlex Deucher ** Definitions for SDMA_PKT_SRBM_WRITE packet 221390df1d55SAlex Deucher */ 221490df1d55SAlex Deucher 221590df1d55SAlex Deucher /*define for HEADER word*/ 221690df1d55SAlex Deucher /*define for op field*/ 221790df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 221890df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 221990df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 222090df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 222190df1d55SAlex Deucher 222290df1d55SAlex Deucher /*define for sub_op field*/ 222390df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 222490df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 222590df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 222690df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 222790df1d55SAlex Deucher 222890df1d55SAlex Deucher /*define for byte_en field*/ 222990df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 223090df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 223190df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 223290df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 223390df1d55SAlex Deucher 223490df1d55SAlex Deucher /*define for ADDR word*/ 223590df1d55SAlex Deucher /*define for addr field*/ 223690df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 223790df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 223890df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 223990df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 224090df1d55SAlex Deucher 224190df1d55SAlex Deucher /*define for DATA word*/ 224290df1d55SAlex Deucher /*define for data field*/ 224390df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 224490df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 224590df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 224690df1d55SAlex Deucher #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 224790df1d55SAlex Deucher 224890df1d55SAlex Deucher 224990df1d55SAlex Deucher /* 225090df1d55SAlex Deucher ** Definitions for SDMA_PKT_PRE_EXE packet 225190df1d55SAlex Deucher */ 225290df1d55SAlex Deucher 225390df1d55SAlex Deucher /*define for HEADER word*/ 225490df1d55SAlex Deucher /*define for op field*/ 225590df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 225690df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 225790df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 225890df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 225990df1d55SAlex Deucher 226090df1d55SAlex Deucher /*define for sub_op field*/ 226190df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 226290df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 226390df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 226490df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 226590df1d55SAlex Deucher 226690df1d55SAlex Deucher /*define for dev_sel field*/ 226790df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 226890df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 226990df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 227090df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 227190df1d55SAlex Deucher 227290df1d55SAlex Deucher /*define for EXEC_COUNT word*/ 227390df1d55SAlex Deucher /*define for exec_count field*/ 227490df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 227590df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 227690df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 227790df1d55SAlex Deucher #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 227890df1d55SAlex Deucher 227990df1d55SAlex Deucher 228090df1d55SAlex Deucher /* 228190df1d55SAlex Deucher ** Definitions for SDMA_PKT_COND_EXE packet 228290df1d55SAlex Deucher */ 228390df1d55SAlex Deucher 228490df1d55SAlex Deucher /*define for HEADER word*/ 228590df1d55SAlex Deucher /*define for op field*/ 228690df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 228790df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 228890df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 228990df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 229090df1d55SAlex Deucher 229190df1d55SAlex Deucher /*define for sub_op field*/ 229290df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 229390df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 229490df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 229590df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 229690df1d55SAlex Deucher 229790df1d55SAlex Deucher /*define for ADDR_LO word*/ 229890df1d55SAlex Deucher /*define for addr_31_0 field*/ 229990df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 230090df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 230190df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 230290df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 230390df1d55SAlex Deucher 230490df1d55SAlex Deucher /*define for ADDR_HI word*/ 230590df1d55SAlex Deucher /*define for addr_63_32 field*/ 230690df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 230790df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 230890df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 230990df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 231090df1d55SAlex Deucher 231190df1d55SAlex Deucher /*define for REFERENCE word*/ 231290df1d55SAlex Deucher /*define for reference field*/ 231390df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 231490df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 231590df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 231690df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 231790df1d55SAlex Deucher 231890df1d55SAlex Deucher /*define for EXEC_COUNT word*/ 231990df1d55SAlex Deucher /*define for exec_count field*/ 232090df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 232190df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 232290df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 232390df1d55SAlex Deucher #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 232490df1d55SAlex Deucher 232590df1d55SAlex Deucher 232690df1d55SAlex Deucher /* 232790df1d55SAlex Deucher ** Definitions for SDMA_PKT_CONSTANT_FILL packet 232890df1d55SAlex Deucher */ 232990df1d55SAlex Deucher 233090df1d55SAlex Deucher /*define for HEADER word*/ 233190df1d55SAlex Deucher /*define for op field*/ 233290df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 233390df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 233490df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 233590df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 233690df1d55SAlex Deucher 233790df1d55SAlex Deucher /*define for sub_op field*/ 233890df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 233990df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 234090df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 234190df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 234290df1d55SAlex Deucher 234390df1d55SAlex Deucher /*define for sw field*/ 234490df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 234590df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 234690df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 234790df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 234890df1d55SAlex Deucher 234990df1d55SAlex Deucher /*define for fillsize field*/ 235090df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 235190df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 235290df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 235390df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 235490df1d55SAlex Deucher 235590df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 235690df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 235790df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 235890df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 235990df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 236090df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 236190df1d55SAlex Deucher 236290df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 236390df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 236490df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 236590df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 236690df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 236790df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 236890df1d55SAlex Deucher 236990df1d55SAlex Deucher /*define for DATA word*/ 237090df1d55SAlex Deucher /*define for src_data_31_0 field*/ 237190df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 237290df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 237390df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 237490df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 237590df1d55SAlex Deucher 237690df1d55SAlex Deucher /*define for COUNT word*/ 237790df1d55SAlex Deucher /*define for count field*/ 237890df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 237990df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 238090df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 238190df1d55SAlex Deucher #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 238290df1d55SAlex Deucher 238390df1d55SAlex Deucher 238490df1d55SAlex Deucher /* 238590df1d55SAlex Deucher ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 238690df1d55SAlex Deucher */ 238790df1d55SAlex Deucher 238890df1d55SAlex Deucher /*define for HEADER word*/ 238990df1d55SAlex Deucher /*define for op field*/ 239090df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 239190df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 239290df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 239390df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 239490df1d55SAlex Deucher 239590df1d55SAlex Deucher /*define for sub_op field*/ 239690df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 239790df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 239890df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 239990df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 240090df1d55SAlex Deucher 240190df1d55SAlex Deucher /*define for memlog_clr field*/ 240290df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 240390df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 240490df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 240590df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 240690df1d55SAlex Deucher 240790df1d55SAlex Deucher /*define for BYTE_STRIDE word*/ 240890df1d55SAlex Deucher /*define for byte_stride field*/ 240990df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 241090df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 241190df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 241290df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 241390df1d55SAlex Deucher 241490df1d55SAlex Deucher /*define for DMA_COUNT word*/ 241590df1d55SAlex Deucher /*define for dma_count field*/ 241690df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 241790df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 241890df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 241990df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 242090df1d55SAlex Deucher 242190df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 242290df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 242390df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 242490df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 242590df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 242690df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 242790df1d55SAlex Deucher 242890df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 242990df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 243090df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 243190df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 243290df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 243390df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 243490df1d55SAlex Deucher 243590df1d55SAlex Deucher /*define for BYTE_COUNT word*/ 243690df1d55SAlex Deucher /*define for count field*/ 243790df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 243890df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 243990df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 244090df1d55SAlex Deucher #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 244190df1d55SAlex Deucher 244290df1d55SAlex Deucher 244390df1d55SAlex Deucher /* 244490df1d55SAlex Deucher ** Definitions for SDMA_PKT_POLL_REGMEM packet 244590df1d55SAlex Deucher */ 244690df1d55SAlex Deucher 244790df1d55SAlex Deucher /*define for HEADER word*/ 244890df1d55SAlex Deucher /*define for op field*/ 244990df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 245090df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 245190df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 245290df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 245390df1d55SAlex Deucher 245490df1d55SAlex Deucher /*define for sub_op field*/ 245590df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 245690df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 245790df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 245890df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 245990df1d55SAlex Deucher 246090df1d55SAlex Deucher /*define for hdp_flush field*/ 246190df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 246290df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 246390df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 246490df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 246590df1d55SAlex Deucher 246690df1d55SAlex Deucher /*define for func field*/ 246790df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 246890df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 246990df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 247090df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 247190df1d55SAlex Deucher 247290df1d55SAlex Deucher /*define for mem_poll field*/ 247390df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 247490df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 247590df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 247690df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 247790df1d55SAlex Deucher 247890df1d55SAlex Deucher /*define for ADDR_LO word*/ 247990df1d55SAlex Deucher /*define for addr_31_0 field*/ 248090df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 248190df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 248290df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 248390df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 248490df1d55SAlex Deucher 248590df1d55SAlex Deucher /*define for ADDR_HI word*/ 248690df1d55SAlex Deucher /*define for addr_63_32 field*/ 248790df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 248890df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 248990df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 249090df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 249190df1d55SAlex Deucher 249290df1d55SAlex Deucher /*define for VALUE word*/ 249390df1d55SAlex Deucher /*define for value field*/ 249490df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 249590df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 249690df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 249790df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 249890df1d55SAlex Deucher 249990df1d55SAlex Deucher /*define for MASK word*/ 250090df1d55SAlex Deucher /*define for mask field*/ 250190df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 250290df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 250390df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 250490df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 250590df1d55SAlex Deucher 250690df1d55SAlex Deucher /*define for DW5 word*/ 250790df1d55SAlex Deucher /*define for interval field*/ 250890df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 250990df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 251090df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 251190df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 251290df1d55SAlex Deucher 251390df1d55SAlex Deucher /*define for retry_count field*/ 251490df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 251590df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 251690df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 251790df1d55SAlex Deucher #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 251890df1d55SAlex Deucher 251990df1d55SAlex Deucher 252090df1d55SAlex Deucher /* 252190df1d55SAlex Deucher ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 252290df1d55SAlex Deucher */ 252390df1d55SAlex Deucher 252490df1d55SAlex Deucher /*define for HEADER word*/ 252590df1d55SAlex Deucher /*define for op field*/ 252690df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 252790df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 252890df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 252990df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 253090df1d55SAlex Deucher 253190df1d55SAlex Deucher /*define for sub_op field*/ 253290df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 253390df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 253490df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 253590df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 253690df1d55SAlex Deucher 253790df1d55SAlex Deucher /*define for SRC_ADDR word*/ 253890df1d55SAlex Deucher /*define for addr_31_2 field*/ 253990df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 254090df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 254190df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 254290df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 254390df1d55SAlex Deucher 254490df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 254590df1d55SAlex Deucher /*define for addr_31_0 field*/ 254690df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 254790df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 254890df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 254990df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 255090df1d55SAlex Deucher 255190df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 255290df1d55SAlex Deucher /*define for addr_63_32 field*/ 255390df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 255490df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 255590df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 255690df1d55SAlex Deucher #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 255790df1d55SAlex Deucher 255890df1d55SAlex Deucher 255990df1d55SAlex Deucher /* 256090df1d55SAlex Deucher ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 256190df1d55SAlex Deucher */ 256290df1d55SAlex Deucher 256390df1d55SAlex Deucher /*define for HEADER word*/ 256490df1d55SAlex Deucher /*define for op field*/ 256590df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 256690df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 256790df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 256890df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 256990df1d55SAlex Deucher 257090df1d55SAlex Deucher /*define for sub_op field*/ 257190df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 257290df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 257390df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 257490df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 257590df1d55SAlex Deucher 257690df1d55SAlex Deucher /*define for ea field*/ 257790df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 257890df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 257990df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 258090df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 258190df1d55SAlex Deucher 258290df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 258390df1d55SAlex Deucher /*define for addr_31_0 field*/ 258490df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 258590df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 258690df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 258790df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 258890df1d55SAlex Deucher 258990df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 259090df1d55SAlex Deucher /*define for addr_63_32 field*/ 259190df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 259290df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 259390df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 259490df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 259590df1d55SAlex Deucher 259690df1d55SAlex Deucher /*define for START_PAGE word*/ 259790df1d55SAlex Deucher /*define for addr_31_4 field*/ 259890df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 259990df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 260090df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 260190df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 260290df1d55SAlex Deucher 260390df1d55SAlex Deucher /*define for PAGE_NUM word*/ 260490df1d55SAlex Deucher /*define for page_num_31_0 field*/ 260590df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 260690df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 260790df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 260890df1d55SAlex Deucher #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 260990df1d55SAlex Deucher 261090df1d55SAlex Deucher 261190df1d55SAlex Deucher /* 261290df1d55SAlex Deucher ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 261390df1d55SAlex Deucher */ 261490df1d55SAlex Deucher 261590df1d55SAlex Deucher /*define for HEADER word*/ 261690df1d55SAlex Deucher /*define for op field*/ 261790df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 261890df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 261990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 262090df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 262190df1d55SAlex Deucher 262290df1d55SAlex Deucher /*define for sub_op field*/ 262390df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 262490df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 262590df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 262690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 262790df1d55SAlex Deucher 262890df1d55SAlex Deucher /*define for mode field*/ 262990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 263090df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 263190df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 263290df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 263390df1d55SAlex Deucher 263490df1d55SAlex Deucher /*define for PATTERN word*/ 263590df1d55SAlex Deucher /*define for pattern field*/ 263690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 263790df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 263890df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 263990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 264090df1d55SAlex Deucher 264190df1d55SAlex Deucher /*define for CMP0_ADDR_START_LO word*/ 264290df1d55SAlex Deucher /*define for cmp0_start_31_0 field*/ 264390df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 264490df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 264590df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 264690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 264790df1d55SAlex Deucher 264890df1d55SAlex Deucher /*define for CMP0_ADDR_START_HI word*/ 264990df1d55SAlex Deucher /*define for cmp0_start_63_32 field*/ 265090df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 265190df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 265290df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 265390df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 265490df1d55SAlex Deucher 265590df1d55SAlex Deucher /*define for CMP0_ADDR_END_LO word*/ 265690df1d55SAlex Deucher /*define for cmp1_end_31_0 field*/ 265790df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 265890df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 265990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 266090df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) 266190df1d55SAlex Deucher 266290df1d55SAlex Deucher /*define for CMP0_ADDR_END_HI word*/ 266390df1d55SAlex Deucher /*define for cmp1_end_63_32 field*/ 266490df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 266590df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 266690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 266790df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) 266890df1d55SAlex Deucher 266990df1d55SAlex Deucher /*define for CMP1_ADDR_START_LO word*/ 267090df1d55SAlex Deucher /*define for cmp1_start_31_0 field*/ 267190df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 267290df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 267390df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 267490df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 267590df1d55SAlex Deucher 267690df1d55SAlex Deucher /*define for CMP1_ADDR_START_HI word*/ 267790df1d55SAlex Deucher /*define for cmp1_start_63_32 field*/ 267890df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 267990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 268090df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 268190df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 268290df1d55SAlex Deucher 268390df1d55SAlex Deucher /*define for CMP1_ADDR_END_LO word*/ 268490df1d55SAlex Deucher /*define for cmp1_end_31_0 field*/ 268590df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 268690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 268790df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 268890df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 268990df1d55SAlex Deucher 269090df1d55SAlex Deucher /*define for CMP1_ADDR_END_HI word*/ 269190df1d55SAlex Deucher /*define for cmp1_end_63_32 field*/ 269290df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 269390df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 269490df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 269590df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 269690df1d55SAlex Deucher 269790df1d55SAlex Deucher /*define for REC_ADDR_LO word*/ 269890df1d55SAlex Deucher /*define for rec_31_0 field*/ 269990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 270090df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 270190df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 270290df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 270390df1d55SAlex Deucher 270490df1d55SAlex Deucher /*define for REC_ADDR_HI word*/ 270590df1d55SAlex Deucher /*define for rec_63_32 field*/ 270690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 270790df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 270890df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 270990df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 271090df1d55SAlex Deucher 271190df1d55SAlex Deucher /*define for RESERVED word*/ 271290df1d55SAlex Deucher /*define for reserved field*/ 271390df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 271490df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 271590df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 271690df1d55SAlex Deucher #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 271790df1d55SAlex Deucher 271890df1d55SAlex Deucher 271990df1d55SAlex Deucher /* 272090df1d55SAlex Deucher ** Definitions for SDMA_PKT_ATOMIC packet 272190df1d55SAlex Deucher */ 272290df1d55SAlex Deucher 272390df1d55SAlex Deucher /*define for HEADER word*/ 272490df1d55SAlex Deucher /*define for op field*/ 272590df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 272690df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 272790df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 272890df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 272990df1d55SAlex Deucher 273090df1d55SAlex Deucher /*define for loop field*/ 273190df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 273290df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 273390df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 273490df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 273590df1d55SAlex Deucher 273690df1d55SAlex Deucher /*define for tmz field*/ 273790df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 273890df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 273990df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 274090df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 274190df1d55SAlex Deucher 274290df1d55SAlex Deucher /*define for atomic_op field*/ 274390df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 274490df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 274590df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 274690df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 274790df1d55SAlex Deucher 274890df1d55SAlex Deucher /*define for ADDR_LO word*/ 274990df1d55SAlex Deucher /*define for addr_31_0 field*/ 275090df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 275190df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 275290df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 275390df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 275490df1d55SAlex Deucher 275590df1d55SAlex Deucher /*define for ADDR_HI word*/ 275690df1d55SAlex Deucher /*define for addr_63_32 field*/ 275790df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 275890df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 275990df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 276090df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 276190df1d55SAlex Deucher 276290df1d55SAlex Deucher /*define for SRC_DATA_LO word*/ 276390df1d55SAlex Deucher /*define for src_data_31_0 field*/ 276490df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 276590df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 276690df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 276790df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 276890df1d55SAlex Deucher 276990df1d55SAlex Deucher /*define for SRC_DATA_HI word*/ 277090df1d55SAlex Deucher /*define for src_data_63_32 field*/ 277190df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 277290df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 277390df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 277490df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 277590df1d55SAlex Deucher 277690df1d55SAlex Deucher /*define for CMP_DATA_LO word*/ 277790df1d55SAlex Deucher /*define for cmp_data_31_0 field*/ 277890df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 277990df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 278090df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 278190df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 278290df1d55SAlex Deucher 278390df1d55SAlex Deucher /*define for CMP_DATA_HI word*/ 278490df1d55SAlex Deucher /*define for cmp_data_63_32 field*/ 278590df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 278690df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 278790df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 278890df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 278990df1d55SAlex Deucher 279090df1d55SAlex Deucher /*define for LOOP_INTERVAL word*/ 279190df1d55SAlex Deucher /*define for loop_interval field*/ 279290df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 279390df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 279490df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 279590df1d55SAlex Deucher #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 279690df1d55SAlex Deucher 279790df1d55SAlex Deucher 279890df1d55SAlex Deucher /* 279990df1d55SAlex Deucher ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 280090df1d55SAlex Deucher */ 280190df1d55SAlex Deucher 280290df1d55SAlex Deucher /*define for HEADER word*/ 280390df1d55SAlex Deucher /*define for op field*/ 280490df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 280590df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 280690df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 280790df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 280890df1d55SAlex Deucher 280990df1d55SAlex Deucher /*define for sub_op field*/ 281090df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 281190df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 281290df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 281390df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 281490df1d55SAlex Deucher 281590df1d55SAlex Deucher /*define for INIT_DATA_LO word*/ 281690df1d55SAlex Deucher /*define for init_data_31_0 field*/ 281790df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 281890df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 281990df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 282090df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 282190df1d55SAlex Deucher 282290df1d55SAlex Deucher /*define for INIT_DATA_HI word*/ 282390df1d55SAlex Deucher /*define for init_data_63_32 field*/ 282490df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 282590df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 282690df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 282790df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 282890df1d55SAlex Deucher 282990df1d55SAlex Deucher 283090df1d55SAlex Deucher /* 283190df1d55SAlex Deucher ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 283290df1d55SAlex Deucher */ 283390df1d55SAlex Deucher 283490df1d55SAlex Deucher /*define for HEADER word*/ 283590df1d55SAlex Deucher /*define for op field*/ 283690df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 283790df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 283890df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 283990df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 284090df1d55SAlex Deucher 284190df1d55SAlex Deucher /*define for sub_op field*/ 284290df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 284390df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 284490df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 284590df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 284690df1d55SAlex Deucher 284790df1d55SAlex Deucher /*define for WRITE_ADDR_LO word*/ 284890df1d55SAlex Deucher /*define for write_addr_31_3 field*/ 284990df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 285090df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 285190df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 285290df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 285390df1d55SAlex Deucher 285490df1d55SAlex Deucher /*define for WRITE_ADDR_HI word*/ 285590df1d55SAlex Deucher /*define for write_addr_63_32 field*/ 285690df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 285790df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 285890df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 285990df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 286090df1d55SAlex Deucher 286190df1d55SAlex Deucher 286290df1d55SAlex Deucher /* 286390df1d55SAlex Deucher ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 286490df1d55SAlex Deucher */ 286590df1d55SAlex Deucher 286690df1d55SAlex Deucher /*define for HEADER word*/ 286790df1d55SAlex Deucher /*define for op field*/ 286890df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 286990df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 287090df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 287190df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 287290df1d55SAlex Deucher 287390df1d55SAlex Deucher /*define for sub_op field*/ 287490df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 287590df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 287690df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 287790df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 287890df1d55SAlex Deucher 287990df1d55SAlex Deucher /*define for WRITE_ADDR_LO word*/ 288090df1d55SAlex Deucher /*define for write_addr_31_3 field*/ 288190df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 288290df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 288390df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 288490df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 288590df1d55SAlex Deucher 288690df1d55SAlex Deucher /*define for WRITE_ADDR_HI word*/ 288790df1d55SAlex Deucher /*define for write_addr_63_32 field*/ 288890df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 288990df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 289090df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 289190df1d55SAlex Deucher #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 289290df1d55SAlex Deucher 289390df1d55SAlex Deucher 289490df1d55SAlex Deucher /* 289590df1d55SAlex Deucher ** Definitions for SDMA_PKT_TRAP packet 289690df1d55SAlex Deucher */ 289790df1d55SAlex Deucher 289890df1d55SAlex Deucher /*define for HEADER word*/ 289990df1d55SAlex Deucher /*define for op field*/ 290090df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_op_offset 0 290190df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 290290df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_op_shift 0 290390df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 290490df1d55SAlex Deucher 290590df1d55SAlex Deucher /*define for sub_op field*/ 290690df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 290790df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 290890df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 290990df1d55SAlex Deucher #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 291090df1d55SAlex Deucher 291190df1d55SAlex Deucher /*define for INT_CONTEXT word*/ 291290df1d55SAlex Deucher /*define for int_context field*/ 291390df1d55SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 291490df1d55SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 291590df1d55SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 291690df1d55SAlex Deucher #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 291790df1d55SAlex Deucher 291890df1d55SAlex Deucher 291990df1d55SAlex Deucher /* 292090df1d55SAlex Deucher ** Definitions for SDMA_PKT_DUMMY_TRAP packet 292190df1d55SAlex Deucher */ 292290df1d55SAlex Deucher 292390df1d55SAlex Deucher /*define for HEADER word*/ 292490df1d55SAlex Deucher /*define for op field*/ 292590df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 292690df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 292790df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 292890df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 292990df1d55SAlex Deucher 293090df1d55SAlex Deucher /*define for sub_op field*/ 293190df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 293290df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 293390df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 293490df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 293590df1d55SAlex Deucher 293690df1d55SAlex Deucher /*define for INT_CONTEXT word*/ 293790df1d55SAlex Deucher /*define for int_context field*/ 293890df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 293990df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 294090df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 294190df1d55SAlex Deucher #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 294290df1d55SAlex Deucher 294390df1d55SAlex Deucher 294490df1d55SAlex Deucher /* 294590df1d55SAlex Deucher ** Definitions for SDMA_PKT_NOP packet 294690df1d55SAlex Deucher */ 294790df1d55SAlex Deucher 294890df1d55SAlex Deucher /*define for HEADER word*/ 294990df1d55SAlex Deucher /*define for op field*/ 295090df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_op_offset 0 295190df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 295290df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_op_shift 0 295390df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 295490df1d55SAlex Deucher 295590df1d55SAlex Deucher /*define for sub_op field*/ 295690df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 295790df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 295890df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 295990df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 296090df1d55SAlex Deucher 296190df1d55SAlex Deucher /*define for count field*/ 296290df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_count_offset 0 296390df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 296490df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_count_shift 16 296590df1d55SAlex Deucher #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 296690df1d55SAlex Deucher 296790df1d55SAlex Deucher /*define for DATA0 word*/ 296890df1d55SAlex Deucher /*define for data0 field*/ 296990df1d55SAlex Deucher #define SDMA_PKT_NOP_DATA0_data0_offset 1 297090df1d55SAlex Deucher #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 297190df1d55SAlex Deucher #define SDMA_PKT_NOP_DATA0_data0_shift 0 297290df1d55SAlex Deucher #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 297390df1d55SAlex Deucher 297490df1d55SAlex Deucher 297590df1d55SAlex Deucher /* 297690df1d55SAlex Deucher ** Definitions for SDMA_AQL_PKT_HEADER packet 297790df1d55SAlex Deucher */ 297890df1d55SAlex Deucher 297990df1d55SAlex Deucher /*define for HEADER word*/ 298090df1d55SAlex Deucher /*define for format field*/ 298190df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 298290df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 298390df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 298490df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 298590df1d55SAlex Deucher 298690df1d55SAlex Deucher /*define for barrier field*/ 298790df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 298890df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 298990df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 299090df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 299190df1d55SAlex Deucher 299290df1d55SAlex Deucher /*define for acquire_fence_scope field*/ 299390df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 299490df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 299590df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 299690df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 299790df1d55SAlex Deucher 299890df1d55SAlex Deucher /*define for release_fence_scope field*/ 299990df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 300090df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 300190df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 300290df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 300390df1d55SAlex Deucher 300490df1d55SAlex Deucher /*define for reserved field*/ 300590df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 300690df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 300790df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 300890df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 300990df1d55SAlex Deucher 301090df1d55SAlex Deucher /*define for op field*/ 301190df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 301290df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 301390df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 301490df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 301590df1d55SAlex Deucher 301690df1d55SAlex Deucher /*define for subop field*/ 301790df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 301890df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 301990df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 302090df1d55SAlex Deucher #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 302190df1d55SAlex Deucher 302290df1d55SAlex Deucher 302390df1d55SAlex Deucher /* 302490df1d55SAlex Deucher ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 302590df1d55SAlex Deucher */ 302690df1d55SAlex Deucher 302790df1d55SAlex Deucher /*define for HEADER word*/ 302890df1d55SAlex Deucher /*define for format field*/ 302990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 303090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 303190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 303290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 303390df1d55SAlex Deucher 303490df1d55SAlex Deucher /*define for barrier field*/ 303590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 303690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 303790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 303890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 303990df1d55SAlex Deucher 304090df1d55SAlex Deucher /*define for acquire_fence_scope field*/ 304190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 304290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 304390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 304490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 304590df1d55SAlex Deucher 304690df1d55SAlex Deucher /*define for release_fence_scope field*/ 304790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 304890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 304990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 305090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 305190df1d55SAlex Deucher 305290df1d55SAlex Deucher /*define for reserved field*/ 305390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 305490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 305590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 305690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 305790df1d55SAlex Deucher 305890df1d55SAlex Deucher /*define for op field*/ 305990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 306090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 306190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 306290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 306390df1d55SAlex Deucher 306490df1d55SAlex Deucher /*define for subop field*/ 306590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 306690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 306790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 306890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 306990df1d55SAlex Deucher 307090df1d55SAlex Deucher /*define for RESERVED_DW1 word*/ 307190df1d55SAlex Deucher /*define for reserved_dw1 field*/ 307290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 307390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 307490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 307590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 307690df1d55SAlex Deucher 307790df1d55SAlex Deucher /*define for RETURN_ADDR_LO word*/ 307890df1d55SAlex Deucher /*define for return_addr_31_0 field*/ 307990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 308090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 308190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 308290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 308390df1d55SAlex Deucher 308490df1d55SAlex Deucher /*define for RETURN_ADDR_HI word*/ 308590df1d55SAlex Deucher /*define for return_addr_63_32 field*/ 308690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 308790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 308890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 308990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 309090df1d55SAlex Deucher 309190df1d55SAlex Deucher /*define for COUNT word*/ 309290df1d55SAlex Deucher /*define for count field*/ 309390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 309490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 309590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 309690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 309790df1d55SAlex Deucher 309890df1d55SAlex Deucher /*define for PARAMETER word*/ 309990df1d55SAlex Deucher /*define for dst_sw field*/ 310090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 310190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 310290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 310390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 310490df1d55SAlex Deucher 310590df1d55SAlex Deucher /*define for src_sw field*/ 310690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 310790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 310890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 310990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 311090df1d55SAlex Deucher 311190df1d55SAlex Deucher /*define for SRC_ADDR_LO word*/ 311290df1d55SAlex Deucher /*define for src_addr_31_0 field*/ 311390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 311490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 311590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 311690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 311790df1d55SAlex Deucher 311890df1d55SAlex Deucher /*define for SRC_ADDR_HI word*/ 311990df1d55SAlex Deucher /*define for src_addr_63_32 field*/ 312090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 312190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 312290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 312390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 312490df1d55SAlex Deucher 312590df1d55SAlex Deucher /*define for DST_ADDR_LO word*/ 312690df1d55SAlex Deucher /*define for dst_addr_31_0 field*/ 312790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 312890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 312990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 313090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 313190df1d55SAlex Deucher 313290df1d55SAlex Deucher /*define for DST_ADDR_HI word*/ 313390df1d55SAlex Deucher /*define for dst_addr_63_32 field*/ 313490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 313590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 313690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 313790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 313890df1d55SAlex Deucher 313990df1d55SAlex Deucher /*define for RESERVED_DW10 word*/ 314090df1d55SAlex Deucher /*define for reserved_dw10 field*/ 314190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 314290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 314390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 314490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 314590df1d55SAlex Deucher 314690df1d55SAlex Deucher /*define for RESERVED_DW11 word*/ 314790df1d55SAlex Deucher /*define for reserved_dw11 field*/ 314890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 314990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 315090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 315190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 315290df1d55SAlex Deucher 315390df1d55SAlex Deucher /*define for RESERVED_DW12 word*/ 315490df1d55SAlex Deucher /*define for reserved_dw12 field*/ 315590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 315690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 315790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 315890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 315990df1d55SAlex Deucher 316090df1d55SAlex Deucher /*define for RESERVED_DW13 word*/ 316190df1d55SAlex Deucher /*define for reserved_dw13 field*/ 316290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 316390df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 316490df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 316590df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 316690df1d55SAlex Deucher 316790df1d55SAlex Deucher /*define for COMPLETION_SIGNAL_LO word*/ 316890df1d55SAlex Deucher /*define for completion_signal_31_0 field*/ 316990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 317090df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 317190df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 317290df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 317390df1d55SAlex Deucher 317490df1d55SAlex Deucher /*define for COMPLETION_SIGNAL_HI word*/ 317590df1d55SAlex Deucher /*define for completion_signal_63_32 field*/ 317690df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 317790df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 317890df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 317990df1d55SAlex Deucher #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 318090df1d55SAlex Deucher 318190df1d55SAlex Deucher 318290df1d55SAlex Deucher /* 318390df1d55SAlex Deucher ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 318490df1d55SAlex Deucher */ 318590df1d55SAlex Deucher 318690df1d55SAlex Deucher /*define for HEADER word*/ 318790df1d55SAlex Deucher /*define for format field*/ 318890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 318990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 319090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 319190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 319290df1d55SAlex Deucher 319390df1d55SAlex Deucher /*define for barrier field*/ 319490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 319590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 319690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 319790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 319890df1d55SAlex Deucher 319990df1d55SAlex Deucher /*define for acquire_fence_scope field*/ 320090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 320190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 320290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 320390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 320490df1d55SAlex Deucher 320590df1d55SAlex Deucher /*define for release_fence_scope field*/ 320690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 320790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 320890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 320990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 321090df1d55SAlex Deucher 321190df1d55SAlex Deucher /*define for reserved field*/ 321290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 321390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 321490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 321590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 321690df1d55SAlex Deucher 321790df1d55SAlex Deucher /*define for op field*/ 321890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 321990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 322090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 322190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 322290df1d55SAlex Deucher 322390df1d55SAlex Deucher /*define for subop field*/ 322490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 322590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 322690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 322790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 322890df1d55SAlex Deucher 322990df1d55SAlex Deucher /*define for RESERVED_DW1 word*/ 323090df1d55SAlex Deucher /*define for reserved_dw1 field*/ 323190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 323290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 323390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 323490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 323590df1d55SAlex Deucher 323690df1d55SAlex Deucher /*define for DEPENDENT_ADDR_0_LO word*/ 323790df1d55SAlex Deucher /*define for dependent_addr_0_31_0 field*/ 323890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 323990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 324090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 324190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 324290df1d55SAlex Deucher 324390df1d55SAlex Deucher /*define for DEPENDENT_ADDR_0_HI word*/ 324490df1d55SAlex Deucher /*define for dependent_addr_0_63_32 field*/ 324590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 324690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 324790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 324890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 324990df1d55SAlex Deucher 325090df1d55SAlex Deucher /*define for DEPENDENT_ADDR_1_LO word*/ 325190df1d55SAlex Deucher /*define for dependent_addr_1_31_0 field*/ 325290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 325390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 325490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 325590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 325690df1d55SAlex Deucher 325790df1d55SAlex Deucher /*define for DEPENDENT_ADDR_1_HI word*/ 325890df1d55SAlex Deucher /*define for dependent_addr_1_63_32 field*/ 325990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 326090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 326190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 326290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 326390df1d55SAlex Deucher 326490df1d55SAlex Deucher /*define for DEPENDENT_ADDR_2_LO word*/ 326590df1d55SAlex Deucher /*define for dependent_addr_2_31_0 field*/ 326690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 326790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 326890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 326990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 327090df1d55SAlex Deucher 327190df1d55SAlex Deucher /*define for DEPENDENT_ADDR_2_HI word*/ 327290df1d55SAlex Deucher /*define for dependent_addr_2_63_32 field*/ 327390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 327490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 327590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 327690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 327790df1d55SAlex Deucher 327890df1d55SAlex Deucher /*define for DEPENDENT_ADDR_3_LO word*/ 327990df1d55SAlex Deucher /*define for dependent_addr_3_31_0 field*/ 328090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 328190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 328290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 328390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 328490df1d55SAlex Deucher 328590df1d55SAlex Deucher /*define for DEPENDENT_ADDR_3_HI word*/ 328690df1d55SAlex Deucher /*define for dependent_addr_3_63_32 field*/ 328790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 328890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 328990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 329090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 329190df1d55SAlex Deucher 329290df1d55SAlex Deucher /*define for DEPENDENT_ADDR_4_LO word*/ 329390df1d55SAlex Deucher /*define for dependent_addr_4_31_0 field*/ 329490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 329590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 329690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 329790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 329890df1d55SAlex Deucher 329990df1d55SAlex Deucher /*define for DEPENDENT_ADDR_4_HI word*/ 330090df1d55SAlex Deucher /*define for dependent_addr_4_63_32 field*/ 330190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 330290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 330390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 330490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 330590df1d55SAlex Deucher 330690df1d55SAlex Deucher /*define for RESERVED_DW12 word*/ 330790df1d55SAlex Deucher /*define for reserved_dw12 field*/ 330890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 330990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 331090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 331190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) 331290df1d55SAlex Deucher 331390df1d55SAlex Deucher /*define for RESERVED_DW13 word*/ 331490df1d55SAlex Deucher /*define for reserved_dw13 field*/ 331590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 331690df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 331790df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 331890df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 331990df1d55SAlex Deucher 332090df1d55SAlex Deucher /*define for COMPLETION_SIGNAL_LO word*/ 332190df1d55SAlex Deucher /*define for completion_signal_31_0 field*/ 332290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 332390df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 332490df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 332590df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 332690df1d55SAlex Deucher 332790df1d55SAlex Deucher /*define for COMPLETION_SIGNAL_HI word*/ 332890df1d55SAlex Deucher /*define for completion_signal_63_32 field*/ 332990df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 333090df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 333190df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 333290df1d55SAlex Deucher #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 333390df1d55SAlex Deucher 333490df1d55SAlex Deucher 333590df1d55SAlex Deucher #endif /* __SDMA_PKT_OPEN_H_ */ 3336