1*5e779b17SHawking Zhang /* 2*5e779b17SHawking Zhang * Copyright 2021 Advanced Micro Devices, Inc. 3*5e779b17SHawking Zhang * 4*5e779b17SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*5e779b17SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*5e779b17SHawking Zhang * to deal in the Software without restriction, including without limitation 7*5e779b17SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*5e779b17SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*5e779b17SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*5e779b17SHawking Zhang * 11*5e779b17SHawking Zhang * The above copyright notice and this permission notice shall be included in 12*5e779b17SHawking Zhang * all copies or substantial portions of the Software. 13*5e779b17SHawking Zhang * 14*5e779b17SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*5e779b17SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*5e779b17SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*5e779b17SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*5e779b17SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*5e779b17SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*5e779b17SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*5e779b17SHawking Zhang * 22*5e779b17SHawking Zhang */ 23*5e779b17SHawking Zhang #ifndef __SDMA_V6_0_0_PKT_OPEN_H_ 24*5e779b17SHawking Zhang #define __SDMA_V6_0_0_PKT_OPEN_H_ 25*5e779b17SHawking Zhang 26*5e779b17SHawking Zhang #define SDMA_OP_NOP 0 27*5e779b17SHawking Zhang #define SDMA_OP_COPY 1 28*5e779b17SHawking Zhang #define SDMA_OP_WRITE 2 29*5e779b17SHawking Zhang #define SDMA_OP_INDIRECT 4 30*5e779b17SHawking Zhang #define SDMA_OP_FENCE 5 31*5e779b17SHawking Zhang #define SDMA_OP_TRAP 6 32*5e779b17SHawking Zhang #define SDMA_OP_SEM 7 33*5e779b17SHawking Zhang #define SDMA_OP_POLL_REGMEM 8 34*5e779b17SHawking Zhang #define SDMA_OP_COND_EXE 9 35*5e779b17SHawking Zhang #define SDMA_OP_ATOMIC 10 36*5e779b17SHawking Zhang #define SDMA_OP_CONST_FILL 11 37*5e779b17SHawking Zhang #define SDMA_OP_PTEPDE 12 38*5e779b17SHawking Zhang #define SDMA_OP_TIMESTAMP 13 39*5e779b17SHawking Zhang #define SDMA_OP_SRBM_WRITE 14 40*5e779b17SHawking Zhang #define SDMA_OP_PRE_EXE 15 41*5e779b17SHawking Zhang #define SDMA_OP_GPUVM_INV 16 42*5e779b17SHawking Zhang #define SDMA_OP_GCR_REQ 17 43*5e779b17SHawking Zhang #define SDMA_OP_DUMMY_TRAP 32 44*5e779b17SHawking Zhang #define SDMA_SUBOP_TIMESTAMP_SET 0 45*5e779b17SHawking Zhang #define SDMA_SUBOP_TIMESTAMP_GET 1 46*5e779b17SHawking Zhang #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 47*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_LINEAR 0 48*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 49*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_TILED 1 50*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 51*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 52*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_SOA 3 53*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 54*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_PHY 8 55*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE 36 56*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_BC 16 57*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_TILED_BC 17 58*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 59*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 60*5e779b17SHawking Zhang #define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 61*5e779b17SHawking Zhang #define SDMA_SUBOP_WRITE_LINEAR 0 62*5e779b17SHawking Zhang #define SDMA_SUBOP_WRITE_TILED 1 63*5e779b17SHawking Zhang #define SDMA_SUBOP_WRITE_TILED_BC 17 64*5e779b17SHawking Zhang #define SDMA_SUBOP_PTEPDE_GEN 0 65*5e779b17SHawking Zhang #define SDMA_SUBOP_PTEPDE_COPY 1 66*5e779b17SHawking Zhang #define SDMA_SUBOP_PTEPDE_RMW 2 67*5e779b17SHawking Zhang #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 68*5e779b17SHawking Zhang #define SDMA_SUBOP_MEM_INCR 1 69*5e779b17SHawking Zhang #define SDMA_SUBOP_DATA_FILL_MULTI 1 70*5e779b17SHawking Zhang #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 71*5e779b17SHawking Zhang #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 72*5e779b17SHawking Zhang #define SDMA_SUBOP_POLL_MEM_VERIFY 3 73*5e779b17SHawking Zhang #define SDMA_SUBOP_VM_INVALIDATION 4 74*5e779b17SHawking Zhang #define HEADER_AGENT_DISPATCH 4 75*5e779b17SHawking Zhang #define HEADER_BARRIER 5 76*5e779b17SHawking Zhang #define SDMA_OP_AQL_COPY 0 77*5e779b17SHawking Zhang #define SDMA_OP_AQL_BARRIER_OR 0 78*5e779b17SHawking Zhang 79*5e779b17SHawking Zhang #define SDMA_GCR_RANGE_IS_PA (1 << 18) 80*5e779b17SHawking Zhang #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) 81*5e779b17SHawking Zhang #define SDMA_GCR_GL2_WB (1 << 15) 82*5e779b17SHawking Zhang #define SDMA_GCR_GL2_INV (1 << 14) 83*5e779b17SHawking Zhang #define SDMA_GCR_GL2_DISCARD (1 << 13) 84*5e779b17SHawking Zhang #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) 85*5e779b17SHawking Zhang #define SDMA_GCR_GL2_US (1 << 10) 86*5e779b17SHawking Zhang #define SDMA_GCR_GL1_INV (1 << 9) 87*5e779b17SHawking Zhang #define SDMA_GCR_GLV_INV (1 << 8) 88*5e779b17SHawking Zhang #define SDMA_GCR_GLK_INV (1 << 7) 89*5e779b17SHawking Zhang #define SDMA_GCR_GLK_WB (1 << 6) 90*5e779b17SHawking Zhang #define SDMA_GCR_GLM_INV (1 << 5) 91*5e779b17SHawking Zhang #define SDMA_GCR_GLM_WB (1 << 4) 92*5e779b17SHawking Zhang #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) 93*5e779b17SHawking Zhang #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) 94*5e779b17SHawking Zhang /* 95*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR packet 96*5e779b17SHawking Zhang */ 97*5e779b17SHawking Zhang 98*5e779b17SHawking Zhang /*define for HEADER word*/ 99*5e779b17SHawking Zhang /*define for op field*/ 100*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 101*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 102*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 103*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 104*5e779b17SHawking Zhang 105*5e779b17SHawking Zhang /*define for sub_op field*/ 106*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 107*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 108*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 109*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 110*5e779b17SHawking Zhang 111*5e779b17SHawking Zhang /*define for encrypt field*/ 112*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 113*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 114*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 115*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 116*5e779b17SHawking Zhang 117*5e779b17SHawking Zhang /*define for tmz field*/ 118*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 119*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 120*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 121*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 122*5e779b17SHawking Zhang 123*5e779b17SHawking Zhang /*define for cpv field*/ 124*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset 0 125*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 126*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift 19 127*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift) 128*5e779b17SHawking Zhang 129*5e779b17SHawking Zhang /*define for backwards field*/ 130*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 131*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 132*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 133*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) 134*5e779b17SHawking Zhang 135*5e779b17SHawking Zhang /*define for broadcast field*/ 136*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 137*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 138*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 139*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 140*5e779b17SHawking Zhang 141*5e779b17SHawking Zhang /*define for COUNT word*/ 142*5e779b17SHawking Zhang /*define for count field*/ 143*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 144*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x3FFFFFFF 145*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 146*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 147*5e779b17SHawking Zhang 148*5e779b17SHawking Zhang /*define for PARAMETER word*/ 149*5e779b17SHawking Zhang /*define for dst_sw field*/ 150*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 151*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 152*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 153*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 154*5e779b17SHawking Zhang 155*5e779b17SHawking Zhang /*define for dst_cache_policy field*/ 156*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 2 157*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 158*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 159*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) 160*5e779b17SHawking Zhang 161*5e779b17SHawking Zhang /*define for src_sw field*/ 162*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 163*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 164*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 165*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 166*5e779b17SHawking Zhang 167*5e779b17SHawking Zhang /*define for src_cache_policy field*/ 168*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 2 169*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 170*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 171*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) 172*5e779b17SHawking Zhang 173*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 174*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 175*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 176*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 177*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 178*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 179*5e779b17SHawking Zhang 180*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 181*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 182*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 183*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 184*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 185*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 186*5e779b17SHawking Zhang 187*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 188*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 189*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 190*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 191*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 192*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 193*5e779b17SHawking Zhang 194*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 195*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 196*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 197*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 198*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 199*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 200*5e779b17SHawking Zhang 201*5e779b17SHawking Zhang 202*5e779b17SHawking Zhang /* 203*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_BC packet 204*5e779b17SHawking Zhang */ 205*5e779b17SHawking Zhang 206*5e779b17SHawking Zhang /*define for HEADER word*/ 207*5e779b17SHawking Zhang /*define for op field*/ 208*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 209*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF 210*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 211*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) 212*5e779b17SHawking Zhang 213*5e779b17SHawking Zhang /*define for sub_op field*/ 214*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 215*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF 216*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 217*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) 218*5e779b17SHawking Zhang 219*5e779b17SHawking Zhang /*define for COUNT word*/ 220*5e779b17SHawking Zhang /*define for count field*/ 221*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 222*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF 223*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 224*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) 225*5e779b17SHawking Zhang 226*5e779b17SHawking Zhang /*define for PARAMETER word*/ 227*5e779b17SHawking Zhang /*define for dst_sw field*/ 228*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 229*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 230*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 231*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) 232*5e779b17SHawking Zhang 233*5e779b17SHawking Zhang /*define for dst_ha field*/ 234*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 235*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 236*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 19 237*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) 238*5e779b17SHawking Zhang 239*5e779b17SHawking Zhang /*define for src_sw field*/ 240*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 241*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 242*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 243*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) 244*5e779b17SHawking Zhang 245*5e779b17SHawking Zhang /*define for src_ha field*/ 246*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 247*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 248*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 27 249*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) 250*5e779b17SHawking Zhang 251*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 252*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 253*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 254*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 255*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 256*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) 257*5e779b17SHawking Zhang 258*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 259*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 260*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 261*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 262*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 263*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) 264*5e779b17SHawking Zhang 265*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 266*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 267*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 268*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 269*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 270*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) 271*5e779b17SHawking Zhang 272*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 273*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 274*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 275*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 276*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 277*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) 278*5e779b17SHawking Zhang 279*5e779b17SHawking Zhang 280*5e779b17SHawking Zhang /* 281*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 282*5e779b17SHawking Zhang */ 283*5e779b17SHawking Zhang 284*5e779b17SHawking Zhang /*define for HEADER word*/ 285*5e779b17SHawking Zhang /*define for op field*/ 286*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 287*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 288*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 289*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 290*5e779b17SHawking Zhang 291*5e779b17SHawking Zhang /*define for sub_op field*/ 292*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 293*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 294*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 295*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 296*5e779b17SHawking Zhang 297*5e779b17SHawking Zhang /*define for tmz field*/ 298*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 299*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 300*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 301*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 302*5e779b17SHawking Zhang 303*5e779b17SHawking Zhang /*define for cpv field*/ 304*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset 0 305*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask 0x00000001 306*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift 19 307*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift) 308*5e779b17SHawking Zhang 309*5e779b17SHawking Zhang /*define for all field*/ 310*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 311*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 312*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 313*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 314*5e779b17SHawking Zhang 315*5e779b17SHawking Zhang /*define for COUNT word*/ 316*5e779b17SHawking Zhang /*define for count field*/ 317*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 318*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 319*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 320*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 321*5e779b17SHawking Zhang 322*5e779b17SHawking Zhang /*define for PARAMETER word*/ 323*5e779b17SHawking Zhang /*define for dst_mtype field*/ 324*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 325*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 326*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 327*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) 328*5e779b17SHawking Zhang 329*5e779b17SHawking Zhang /*define for dst_l2_policy field*/ 330*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 331*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 332*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 333*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) 334*5e779b17SHawking Zhang 335*5e779b17SHawking Zhang /*define for dst_llc field*/ 336*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset 2 337*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask 0x00000001 338*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift 8 339*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift) 340*5e779b17SHawking Zhang 341*5e779b17SHawking Zhang /*define for src_mtype field*/ 342*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 343*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 344*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 345*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) 346*5e779b17SHawking Zhang 347*5e779b17SHawking Zhang /*define for src_l2_policy field*/ 348*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 349*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 350*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 351*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) 352*5e779b17SHawking Zhang 353*5e779b17SHawking Zhang /*define for src_llc field*/ 354*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset 2 355*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask 0x00000001 356*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift 16 357*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift) 358*5e779b17SHawking Zhang 359*5e779b17SHawking Zhang /*define for dst_sw field*/ 360*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 361*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 362*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 17 363*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 364*5e779b17SHawking Zhang 365*5e779b17SHawking Zhang /*define for dst_gcc field*/ 366*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 367*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 368*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 369*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 370*5e779b17SHawking Zhang 371*5e779b17SHawking Zhang /*define for dst_sys field*/ 372*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 373*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 374*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 375*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 376*5e779b17SHawking Zhang 377*5e779b17SHawking Zhang /*define for dst_snoop field*/ 378*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 379*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 380*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 381*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 382*5e779b17SHawking Zhang 383*5e779b17SHawking Zhang /*define for dst_gpa field*/ 384*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 385*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 386*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 387*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 388*5e779b17SHawking Zhang 389*5e779b17SHawking Zhang /*define for src_sw field*/ 390*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 391*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 392*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 393*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 394*5e779b17SHawking Zhang 395*5e779b17SHawking Zhang /*define for src_sys field*/ 396*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 397*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 398*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 399*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 400*5e779b17SHawking Zhang 401*5e779b17SHawking Zhang /*define for src_snoop field*/ 402*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 403*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 404*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 405*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 406*5e779b17SHawking Zhang 407*5e779b17SHawking Zhang /*define for src_gpa field*/ 408*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 409*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 410*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 411*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 412*5e779b17SHawking Zhang 413*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 414*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 415*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 416*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 417*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 418*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 419*5e779b17SHawking Zhang 420*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 421*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 422*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 423*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 424*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 425*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 426*5e779b17SHawking Zhang 427*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 428*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 429*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 430*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 431*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 432*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 433*5e779b17SHawking Zhang 434*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 435*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 436*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 437*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 438*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 439*5e779b17SHawking Zhang #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 440*5e779b17SHawking Zhang 441*5e779b17SHawking Zhang 442*5e779b17SHawking Zhang /* 443*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 444*5e779b17SHawking Zhang */ 445*5e779b17SHawking Zhang 446*5e779b17SHawking Zhang /*define for HEADER word*/ 447*5e779b17SHawking Zhang /*define for op field*/ 448*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 449*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 450*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 451*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 452*5e779b17SHawking Zhang 453*5e779b17SHawking Zhang /*define for sub_op field*/ 454*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 455*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 456*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 457*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 458*5e779b17SHawking Zhang 459*5e779b17SHawking Zhang /*define for tmz field*/ 460*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 461*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 462*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 463*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 464*5e779b17SHawking Zhang 465*5e779b17SHawking Zhang /*define for cpv field*/ 466*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset 0 467*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask 0x00000001 468*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift 19 469*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift) 470*5e779b17SHawking Zhang 471*5e779b17SHawking Zhang /*define for COUNT word*/ 472*5e779b17SHawking Zhang /*define for count field*/ 473*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 474*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 475*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 476*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 477*5e779b17SHawking Zhang 478*5e779b17SHawking Zhang /*define for addr_pair_num field*/ 479*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset 1 480*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask 0x000000FF 481*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift 24 482*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift) 483*5e779b17SHawking Zhang 484*5e779b17SHawking Zhang /*define for PARAMETER word*/ 485*5e779b17SHawking Zhang /*define for dst_mtype field*/ 486*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 487*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 488*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 489*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) 490*5e779b17SHawking Zhang 491*5e779b17SHawking Zhang /*define for dst_l2_policy field*/ 492*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 493*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 494*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 495*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) 496*5e779b17SHawking Zhang 497*5e779b17SHawking Zhang /*define for dst_llc field*/ 498*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset 2 499*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask 0x00000001 500*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift 8 501*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift) 502*5e779b17SHawking Zhang 503*5e779b17SHawking Zhang /*define for src_mtype field*/ 504*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 505*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 506*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 507*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) 508*5e779b17SHawking Zhang 509*5e779b17SHawking Zhang /*define for src_l2_policy field*/ 510*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 511*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 512*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 513*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) 514*5e779b17SHawking Zhang 515*5e779b17SHawking Zhang /*define for src_llc field*/ 516*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset 2 517*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask 0x00000001 518*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift 16 519*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift) 520*5e779b17SHawking Zhang 521*5e779b17SHawking Zhang /*define for dst_sw field*/ 522*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 523*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 524*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 17 525*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 526*5e779b17SHawking Zhang 527*5e779b17SHawking Zhang /*define for dst_gcc field*/ 528*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 529*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 530*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 531*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 532*5e779b17SHawking Zhang 533*5e779b17SHawking Zhang /*define for dst_sys field*/ 534*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 535*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 536*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 537*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 538*5e779b17SHawking Zhang 539*5e779b17SHawking Zhang /*define for dst_log field*/ 540*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 541*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 542*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 543*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 544*5e779b17SHawking Zhang 545*5e779b17SHawking Zhang /*define for dst_snoop field*/ 546*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 547*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 548*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 549*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 550*5e779b17SHawking Zhang 551*5e779b17SHawking Zhang /*define for dst_gpa field*/ 552*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 553*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 554*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 555*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 556*5e779b17SHawking Zhang 557*5e779b17SHawking Zhang /*define for src_sw field*/ 558*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 559*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 560*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 561*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 562*5e779b17SHawking Zhang 563*5e779b17SHawking Zhang /*define for src_gcc field*/ 564*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 565*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 566*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 567*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 568*5e779b17SHawking Zhang 569*5e779b17SHawking Zhang /*define for src_sys field*/ 570*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 571*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 572*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 573*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 574*5e779b17SHawking Zhang 575*5e779b17SHawking Zhang /*define for src_snoop field*/ 576*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 577*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 578*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 579*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 580*5e779b17SHawking Zhang 581*5e779b17SHawking Zhang /*define for src_gpa field*/ 582*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 583*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 584*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 585*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 586*5e779b17SHawking Zhang 587*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 588*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 589*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 590*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 591*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 592*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 593*5e779b17SHawking Zhang 594*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 595*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 596*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 597*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 598*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 599*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 600*5e779b17SHawking Zhang 601*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 602*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 603*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 604*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 605*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 606*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 607*5e779b17SHawking Zhang 608*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 609*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 610*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 611*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 612*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 613*5e779b17SHawking Zhang #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 614*5e779b17SHawking Zhang 615*5e779b17SHawking Zhang 616*5e779b17SHawking Zhang /* 617*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 618*5e779b17SHawking Zhang */ 619*5e779b17SHawking Zhang 620*5e779b17SHawking Zhang /*define for HEADER word*/ 621*5e779b17SHawking Zhang /*define for op field*/ 622*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 623*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 624*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 625*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 626*5e779b17SHawking Zhang 627*5e779b17SHawking Zhang /*define for sub_op field*/ 628*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 629*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 630*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 631*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 632*5e779b17SHawking Zhang 633*5e779b17SHawking Zhang /*define for encrypt field*/ 634*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 635*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 636*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 637*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 638*5e779b17SHawking Zhang 639*5e779b17SHawking Zhang /*define for tmz field*/ 640*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 641*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 642*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 643*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 644*5e779b17SHawking Zhang 645*5e779b17SHawking Zhang /*define for cpv field*/ 646*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset 0 647*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask 0x00000001 648*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift 19 649*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift) 650*5e779b17SHawking Zhang 651*5e779b17SHawking Zhang /*define for broadcast field*/ 652*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 653*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 654*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 655*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 656*5e779b17SHawking Zhang 657*5e779b17SHawking Zhang /*define for COUNT word*/ 658*5e779b17SHawking Zhang /*define for count field*/ 659*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 660*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x3FFFFFFF 661*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 662*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 663*5e779b17SHawking Zhang 664*5e779b17SHawking Zhang /*define for PARAMETER word*/ 665*5e779b17SHawking Zhang /*define for dst2_sw field*/ 666*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 667*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 668*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 669*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 670*5e779b17SHawking Zhang 671*5e779b17SHawking Zhang /*define for dst2_cache_policy field*/ 672*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset 2 673*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask 0x00000007 674*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift 10 675*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift) 676*5e779b17SHawking Zhang 677*5e779b17SHawking Zhang /*define for dst1_sw field*/ 678*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 679*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 680*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 681*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 682*5e779b17SHawking Zhang 683*5e779b17SHawking Zhang /*define for dst1_cache_policy field*/ 684*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset 2 685*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask 0x00000007 686*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift 18 687*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift) 688*5e779b17SHawking Zhang 689*5e779b17SHawking Zhang /*define for src_sw field*/ 690*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 691*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 692*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 693*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 694*5e779b17SHawking Zhang 695*5e779b17SHawking Zhang /*define for src_cache_policy field*/ 696*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset 2 697*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 698*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift 26 699*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift) 700*5e779b17SHawking Zhang 701*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 702*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 703*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 704*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 705*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 706*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 707*5e779b17SHawking Zhang 708*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 709*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 710*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 711*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 712*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 713*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 714*5e779b17SHawking Zhang 715*5e779b17SHawking Zhang /*define for DST1_ADDR_LO word*/ 716*5e779b17SHawking Zhang /*define for dst1_addr_31_0 field*/ 717*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 718*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 719*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 720*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 721*5e779b17SHawking Zhang 722*5e779b17SHawking Zhang /*define for DST1_ADDR_HI word*/ 723*5e779b17SHawking Zhang /*define for dst1_addr_63_32 field*/ 724*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 725*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 726*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 727*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 728*5e779b17SHawking Zhang 729*5e779b17SHawking Zhang /*define for DST2_ADDR_LO word*/ 730*5e779b17SHawking Zhang /*define for dst2_addr_31_0 field*/ 731*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 732*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 733*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 734*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 735*5e779b17SHawking Zhang 736*5e779b17SHawking Zhang /*define for DST2_ADDR_HI word*/ 737*5e779b17SHawking Zhang /*define for dst2_addr_63_32 field*/ 738*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 739*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 740*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 741*5e779b17SHawking Zhang #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 742*5e779b17SHawking Zhang 743*5e779b17SHawking Zhang 744*5e779b17SHawking Zhang /* 745*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 746*5e779b17SHawking Zhang */ 747*5e779b17SHawking Zhang 748*5e779b17SHawking Zhang /*define for HEADER word*/ 749*5e779b17SHawking Zhang /*define for op field*/ 750*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 751*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 752*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 753*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 754*5e779b17SHawking Zhang 755*5e779b17SHawking Zhang /*define for sub_op field*/ 756*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 757*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 758*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 759*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 760*5e779b17SHawking Zhang 761*5e779b17SHawking Zhang /*define for tmz field*/ 762*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 763*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 764*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 765*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 766*5e779b17SHawking Zhang 767*5e779b17SHawking Zhang /*define for cpv field*/ 768*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset 0 769*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask 0x00000001 770*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift 19 771*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift) 772*5e779b17SHawking Zhang 773*5e779b17SHawking Zhang /*define for elementsize field*/ 774*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 775*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 776*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 777*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 778*5e779b17SHawking Zhang 779*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 780*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 781*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 782*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 783*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 784*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 785*5e779b17SHawking Zhang 786*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 787*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 788*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 789*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 790*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 791*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 792*5e779b17SHawking Zhang 793*5e779b17SHawking Zhang /*define for DW_3 word*/ 794*5e779b17SHawking Zhang /*define for src_x field*/ 795*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 796*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 797*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 798*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 799*5e779b17SHawking Zhang 800*5e779b17SHawking Zhang /*define for src_y field*/ 801*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 802*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 803*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 804*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 805*5e779b17SHawking Zhang 806*5e779b17SHawking Zhang /*define for DW_4 word*/ 807*5e779b17SHawking Zhang /*define for src_z field*/ 808*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 809*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF 810*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 811*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 812*5e779b17SHawking Zhang 813*5e779b17SHawking Zhang /*define for src_pitch field*/ 814*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 815*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 816*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 817*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 818*5e779b17SHawking Zhang 819*5e779b17SHawking Zhang /*define for DW_5 word*/ 820*5e779b17SHawking Zhang /*define for src_slice_pitch field*/ 821*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 822*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 823*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 824*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 825*5e779b17SHawking Zhang 826*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 827*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 828*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 829*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 830*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 831*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 832*5e779b17SHawking Zhang 833*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 834*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 835*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 836*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 837*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 838*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 839*5e779b17SHawking Zhang 840*5e779b17SHawking Zhang /*define for DW_8 word*/ 841*5e779b17SHawking Zhang /*define for dst_x field*/ 842*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 843*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 844*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 845*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 846*5e779b17SHawking Zhang 847*5e779b17SHawking Zhang /*define for dst_y field*/ 848*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 849*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 850*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 851*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 852*5e779b17SHawking Zhang 853*5e779b17SHawking Zhang /*define for DW_9 word*/ 854*5e779b17SHawking Zhang /*define for dst_z field*/ 855*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 856*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF 857*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 858*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 859*5e779b17SHawking Zhang 860*5e779b17SHawking Zhang /*define for dst_pitch field*/ 861*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 862*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 863*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 864*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 865*5e779b17SHawking Zhang 866*5e779b17SHawking Zhang /*define for DW_10 word*/ 867*5e779b17SHawking Zhang /*define for dst_slice_pitch field*/ 868*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 869*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 870*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 871*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 872*5e779b17SHawking Zhang 873*5e779b17SHawking Zhang /*define for DW_11 word*/ 874*5e779b17SHawking Zhang /*define for rect_x field*/ 875*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 876*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 877*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 878*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 879*5e779b17SHawking Zhang 880*5e779b17SHawking Zhang /*define for rect_y field*/ 881*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 882*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 883*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 884*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 885*5e779b17SHawking Zhang 886*5e779b17SHawking Zhang /*define for DW_12 word*/ 887*5e779b17SHawking Zhang /*define for rect_z field*/ 888*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 889*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF 890*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 891*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 892*5e779b17SHawking Zhang 893*5e779b17SHawking Zhang /*define for dst_sw field*/ 894*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 895*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 896*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 897*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 898*5e779b17SHawking Zhang 899*5e779b17SHawking Zhang /*define for dst_cache_policy field*/ 900*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset 12 901*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask 0x00000007 902*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift 18 903*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift) 904*5e779b17SHawking Zhang 905*5e779b17SHawking Zhang /*define for src_sw field*/ 906*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 907*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 908*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 909*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 910*5e779b17SHawking Zhang 911*5e779b17SHawking Zhang /*define for src_cache_policy field*/ 912*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset 12 913*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask 0x00000007 914*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift 26 915*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift) 916*5e779b17SHawking Zhang 917*5e779b17SHawking Zhang 918*5e779b17SHawking Zhang /* 919*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE packet 920*5e779b17SHawking Zhang */ 921*5e779b17SHawking Zhang 922*5e779b17SHawking Zhang /*define for HEADER word*/ 923*5e779b17SHawking Zhang /*define for op field*/ 924*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset 0 925*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask 0x000000FF 926*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift 0 927*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift) 928*5e779b17SHawking Zhang 929*5e779b17SHawking Zhang /*define for sub_op field*/ 930*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset 0 931*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask 0x000000FF 932*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift 8 933*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift) 934*5e779b17SHawking Zhang 935*5e779b17SHawking Zhang /*define for tmz field*/ 936*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset 0 937*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask 0x00000001 938*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift 18 939*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift) 940*5e779b17SHawking Zhang 941*5e779b17SHawking Zhang /*define for cpv field*/ 942*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset 0 943*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask 0x00000001 944*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift 19 945*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift) 946*5e779b17SHawking Zhang 947*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 948*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 949*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset 1 950*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 951*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift 0 952*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift) 953*5e779b17SHawking Zhang 954*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 955*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 956*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset 2 957*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 958*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift 0 959*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift) 960*5e779b17SHawking Zhang 961*5e779b17SHawking Zhang /*define for DW_3 word*/ 962*5e779b17SHawking Zhang /*define for src_x field*/ 963*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset 3 964*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask 0xFFFFFFFF 965*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift 0 966*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift) 967*5e779b17SHawking Zhang 968*5e779b17SHawking Zhang /*define for DW_4 word*/ 969*5e779b17SHawking Zhang /*define for src_y field*/ 970*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset 4 971*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask 0xFFFFFFFF 972*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift 0 973*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift) 974*5e779b17SHawking Zhang 975*5e779b17SHawking Zhang /*define for DW_5 word*/ 976*5e779b17SHawking Zhang /*define for src_z field*/ 977*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset 5 978*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask 0xFFFFFFFF 979*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift 0 980*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift) 981*5e779b17SHawking Zhang 982*5e779b17SHawking Zhang /*define for DW_6 word*/ 983*5e779b17SHawking Zhang /*define for src_pitch field*/ 984*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset 6 985*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask 0xFFFFFFFF 986*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift 0 987*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift) 988*5e779b17SHawking Zhang 989*5e779b17SHawking Zhang /*define for DW_7 word*/ 990*5e779b17SHawking Zhang /*define for src_slice_pitch_31_0 field*/ 991*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset 7 992*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask 0xFFFFFFFF 993*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift 0 994*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift) 995*5e779b17SHawking Zhang 996*5e779b17SHawking Zhang /*define for DW_8 word*/ 997*5e779b17SHawking Zhang /*define for src_slice_pitch_47_32 field*/ 998*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset 8 999*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask 0x0000FFFF 1000*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift 0 1001*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift) 1002*5e779b17SHawking Zhang 1003*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 1004*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 1005*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset 9 1006*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1007*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift 0 1008*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift) 1009*5e779b17SHawking Zhang 1010*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 1011*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 1012*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset 10 1013*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1014*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift 0 1015*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift) 1016*5e779b17SHawking Zhang 1017*5e779b17SHawking Zhang /*define for DW_11 word*/ 1018*5e779b17SHawking Zhang /*define for dst_x field*/ 1019*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset 11 1020*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask 0xFFFFFFFF 1021*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift 0 1022*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift) 1023*5e779b17SHawking Zhang 1024*5e779b17SHawking Zhang /*define for DW_12 word*/ 1025*5e779b17SHawking Zhang /*define for dst_y field*/ 1026*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset 12 1027*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask 0xFFFFFFFF 1028*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift 0 1029*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift) 1030*5e779b17SHawking Zhang 1031*5e779b17SHawking Zhang /*define for DW_13 word*/ 1032*5e779b17SHawking Zhang /*define for dst_z field*/ 1033*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset 13 1034*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask 0xFFFFFFFF 1035*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift 0 1036*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift) 1037*5e779b17SHawking Zhang 1038*5e779b17SHawking Zhang /*define for DW_14 word*/ 1039*5e779b17SHawking Zhang /*define for dst_pitch field*/ 1040*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset 14 1041*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask 0xFFFFFFFF 1042*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift 0 1043*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift) 1044*5e779b17SHawking Zhang 1045*5e779b17SHawking Zhang /*define for DW_15 word*/ 1046*5e779b17SHawking Zhang /*define for dst_slice_pitch_31_0 field*/ 1047*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset 15 1048*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask 0xFFFFFFFF 1049*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift 0 1050*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift) 1051*5e779b17SHawking Zhang 1052*5e779b17SHawking Zhang /*define for DW_16 word*/ 1053*5e779b17SHawking Zhang /*define for dst_slice_pitch_47_32 field*/ 1054*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset 16 1055*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask 0x0000FFFF 1056*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift 0 1057*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift) 1058*5e779b17SHawking Zhang 1059*5e779b17SHawking Zhang /*define for dst_sw field*/ 1060*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset 16 1061*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask 0x00000003 1062*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift 16 1063*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift) 1064*5e779b17SHawking Zhang 1065*5e779b17SHawking Zhang /*define for dst_policy field*/ 1066*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset 16 1067*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask 0x00000007 1068*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift 18 1069*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift) 1070*5e779b17SHawking Zhang 1071*5e779b17SHawking Zhang /*define for src_sw field*/ 1072*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset 16 1073*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask 0x00000003 1074*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift 24 1075*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift) 1076*5e779b17SHawking Zhang 1077*5e779b17SHawking Zhang /*define for src_policy field*/ 1078*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset 16 1079*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask 0x00000007 1080*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift 26 1081*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift) 1082*5e779b17SHawking Zhang 1083*5e779b17SHawking Zhang /*define for DW_17 word*/ 1084*5e779b17SHawking Zhang /*define for rect_x field*/ 1085*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset 17 1086*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask 0xFFFFFFFF 1087*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift 0 1088*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift) 1089*5e779b17SHawking Zhang 1090*5e779b17SHawking Zhang /*define for DW_18 word*/ 1091*5e779b17SHawking Zhang /*define for rect_y field*/ 1092*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset 18 1093*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask 0xFFFFFFFF 1094*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift 0 1095*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift) 1096*5e779b17SHawking Zhang 1097*5e779b17SHawking Zhang /*define for DW_19 word*/ 1098*5e779b17SHawking Zhang /*define for rect_z field*/ 1099*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset 19 1100*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask 0xFFFFFFFF 1101*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift 0 1102*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift) 1103*5e779b17SHawking Zhang 1104*5e779b17SHawking Zhang 1105*5e779b17SHawking Zhang /* 1106*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet 1107*5e779b17SHawking Zhang */ 1108*5e779b17SHawking Zhang 1109*5e779b17SHawking Zhang /*define for HEADER word*/ 1110*5e779b17SHawking Zhang /*define for op field*/ 1111*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 1112*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF 1113*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 1114*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) 1115*5e779b17SHawking Zhang 1116*5e779b17SHawking Zhang /*define for sub_op field*/ 1117*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 1118*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 1119*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 1120*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) 1121*5e779b17SHawking Zhang 1122*5e779b17SHawking Zhang /*define for elementsize field*/ 1123*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 1124*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 1125*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 1126*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) 1127*5e779b17SHawking Zhang 1128*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 1129*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 1130*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 1131*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1132*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 1133*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) 1134*5e779b17SHawking Zhang 1135*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 1136*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 1137*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 1138*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1139*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 1140*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) 1141*5e779b17SHawking Zhang 1142*5e779b17SHawking Zhang /*define for DW_3 word*/ 1143*5e779b17SHawking Zhang /*define for src_x field*/ 1144*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 1145*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF 1146*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 1147*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) 1148*5e779b17SHawking Zhang 1149*5e779b17SHawking Zhang /*define for src_y field*/ 1150*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 1151*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF 1152*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 1153*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) 1154*5e779b17SHawking Zhang 1155*5e779b17SHawking Zhang /*define for DW_4 word*/ 1156*5e779b17SHawking Zhang /*define for src_z field*/ 1157*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 1158*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF 1159*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 1160*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) 1161*5e779b17SHawking Zhang 1162*5e779b17SHawking Zhang /*define for src_pitch field*/ 1163*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 1164*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF 1165*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 1166*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) 1167*5e779b17SHawking Zhang 1168*5e779b17SHawking Zhang /*define for DW_5 word*/ 1169*5e779b17SHawking Zhang /*define for src_slice_pitch field*/ 1170*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 1171*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF 1172*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 1173*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) 1174*5e779b17SHawking Zhang 1175*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 1176*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 1177*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 1178*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1179*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 1180*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) 1181*5e779b17SHawking Zhang 1182*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 1183*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 1184*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 1185*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1186*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 1187*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) 1188*5e779b17SHawking Zhang 1189*5e779b17SHawking Zhang /*define for DW_8 word*/ 1190*5e779b17SHawking Zhang /*define for dst_x field*/ 1191*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 1192*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF 1193*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 1194*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) 1195*5e779b17SHawking Zhang 1196*5e779b17SHawking Zhang /*define for dst_y field*/ 1197*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 1198*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF 1199*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 1200*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) 1201*5e779b17SHawking Zhang 1202*5e779b17SHawking Zhang /*define for DW_9 word*/ 1203*5e779b17SHawking Zhang /*define for dst_z field*/ 1204*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 1205*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF 1206*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 1207*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) 1208*5e779b17SHawking Zhang 1209*5e779b17SHawking Zhang /*define for dst_pitch field*/ 1210*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 1211*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF 1212*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 1213*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) 1214*5e779b17SHawking Zhang 1215*5e779b17SHawking Zhang /*define for DW_10 word*/ 1216*5e779b17SHawking Zhang /*define for dst_slice_pitch field*/ 1217*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 1218*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 1219*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 1220*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) 1221*5e779b17SHawking Zhang 1222*5e779b17SHawking Zhang /*define for DW_11 word*/ 1223*5e779b17SHawking Zhang /*define for rect_x field*/ 1224*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 1225*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF 1226*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 1227*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) 1228*5e779b17SHawking Zhang 1229*5e779b17SHawking Zhang /*define for rect_y field*/ 1230*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 1231*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF 1232*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 1233*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) 1234*5e779b17SHawking Zhang 1235*5e779b17SHawking Zhang /*define for DW_12 word*/ 1236*5e779b17SHawking Zhang /*define for rect_z field*/ 1237*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 1238*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF 1239*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 1240*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) 1241*5e779b17SHawking Zhang 1242*5e779b17SHawking Zhang /*define for dst_sw field*/ 1243*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 1244*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 1245*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 1246*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) 1247*5e779b17SHawking Zhang 1248*5e779b17SHawking Zhang /*define for dst_ha field*/ 1249*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 1250*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 1251*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 19 1252*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) 1253*5e779b17SHawking Zhang 1254*5e779b17SHawking Zhang /*define for src_sw field*/ 1255*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 1256*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 1257*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 1258*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) 1259*5e779b17SHawking Zhang 1260*5e779b17SHawking Zhang /*define for src_ha field*/ 1261*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 1262*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 1263*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 27 1264*5e779b17SHawking Zhang #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) 1265*5e779b17SHawking Zhang 1266*5e779b17SHawking Zhang 1267*5e779b17SHawking Zhang /* 1268*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED packet 1269*5e779b17SHawking Zhang */ 1270*5e779b17SHawking Zhang 1271*5e779b17SHawking Zhang /*define for HEADER word*/ 1272*5e779b17SHawking Zhang /*define for op field*/ 1273*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 1274*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 1275*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 1276*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 1277*5e779b17SHawking Zhang 1278*5e779b17SHawking Zhang /*define for sub_op field*/ 1279*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 1280*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 1281*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 1282*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 1283*5e779b17SHawking Zhang 1284*5e779b17SHawking Zhang /*define for encrypt field*/ 1285*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 1286*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 1287*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 1288*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 1289*5e779b17SHawking Zhang 1290*5e779b17SHawking Zhang /*define for tmz field*/ 1291*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 1292*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 1293*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 1294*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 1295*5e779b17SHawking Zhang 1296*5e779b17SHawking Zhang /*define for cpv field*/ 1297*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_cpv_offset 0 1298*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_cpv_mask 0x00000001 1299*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_cpv_shift 19 1300*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_HEADER_cpv_shift) 1301*5e779b17SHawking Zhang 1302*5e779b17SHawking Zhang /*define for detile field*/ 1303*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 1304*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 1305*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 1306*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 1307*5e779b17SHawking Zhang 1308*5e779b17SHawking Zhang /*define for TILED_ADDR_LO word*/ 1309*5e779b17SHawking Zhang /*define for tiled_addr_31_0 field*/ 1310*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1311*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1312*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1313*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 1314*5e779b17SHawking Zhang 1315*5e779b17SHawking Zhang /*define for TILED_ADDR_HI word*/ 1316*5e779b17SHawking Zhang /*define for tiled_addr_63_32 field*/ 1317*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1318*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1319*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1320*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 1321*5e779b17SHawking Zhang 1322*5e779b17SHawking Zhang /*define for DW_3 word*/ 1323*5e779b17SHawking Zhang /*define for width field*/ 1324*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 1325*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 1326*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 1327*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 1328*5e779b17SHawking Zhang 1329*5e779b17SHawking Zhang /*define for DW_4 word*/ 1330*5e779b17SHawking Zhang /*define for height field*/ 1331*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 1332*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 1333*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 1334*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 1335*5e779b17SHawking Zhang 1336*5e779b17SHawking Zhang /*define for depth field*/ 1337*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 1338*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF 1339*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 1340*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 1341*5e779b17SHawking Zhang 1342*5e779b17SHawking Zhang /*define for DW_5 word*/ 1343*5e779b17SHawking Zhang /*define for element_size field*/ 1344*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 1345*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 1346*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 1347*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 1348*5e779b17SHawking Zhang 1349*5e779b17SHawking Zhang /*define for swizzle_mode field*/ 1350*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 1351*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 1352*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 1353*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 1354*5e779b17SHawking Zhang 1355*5e779b17SHawking Zhang /*define for dimension field*/ 1356*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 1357*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 1358*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 1359*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 1360*5e779b17SHawking Zhang 1361*5e779b17SHawking Zhang /*define for mip_max field*/ 1362*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 1363*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F 1364*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 1365*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) 1366*5e779b17SHawking Zhang 1367*5e779b17SHawking Zhang /*define for DW_6 word*/ 1368*5e779b17SHawking Zhang /*define for x field*/ 1369*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 1370*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 1371*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 1372*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 1373*5e779b17SHawking Zhang 1374*5e779b17SHawking Zhang /*define for y field*/ 1375*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 1376*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 1377*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 1378*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 1379*5e779b17SHawking Zhang 1380*5e779b17SHawking Zhang /*define for DW_7 word*/ 1381*5e779b17SHawking Zhang /*define for z field*/ 1382*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 1383*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF 1384*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 1385*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 1386*5e779b17SHawking Zhang 1387*5e779b17SHawking Zhang /*define for linear_sw field*/ 1388*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 1389*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 1390*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 1391*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 1392*5e779b17SHawking Zhang 1393*5e779b17SHawking Zhang /*define for linear_cache_policy field*/ 1394*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset 7 1395*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask 0x00000007 1396*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift 18 1397*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift) 1398*5e779b17SHawking Zhang 1399*5e779b17SHawking Zhang /*define for tile_sw field*/ 1400*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 1401*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 1402*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 1403*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 1404*5e779b17SHawking Zhang 1405*5e779b17SHawking Zhang /*define for tile_cache_policy field*/ 1406*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset 7 1407*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask 0x00000007 1408*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift 26 1409*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift) 1410*5e779b17SHawking Zhang 1411*5e779b17SHawking Zhang /*define for LINEAR_ADDR_LO word*/ 1412*5e779b17SHawking Zhang /*define for linear_addr_31_0 field*/ 1413*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1414*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1415*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1416*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1417*5e779b17SHawking Zhang 1418*5e779b17SHawking Zhang /*define for LINEAR_ADDR_HI word*/ 1419*5e779b17SHawking Zhang /*define for linear_addr_63_32 field*/ 1420*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1421*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1422*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1423*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1424*5e779b17SHawking Zhang 1425*5e779b17SHawking Zhang /*define for LINEAR_PITCH word*/ 1426*5e779b17SHawking Zhang /*define for linear_pitch field*/ 1427*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 1428*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1429*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 1430*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 1431*5e779b17SHawking Zhang 1432*5e779b17SHawking Zhang /*define for LINEAR_SLICE_PITCH word*/ 1433*5e779b17SHawking Zhang /*define for linear_slice_pitch field*/ 1434*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 1435*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1436*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1437*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1438*5e779b17SHawking Zhang 1439*5e779b17SHawking Zhang /*define for COUNT word*/ 1440*5e779b17SHawking Zhang /*define for count field*/ 1441*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 1442*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x3FFFFFFF 1443*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 1444*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 1445*5e779b17SHawking Zhang 1446*5e779b17SHawking Zhang 1447*5e779b17SHawking Zhang /* 1448*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED_BC packet 1449*5e779b17SHawking Zhang */ 1450*5e779b17SHawking Zhang 1451*5e779b17SHawking Zhang /*define for HEADER word*/ 1452*5e779b17SHawking Zhang /*define for op field*/ 1453*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 1454*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF 1455*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 1456*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) 1457*5e779b17SHawking Zhang 1458*5e779b17SHawking Zhang /*define for sub_op field*/ 1459*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 1460*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF 1461*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 1462*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) 1463*5e779b17SHawking Zhang 1464*5e779b17SHawking Zhang /*define for detile field*/ 1465*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 1466*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 1467*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 1468*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) 1469*5e779b17SHawking Zhang 1470*5e779b17SHawking Zhang /*define for TILED_ADDR_LO word*/ 1471*5e779b17SHawking Zhang /*define for tiled_addr_31_0 field*/ 1472*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1473*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1474*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1475*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 1476*5e779b17SHawking Zhang 1477*5e779b17SHawking Zhang /*define for TILED_ADDR_HI word*/ 1478*5e779b17SHawking Zhang /*define for tiled_addr_63_32 field*/ 1479*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1480*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1481*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1482*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 1483*5e779b17SHawking Zhang 1484*5e779b17SHawking Zhang /*define for DW_3 word*/ 1485*5e779b17SHawking Zhang /*define for width field*/ 1486*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 1487*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF 1488*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 1489*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) 1490*5e779b17SHawking Zhang 1491*5e779b17SHawking Zhang /*define for DW_4 word*/ 1492*5e779b17SHawking Zhang /*define for height field*/ 1493*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 1494*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF 1495*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 1496*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) 1497*5e779b17SHawking Zhang 1498*5e779b17SHawking Zhang /*define for depth field*/ 1499*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 1500*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF 1501*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 1502*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) 1503*5e779b17SHawking Zhang 1504*5e779b17SHawking Zhang /*define for DW_5 word*/ 1505*5e779b17SHawking Zhang /*define for element_size field*/ 1506*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 1507*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 1508*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 1509*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) 1510*5e779b17SHawking Zhang 1511*5e779b17SHawking Zhang /*define for array_mode field*/ 1512*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 1513*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F 1514*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 1515*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) 1516*5e779b17SHawking Zhang 1517*5e779b17SHawking Zhang /*define for mit_mode field*/ 1518*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 1519*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 1520*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 1521*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) 1522*5e779b17SHawking Zhang 1523*5e779b17SHawking Zhang /*define for tilesplit_size field*/ 1524*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 1525*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 1526*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 1527*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) 1528*5e779b17SHawking Zhang 1529*5e779b17SHawking Zhang /*define for bank_w field*/ 1530*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 1531*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 1532*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 1533*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) 1534*5e779b17SHawking Zhang 1535*5e779b17SHawking Zhang /*define for bank_h field*/ 1536*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 1537*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 1538*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 1539*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) 1540*5e779b17SHawking Zhang 1541*5e779b17SHawking Zhang /*define for num_bank field*/ 1542*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 1543*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 1544*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 1545*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) 1546*5e779b17SHawking Zhang 1547*5e779b17SHawking Zhang /*define for mat_aspt field*/ 1548*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 1549*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 1550*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 1551*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) 1552*5e779b17SHawking Zhang 1553*5e779b17SHawking Zhang /*define for pipe_config field*/ 1554*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 1555*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F 1556*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 1557*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) 1558*5e779b17SHawking Zhang 1559*5e779b17SHawking Zhang /*define for DW_6 word*/ 1560*5e779b17SHawking Zhang /*define for x field*/ 1561*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 1562*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF 1563*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 1564*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) 1565*5e779b17SHawking Zhang 1566*5e779b17SHawking Zhang /*define for y field*/ 1567*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 1568*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF 1569*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 1570*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) 1571*5e779b17SHawking Zhang 1572*5e779b17SHawking Zhang /*define for DW_7 word*/ 1573*5e779b17SHawking Zhang /*define for z field*/ 1574*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 1575*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF 1576*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 1577*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) 1578*5e779b17SHawking Zhang 1579*5e779b17SHawking Zhang /*define for linear_sw field*/ 1580*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 1581*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 1582*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 1583*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) 1584*5e779b17SHawking Zhang 1585*5e779b17SHawking Zhang /*define for tile_sw field*/ 1586*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 1587*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 1588*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 1589*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) 1590*5e779b17SHawking Zhang 1591*5e779b17SHawking Zhang /*define for LINEAR_ADDR_LO word*/ 1592*5e779b17SHawking Zhang /*define for linear_addr_31_0 field*/ 1593*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1594*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1595*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1596*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1597*5e779b17SHawking Zhang 1598*5e779b17SHawking Zhang /*define for LINEAR_ADDR_HI word*/ 1599*5e779b17SHawking Zhang /*define for linear_addr_63_32 field*/ 1600*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1601*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1602*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1603*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1604*5e779b17SHawking Zhang 1605*5e779b17SHawking Zhang /*define for LINEAR_PITCH word*/ 1606*5e779b17SHawking Zhang /*define for linear_pitch field*/ 1607*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 1608*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1609*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 1610*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) 1611*5e779b17SHawking Zhang 1612*5e779b17SHawking Zhang /*define for LINEAR_SLICE_PITCH word*/ 1613*5e779b17SHawking Zhang /*define for linear_slice_pitch field*/ 1614*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 1615*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1616*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1617*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1618*5e779b17SHawking Zhang 1619*5e779b17SHawking Zhang /*define for COUNT word*/ 1620*5e779b17SHawking Zhang /*define for count field*/ 1621*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 12 1622*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF 1623*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 1624*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) 1625*5e779b17SHawking Zhang 1626*5e779b17SHawking Zhang 1627*5e779b17SHawking Zhang /* 1628*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 1629*5e779b17SHawking Zhang */ 1630*5e779b17SHawking Zhang 1631*5e779b17SHawking Zhang /*define for HEADER word*/ 1632*5e779b17SHawking Zhang /*define for op field*/ 1633*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 1634*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 1635*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 1636*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 1637*5e779b17SHawking Zhang 1638*5e779b17SHawking Zhang /*define for sub_op field*/ 1639*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 1640*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 1641*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 1642*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 1643*5e779b17SHawking Zhang 1644*5e779b17SHawking Zhang /*define for encrypt field*/ 1645*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 1646*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 1647*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 1648*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 1649*5e779b17SHawking Zhang 1650*5e779b17SHawking Zhang /*define for tmz field*/ 1651*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 1652*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 1653*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 1654*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 1655*5e779b17SHawking Zhang 1656*5e779b17SHawking Zhang /*define for cpv field*/ 1657*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset 0 1658*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask 0x00000001 1659*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift 19 1660*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift) 1661*5e779b17SHawking Zhang 1662*5e779b17SHawking Zhang /*define for videocopy field*/ 1663*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 1664*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 1665*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 1666*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 1667*5e779b17SHawking Zhang 1668*5e779b17SHawking Zhang /*define for broadcast field*/ 1669*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 1670*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 1671*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 1672*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 1673*5e779b17SHawking Zhang 1674*5e779b17SHawking Zhang /*define for TILED_ADDR_LO_0 word*/ 1675*5e779b17SHawking Zhang /*define for tiled_addr0_31_0 field*/ 1676*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 1677*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 1678*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 1679*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 1680*5e779b17SHawking Zhang 1681*5e779b17SHawking Zhang /*define for TILED_ADDR_HI_0 word*/ 1682*5e779b17SHawking Zhang /*define for tiled_addr0_63_32 field*/ 1683*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 1684*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 1685*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 1686*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 1687*5e779b17SHawking Zhang 1688*5e779b17SHawking Zhang /*define for TILED_ADDR_LO_1 word*/ 1689*5e779b17SHawking Zhang /*define for tiled_addr1_31_0 field*/ 1690*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 1691*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 1692*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 1693*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 1694*5e779b17SHawking Zhang 1695*5e779b17SHawking Zhang /*define for TILED_ADDR_HI_1 word*/ 1696*5e779b17SHawking Zhang /*define for tiled_addr1_63_32 field*/ 1697*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 1698*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 1699*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 1700*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 1701*5e779b17SHawking Zhang 1702*5e779b17SHawking Zhang /*define for DW_5 word*/ 1703*5e779b17SHawking Zhang /*define for width field*/ 1704*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 1705*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 1706*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 1707*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 1708*5e779b17SHawking Zhang 1709*5e779b17SHawking Zhang /*define for DW_6 word*/ 1710*5e779b17SHawking Zhang /*define for height field*/ 1711*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 1712*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 1713*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 1714*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 1715*5e779b17SHawking Zhang 1716*5e779b17SHawking Zhang /*define for depth field*/ 1717*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 1718*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF 1719*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 1720*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 1721*5e779b17SHawking Zhang 1722*5e779b17SHawking Zhang /*define for DW_7 word*/ 1723*5e779b17SHawking Zhang /*define for element_size field*/ 1724*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 1725*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 1726*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 1727*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 1728*5e779b17SHawking Zhang 1729*5e779b17SHawking Zhang /*define for swizzle_mode field*/ 1730*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 1731*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 1732*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 1733*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 1734*5e779b17SHawking Zhang 1735*5e779b17SHawking Zhang /*define for dimension field*/ 1736*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 1737*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 1738*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 1739*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 1740*5e779b17SHawking Zhang 1741*5e779b17SHawking Zhang /*define for mip_max field*/ 1742*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 1743*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F 1744*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 1745*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) 1746*5e779b17SHawking Zhang 1747*5e779b17SHawking Zhang /*define for DW_8 word*/ 1748*5e779b17SHawking Zhang /*define for x field*/ 1749*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 1750*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 1751*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 1752*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 1753*5e779b17SHawking Zhang 1754*5e779b17SHawking Zhang /*define for y field*/ 1755*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 1756*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 1757*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 1758*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 1759*5e779b17SHawking Zhang 1760*5e779b17SHawking Zhang /*define for DW_9 word*/ 1761*5e779b17SHawking Zhang /*define for z field*/ 1762*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 1763*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF 1764*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 1765*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 1766*5e779b17SHawking Zhang 1767*5e779b17SHawking Zhang /*define for DW_10 word*/ 1768*5e779b17SHawking Zhang /*define for dst2_sw field*/ 1769*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 1770*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 1771*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 1772*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 1773*5e779b17SHawking Zhang 1774*5e779b17SHawking Zhang /*define for dst2_cache_policy field*/ 1775*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset 10 1776*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask 0x00000007 1777*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift 10 1778*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift) 1779*5e779b17SHawking Zhang 1780*5e779b17SHawking Zhang /*define for linear_sw field*/ 1781*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 1782*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 1783*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 1784*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 1785*5e779b17SHawking Zhang 1786*5e779b17SHawking Zhang /*define for linear_cache_policy field*/ 1787*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset 10 1788*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask 0x00000007 1789*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift 18 1790*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift) 1791*5e779b17SHawking Zhang 1792*5e779b17SHawking Zhang /*define for tile_sw field*/ 1793*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 1794*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 1795*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 1796*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 1797*5e779b17SHawking Zhang 1798*5e779b17SHawking Zhang /*define for tile_cache_policy field*/ 1799*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset 10 1800*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask 0x00000007 1801*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift 26 1802*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift) 1803*5e779b17SHawking Zhang 1804*5e779b17SHawking Zhang /*define for LINEAR_ADDR_LO word*/ 1805*5e779b17SHawking Zhang /*define for linear_addr_31_0 field*/ 1806*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 1807*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1808*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1809*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1810*5e779b17SHawking Zhang 1811*5e779b17SHawking Zhang /*define for LINEAR_ADDR_HI word*/ 1812*5e779b17SHawking Zhang /*define for linear_addr_63_32 field*/ 1813*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 1814*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1815*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1816*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1817*5e779b17SHawking Zhang 1818*5e779b17SHawking Zhang /*define for LINEAR_PITCH word*/ 1819*5e779b17SHawking Zhang /*define for linear_pitch field*/ 1820*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 1821*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1822*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 1823*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 1824*5e779b17SHawking Zhang 1825*5e779b17SHawking Zhang /*define for LINEAR_SLICE_PITCH word*/ 1826*5e779b17SHawking Zhang /*define for linear_slice_pitch field*/ 1827*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 1828*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1829*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1830*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1831*5e779b17SHawking Zhang 1832*5e779b17SHawking Zhang /*define for COUNT word*/ 1833*5e779b17SHawking Zhang /*define for count field*/ 1834*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 1835*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x3FFFFFFF 1836*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 1837*5e779b17SHawking Zhang #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 1838*5e779b17SHawking Zhang 1839*5e779b17SHawking Zhang 1840*5e779b17SHawking Zhang /* 1841*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_T2T packet 1842*5e779b17SHawking Zhang */ 1843*5e779b17SHawking Zhang 1844*5e779b17SHawking Zhang /*define for HEADER word*/ 1845*5e779b17SHawking Zhang /*define for op field*/ 1846*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 1847*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 1848*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 1849*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 1850*5e779b17SHawking Zhang 1851*5e779b17SHawking Zhang /*define for sub_op field*/ 1852*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 1853*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 1854*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 1855*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 1856*5e779b17SHawking Zhang 1857*5e779b17SHawking Zhang /*define for tmz field*/ 1858*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 1859*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 1860*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 1861*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 1862*5e779b17SHawking Zhang 1863*5e779b17SHawking Zhang /*define for dcc field*/ 1864*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 1865*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 1866*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 1867*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) 1868*5e779b17SHawking Zhang 1869*5e779b17SHawking Zhang /*define for cpv field*/ 1870*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_cpv_offset 0 1871*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_cpv_mask 0x00000001 1872*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_cpv_shift 28 1873*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_cpv_mask) << SDMA_PKT_COPY_T2T_HEADER_cpv_shift) 1874*5e779b17SHawking Zhang 1875*5e779b17SHawking Zhang /*define for dcc_dir field*/ 1876*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 1877*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 1878*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 1879*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) 1880*5e779b17SHawking Zhang 1881*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 1882*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 1883*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 1884*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1885*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 1886*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 1887*5e779b17SHawking Zhang 1888*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 1889*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 1890*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 1891*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1892*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 1893*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 1894*5e779b17SHawking Zhang 1895*5e779b17SHawking Zhang /*define for DW_3 word*/ 1896*5e779b17SHawking Zhang /*define for src_x field*/ 1897*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 1898*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 1899*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 1900*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 1901*5e779b17SHawking Zhang 1902*5e779b17SHawking Zhang /*define for src_y field*/ 1903*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 1904*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 1905*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 1906*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 1907*5e779b17SHawking Zhang 1908*5e779b17SHawking Zhang /*define for DW_4 word*/ 1909*5e779b17SHawking Zhang /*define for src_z field*/ 1910*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 1911*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF 1912*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 1913*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 1914*5e779b17SHawking Zhang 1915*5e779b17SHawking Zhang /*define for src_width field*/ 1916*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 1917*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 1918*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 1919*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 1920*5e779b17SHawking Zhang 1921*5e779b17SHawking Zhang /*define for DW_5 word*/ 1922*5e779b17SHawking Zhang /*define for src_height field*/ 1923*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 1924*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 1925*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 1926*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 1927*5e779b17SHawking Zhang 1928*5e779b17SHawking Zhang /*define for src_depth field*/ 1929*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 1930*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF 1931*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 1932*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 1933*5e779b17SHawking Zhang 1934*5e779b17SHawking Zhang /*define for DW_6 word*/ 1935*5e779b17SHawking Zhang /*define for src_element_size field*/ 1936*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 1937*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 1938*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 1939*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 1940*5e779b17SHawking Zhang 1941*5e779b17SHawking Zhang /*define for src_swizzle_mode field*/ 1942*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 1943*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 1944*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 1945*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 1946*5e779b17SHawking Zhang 1947*5e779b17SHawking Zhang /*define for src_dimension field*/ 1948*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 1949*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 1950*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 1951*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 1952*5e779b17SHawking Zhang 1953*5e779b17SHawking Zhang /*define for src_mip_max field*/ 1954*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 1955*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F 1956*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 1957*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) 1958*5e779b17SHawking Zhang 1959*5e779b17SHawking Zhang /*define for src_mip_id field*/ 1960*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 1961*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F 1962*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 1963*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) 1964*5e779b17SHawking Zhang 1965*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 1966*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 1967*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 1968*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1969*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 1970*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 1971*5e779b17SHawking Zhang 1972*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 1973*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 1974*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 1975*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1976*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 1977*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 1978*5e779b17SHawking Zhang 1979*5e779b17SHawking Zhang /*define for DW_9 word*/ 1980*5e779b17SHawking Zhang /*define for dst_x field*/ 1981*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 1982*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 1983*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 1984*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 1985*5e779b17SHawking Zhang 1986*5e779b17SHawking Zhang /*define for dst_y field*/ 1987*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 1988*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 1989*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 1990*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 1991*5e779b17SHawking Zhang 1992*5e779b17SHawking Zhang /*define for DW_10 word*/ 1993*5e779b17SHawking Zhang /*define for dst_z field*/ 1994*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 1995*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF 1996*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 1997*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 1998*5e779b17SHawking Zhang 1999*5e779b17SHawking Zhang /*define for dst_width field*/ 2000*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 2001*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 2002*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 2003*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 2004*5e779b17SHawking Zhang 2005*5e779b17SHawking Zhang /*define for DW_11 word*/ 2006*5e779b17SHawking Zhang /*define for dst_height field*/ 2007*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 2008*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 2009*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 2010*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 2011*5e779b17SHawking Zhang 2012*5e779b17SHawking Zhang /*define for dst_depth field*/ 2013*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 2014*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF 2015*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 2016*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 2017*5e779b17SHawking Zhang 2018*5e779b17SHawking Zhang /*define for DW_12 word*/ 2019*5e779b17SHawking Zhang /*define for dst_element_size field*/ 2020*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 2021*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 2022*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 2023*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 2024*5e779b17SHawking Zhang 2025*5e779b17SHawking Zhang /*define for dst_swizzle_mode field*/ 2026*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 2027*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 2028*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 2029*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 2030*5e779b17SHawking Zhang 2031*5e779b17SHawking Zhang /*define for dst_dimension field*/ 2032*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 2033*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 2034*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 2035*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 2036*5e779b17SHawking Zhang 2037*5e779b17SHawking Zhang /*define for dst_mip_max field*/ 2038*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 2039*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F 2040*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 2041*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) 2042*5e779b17SHawking Zhang 2043*5e779b17SHawking Zhang /*define for dst_mip_id field*/ 2044*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 2045*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F 2046*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 2047*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) 2048*5e779b17SHawking Zhang 2049*5e779b17SHawking Zhang /*define for DW_13 word*/ 2050*5e779b17SHawking Zhang /*define for rect_x field*/ 2051*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 2052*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 2053*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 2054*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 2055*5e779b17SHawking Zhang 2056*5e779b17SHawking Zhang /*define for rect_y field*/ 2057*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 2058*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 2059*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 2060*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 2061*5e779b17SHawking Zhang 2062*5e779b17SHawking Zhang /*define for DW_14 word*/ 2063*5e779b17SHawking Zhang /*define for rect_z field*/ 2064*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 2065*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF 2066*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 2067*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 2068*5e779b17SHawking Zhang 2069*5e779b17SHawking Zhang /*define for dst_sw field*/ 2070*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 2071*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 2072*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 2073*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 2074*5e779b17SHawking Zhang 2075*5e779b17SHawking Zhang /*define for dst_cache_policy field*/ 2076*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset 14 2077*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask 0x00000007 2078*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift 18 2079*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift) 2080*5e779b17SHawking Zhang 2081*5e779b17SHawking Zhang /*define for src_sw field*/ 2082*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 2083*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 2084*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 2085*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 2086*5e779b17SHawking Zhang 2087*5e779b17SHawking Zhang /*define for src_cache_policy field*/ 2088*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset 14 2089*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask 0x00000007 2090*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift 26 2091*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift) 2092*5e779b17SHawking Zhang 2093*5e779b17SHawking Zhang /*define for META_ADDR_LO word*/ 2094*5e779b17SHawking Zhang /*define for meta_addr_31_0 field*/ 2095*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 2096*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 2097*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 2098*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) 2099*5e779b17SHawking Zhang 2100*5e779b17SHawking Zhang /*define for META_ADDR_HI word*/ 2101*5e779b17SHawking Zhang /*define for meta_addr_63_32 field*/ 2102*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 2103*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 2104*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 2105*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) 2106*5e779b17SHawking Zhang 2107*5e779b17SHawking Zhang /*define for META_CONFIG word*/ 2108*5e779b17SHawking Zhang /*define for data_format field*/ 2109*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 2110*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F 2111*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 2112*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) 2113*5e779b17SHawking Zhang 2114*5e779b17SHawking Zhang /*define for color_transform_disable field*/ 2115*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 2116*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 2117*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 2118*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) 2119*5e779b17SHawking Zhang 2120*5e779b17SHawking Zhang /*define for alpha_is_on_msb field*/ 2121*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 2122*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 2123*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 2124*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) 2125*5e779b17SHawking Zhang 2126*5e779b17SHawking Zhang /*define for number_type field*/ 2127*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 2128*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 2129*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 2130*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) 2131*5e779b17SHawking Zhang 2132*5e779b17SHawking Zhang /*define for surface_type field*/ 2133*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 2134*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 2135*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 2136*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) 2137*5e779b17SHawking Zhang 2138*5e779b17SHawking Zhang /*define for meta_llc field*/ 2139*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset 17 2140*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask 0x00000001 2141*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift 14 2142*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift) 2143*5e779b17SHawking Zhang 2144*5e779b17SHawking Zhang /*define for max_comp_block_size field*/ 2145*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 2146*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 2147*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 2148*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) 2149*5e779b17SHawking Zhang 2150*5e779b17SHawking Zhang /*define for max_uncomp_block_size field*/ 2151*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 2152*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 2153*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 2154*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) 2155*5e779b17SHawking Zhang 2156*5e779b17SHawking Zhang /*define for write_compress_enable field*/ 2157*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 2158*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 2159*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 2160*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) 2161*5e779b17SHawking Zhang 2162*5e779b17SHawking Zhang /*define for meta_tmz field*/ 2163*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 2164*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 2165*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 2166*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) 2167*5e779b17SHawking Zhang 2168*5e779b17SHawking Zhang /*define for pipe_aligned field*/ 2169*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset 17 2170*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask 0x00000001 2171*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift 31 2172*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift) 2173*5e779b17SHawking Zhang 2174*5e779b17SHawking Zhang 2175*5e779b17SHawking Zhang /* 2176*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_T2T_BC packet 2177*5e779b17SHawking Zhang */ 2178*5e779b17SHawking Zhang 2179*5e779b17SHawking Zhang /*define for HEADER word*/ 2180*5e779b17SHawking Zhang /*define for op field*/ 2181*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 2182*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF 2183*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 2184*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) 2185*5e779b17SHawking Zhang 2186*5e779b17SHawking Zhang /*define for sub_op field*/ 2187*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 2188*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF 2189*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 2190*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) 2191*5e779b17SHawking Zhang 2192*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 2193*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 2194*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 2195*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 2196*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 2197*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) 2198*5e779b17SHawking Zhang 2199*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 2200*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 2201*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 2202*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 2203*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 2204*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) 2205*5e779b17SHawking Zhang 2206*5e779b17SHawking Zhang /*define for DW_3 word*/ 2207*5e779b17SHawking Zhang /*define for src_x field*/ 2208*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 2209*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF 2210*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 2211*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) 2212*5e779b17SHawking Zhang 2213*5e779b17SHawking Zhang /*define for src_y field*/ 2214*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 2215*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF 2216*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 2217*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) 2218*5e779b17SHawking Zhang 2219*5e779b17SHawking Zhang /*define for DW_4 word*/ 2220*5e779b17SHawking Zhang /*define for src_z field*/ 2221*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 2222*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF 2223*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 2224*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) 2225*5e779b17SHawking Zhang 2226*5e779b17SHawking Zhang /*define for src_width field*/ 2227*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 2228*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF 2229*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 2230*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) 2231*5e779b17SHawking Zhang 2232*5e779b17SHawking Zhang /*define for DW_5 word*/ 2233*5e779b17SHawking Zhang /*define for src_height field*/ 2234*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 2235*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF 2236*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 2237*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) 2238*5e779b17SHawking Zhang 2239*5e779b17SHawking Zhang /*define for src_depth field*/ 2240*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 2241*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF 2242*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 2243*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) 2244*5e779b17SHawking Zhang 2245*5e779b17SHawking Zhang /*define for DW_6 word*/ 2246*5e779b17SHawking Zhang /*define for src_element_size field*/ 2247*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 2248*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 2249*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 2250*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) 2251*5e779b17SHawking Zhang 2252*5e779b17SHawking Zhang /*define for src_array_mode field*/ 2253*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 2254*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F 2255*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 2256*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) 2257*5e779b17SHawking Zhang 2258*5e779b17SHawking Zhang /*define for src_mit_mode field*/ 2259*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 2260*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 2261*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 2262*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) 2263*5e779b17SHawking Zhang 2264*5e779b17SHawking Zhang /*define for src_tilesplit_size field*/ 2265*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 2266*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 2267*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 2268*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) 2269*5e779b17SHawking Zhang 2270*5e779b17SHawking Zhang /*define for src_bank_w field*/ 2271*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 2272*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 2273*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 2274*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) 2275*5e779b17SHawking Zhang 2276*5e779b17SHawking Zhang /*define for src_bank_h field*/ 2277*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 2278*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 2279*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 2280*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) 2281*5e779b17SHawking Zhang 2282*5e779b17SHawking Zhang /*define for src_num_bank field*/ 2283*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 2284*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 2285*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 2286*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) 2287*5e779b17SHawking Zhang 2288*5e779b17SHawking Zhang /*define for src_mat_aspt field*/ 2289*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 2290*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 2291*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 2292*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) 2293*5e779b17SHawking Zhang 2294*5e779b17SHawking Zhang /*define for src_pipe_config field*/ 2295*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 2296*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F 2297*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 2298*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) 2299*5e779b17SHawking Zhang 2300*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 2301*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 2302*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 2303*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2304*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 2305*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) 2306*5e779b17SHawking Zhang 2307*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 2308*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 2309*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 2310*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2311*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 2312*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) 2313*5e779b17SHawking Zhang 2314*5e779b17SHawking Zhang /*define for DW_9 word*/ 2315*5e779b17SHawking Zhang /*define for dst_x field*/ 2316*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 2317*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF 2318*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 2319*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) 2320*5e779b17SHawking Zhang 2321*5e779b17SHawking Zhang /*define for dst_y field*/ 2322*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 2323*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF 2324*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 2325*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) 2326*5e779b17SHawking Zhang 2327*5e779b17SHawking Zhang /*define for DW_10 word*/ 2328*5e779b17SHawking Zhang /*define for dst_z field*/ 2329*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 2330*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF 2331*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 2332*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) 2333*5e779b17SHawking Zhang 2334*5e779b17SHawking Zhang /*define for dst_width field*/ 2335*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 2336*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF 2337*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 2338*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) 2339*5e779b17SHawking Zhang 2340*5e779b17SHawking Zhang /*define for DW_11 word*/ 2341*5e779b17SHawking Zhang /*define for dst_height field*/ 2342*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 2343*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF 2344*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 2345*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) 2346*5e779b17SHawking Zhang 2347*5e779b17SHawking Zhang /*define for dst_depth field*/ 2348*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 2349*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF 2350*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 2351*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) 2352*5e779b17SHawking Zhang 2353*5e779b17SHawking Zhang /*define for DW_12 word*/ 2354*5e779b17SHawking Zhang /*define for dst_element_size field*/ 2355*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 2356*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 2357*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 2358*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) 2359*5e779b17SHawking Zhang 2360*5e779b17SHawking Zhang /*define for dst_array_mode field*/ 2361*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 2362*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F 2363*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 2364*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) 2365*5e779b17SHawking Zhang 2366*5e779b17SHawking Zhang /*define for dst_mit_mode field*/ 2367*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 2368*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 2369*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 2370*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) 2371*5e779b17SHawking Zhang 2372*5e779b17SHawking Zhang /*define for dst_tilesplit_size field*/ 2373*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 2374*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 2375*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 2376*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) 2377*5e779b17SHawking Zhang 2378*5e779b17SHawking Zhang /*define for dst_bank_w field*/ 2379*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 2380*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 2381*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 2382*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) 2383*5e779b17SHawking Zhang 2384*5e779b17SHawking Zhang /*define for dst_bank_h field*/ 2385*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 2386*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 2387*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 2388*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) 2389*5e779b17SHawking Zhang 2390*5e779b17SHawking Zhang /*define for dst_num_bank field*/ 2391*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 2392*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 2393*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 2394*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) 2395*5e779b17SHawking Zhang 2396*5e779b17SHawking Zhang /*define for dst_mat_aspt field*/ 2397*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 2398*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 2399*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 2400*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) 2401*5e779b17SHawking Zhang 2402*5e779b17SHawking Zhang /*define for dst_pipe_config field*/ 2403*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 2404*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F 2405*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 2406*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) 2407*5e779b17SHawking Zhang 2408*5e779b17SHawking Zhang /*define for DW_13 word*/ 2409*5e779b17SHawking Zhang /*define for rect_x field*/ 2410*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 2411*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF 2412*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 2413*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) 2414*5e779b17SHawking Zhang 2415*5e779b17SHawking Zhang /*define for rect_y field*/ 2416*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 2417*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF 2418*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 2419*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) 2420*5e779b17SHawking Zhang 2421*5e779b17SHawking Zhang /*define for DW_14 word*/ 2422*5e779b17SHawking Zhang /*define for rect_z field*/ 2423*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 2424*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF 2425*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 2426*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) 2427*5e779b17SHawking Zhang 2428*5e779b17SHawking Zhang /*define for dst_sw field*/ 2429*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 2430*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 2431*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 2432*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) 2433*5e779b17SHawking Zhang 2434*5e779b17SHawking Zhang /*define for src_sw field*/ 2435*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 2436*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 2437*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 2438*5e779b17SHawking Zhang #define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) 2439*5e779b17SHawking Zhang 2440*5e779b17SHawking Zhang 2441*5e779b17SHawking Zhang /* 2442*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 2443*5e779b17SHawking Zhang */ 2444*5e779b17SHawking Zhang 2445*5e779b17SHawking Zhang /*define for HEADER word*/ 2446*5e779b17SHawking Zhang /*define for op field*/ 2447*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 2448*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 2449*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 2450*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 2451*5e779b17SHawking Zhang 2452*5e779b17SHawking Zhang /*define for sub_op field*/ 2453*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 2454*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 2455*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 2456*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 2457*5e779b17SHawking Zhang 2458*5e779b17SHawking Zhang /*define for tmz field*/ 2459*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 2460*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 2461*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 2462*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 2463*5e779b17SHawking Zhang 2464*5e779b17SHawking Zhang /*define for dcc field*/ 2465*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 2466*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 2467*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 2468*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) 2469*5e779b17SHawking Zhang 2470*5e779b17SHawking Zhang /*define for cpv field*/ 2471*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset 0 2472*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask 0x00000001 2473*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift 28 2474*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift) 2475*5e779b17SHawking Zhang 2476*5e779b17SHawking Zhang /*define for detile field*/ 2477*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 2478*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 2479*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 2480*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 2481*5e779b17SHawking Zhang 2482*5e779b17SHawking Zhang /*define for TILED_ADDR_LO word*/ 2483*5e779b17SHawking Zhang /*define for tiled_addr_31_0 field*/ 2484*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2485*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2486*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2487*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 2488*5e779b17SHawking Zhang 2489*5e779b17SHawking Zhang /*define for TILED_ADDR_HI word*/ 2490*5e779b17SHawking Zhang /*define for tiled_addr_63_32 field*/ 2491*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2492*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2493*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2494*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 2495*5e779b17SHawking Zhang 2496*5e779b17SHawking Zhang /*define for DW_3 word*/ 2497*5e779b17SHawking Zhang /*define for tiled_x field*/ 2498*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 2499*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 2500*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 2501*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 2502*5e779b17SHawking Zhang 2503*5e779b17SHawking Zhang /*define for tiled_y field*/ 2504*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 2505*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 2506*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 2507*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 2508*5e779b17SHawking Zhang 2509*5e779b17SHawking Zhang /*define for DW_4 word*/ 2510*5e779b17SHawking Zhang /*define for tiled_z field*/ 2511*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 2512*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF 2513*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 2514*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 2515*5e779b17SHawking Zhang 2516*5e779b17SHawking Zhang /*define for width field*/ 2517*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 2518*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 2519*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 2520*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 2521*5e779b17SHawking Zhang 2522*5e779b17SHawking Zhang /*define for DW_5 word*/ 2523*5e779b17SHawking Zhang /*define for height field*/ 2524*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 2525*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 2526*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 2527*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 2528*5e779b17SHawking Zhang 2529*5e779b17SHawking Zhang /*define for depth field*/ 2530*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 2531*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF 2532*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 2533*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 2534*5e779b17SHawking Zhang 2535*5e779b17SHawking Zhang /*define for DW_6 word*/ 2536*5e779b17SHawking Zhang /*define for element_size field*/ 2537*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 2538*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 2539*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 2540*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 2541*5e779b17SHawking Zhang 2542*5e779b17SHawking Zhang /*define for swizzle_mode field*/ 2543*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 2544*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 2545*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 2546*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 2547*5e779b17SHawking Zhang 2548*5e779b17SHawking Zhang /*define for dimension field*/ 2549*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 2550*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 2551*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 2552*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 2553*5e779b17SHawking Zhang 2554*5e779b17SHawking Zhang /*define for mip_max field*/ 2555*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 2556*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F 2557*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 2558*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) 2559*5e779b17SHawking Zhang 2560*5e779b17SHawking Zhang /*define for mip_id field*/ 2561*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 2562*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F 2563*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 2564*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) 2565*5e779b17SHawking Zhang 2566*5e779b17SHawking Zhang /*define for LINEAR_ADDR_LO word*/ 2567*5e779b17SHawking Zhang /*define for linear_addr_31_0 field*/ 2568*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2569*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2570*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2571*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2572*5e779b17SHawking Zhang 2573*5e779b17SHawking Zhang /*define for LINEAR_ADDR_HI word*/ 2574*5e779b17SHawking Zhang /*define for linear_addr_63_32 field*/ 2575*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2576*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2577*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2578*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2579*5e779b17SHawking Zhang 2580*5e779b17SHawking Zhang /*define for DW_9 word*/ 2581*5e779b17SHawking Zhang /*define for linear_x field*/ 2582*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 2583*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 2584*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 2585*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 2586*5e779b17SHawking Zhang 2587*5e779b17SHawking Zhang /*define for linear_y field*/ 2588*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 2589*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 2590*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 2591*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 2592*5e779b17SHawking Zhang 2593*5e779b17SHawking Zhang /*define for DW_10 word*/ 2594*5e779b17SHawking Zhang /*define for linear_z field*/ 2595*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 2596*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF 2597*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 2598*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 2599*5e779b17SHawking Zhang 2600*5e779b17SHawking Zhang /*define for linear_pitch field*/ 2601*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 2602*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 2603*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 2604*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 2605*5e779b17SHawking Zhang 2606*5e779b17SHawking Zhang /*define for DW_11 word*/ 2607*5e779b17SHawking Zhang /*define for linear_slice_pitch field*/ 2608*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 2609*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2610*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 2611*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 2612*5e779b17SHawking Zhang 2613*5e779b17SHawking Zhang /*define for DW_12 word*/ 2614*5e779b17SHawking Zhang /*define for rect_x field*/ 2615*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 2616*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 2617*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 2618*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 2619*5e779b17SHawking Zhang 2620*5e779b17SHawking Zhang /*define for rect_y field*/ 2621*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 2622*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 2623*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 2624*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 2625*5e779b17SHawking Zhang 2626*5e779b17SHawking Zhang /*define for DW_13 word*/ 2627*5e779b17SHawking Zhang /*define for rect_z field*/ 2628*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 2629*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF 2630*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 2631*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 2632*5e779b17SHawking Zhang 2633*5e779b17SHawking Zhang /*define for linear_sw field*/ 2634*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 2635*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 2636*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 2637*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 2638*5e779b17SHawking Zhang 2639*5e779b17SHawking Zhang /*define for linear_cache_policy field*/ 2640*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset 13 2641*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask 0x00000007 2642*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift 18 2643*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift) 2644*5e779b17SHawking Zhang 2645*5e779b17SHawking Zhang /*define for tile_sw field*/ 2646*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 2647*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 2648*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 2649*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 2650*5e779b17SHawking Zhang 2651*5e779b17SHawking Zhang /*define for tile_cache_policy field*/ 2652*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset 13 2653*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask 0x00000007 2654*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift 26 2655*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift) 2656*5e779b17SHawking Zhang 2657*5e779b17SHawking Zhang /*define for META_ADDR_LO word*/ 2658*5e779b17SHawking Zhang /*define for meta_addr_31_0 field*/ 2659*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 2660*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 2661*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 2662*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) 2663*5e779b17SHawking Zhang 2664*5e779b17SHawking Zhang /*define for META_ADDR_HI word*/ 2665*5e779b17SHawking Zhang /*define for meta_addr_63_32 field*/ 2666*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 2667*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 2668*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 2669*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) 2670*5e779b17SHawking Zhang 2671*5e779b17SHawking Zhang /*define for META_CONFIG word*/ 2672*5e779b17SHawking Zhang /*define for data_format field*/ 2673*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 2674*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F 2675*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 2676*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) 2677*5e779b17SHawking Zhang 2678*5e779b17SHawking Zhang /*define for color_transform_disable field*/ 2679*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 2680*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 2681*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 2682*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) 2683*5e779b17SHawking Zhang 2684*5e779b17SHawking Zhang /*define for alpha_is_on_msb field*/ 2685*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 2686*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 2687*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 2688*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) 2689*5e779b17SHawking Zhang 2690*5e779b17SHawking Zhang /*define for number_type field*/ 2691*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 2692*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 2693*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 2694*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) 2695*5e779b17SHawking Zhang 2696*5e779b17SHawking Zhang /*define for surface_type field*/ 2697*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 2698*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 2699*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 2700*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) 2701*5e779b17SHawking Zhang 2702*5e779b17SHawking Zhang /*define for meta_llc field*/ 2703*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset 16 2704*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask 0x00000001 2705*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift 14 2706*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift) 2707*5e779b17SHawking Zhang 2708*5e779b17SHawking Zhang /*define for max_comp_block_size field*/ 2709*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 2710*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 2711*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 2712*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) 2713*5e779b17SHawking Zhang 2714*5e779b17SHawking Zhang /*define for max_uncomp_block_size field*/ 2715*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 2716*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 2717*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 2718*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) 2719*5e779b17SHawking Zhang 2720*5e779b17SHawking Zhang /*define for write_compress_enable field*/ 2721*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 2722*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 2723*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 2724*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) 2725*5e779b17SHawking Zhang 2726*5e779b17SHawking Zhang /*define for meta_tmz field*/ 2727*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 2728*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 2729*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 2730*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) 2731*5e779b17SHawking Zhang 2732*5e779b17SHawking Zhang /*define for pipe_aligned field*/ 2733*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset 16 2734*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask 0x00000001 2735*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift 31 2736*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift) 2737*5e779b17SHawking Zhang 2738*5e779b17SHawking Zhang 2739*5e779b17SHawking Zhang /* 2740*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet 2741*5e779b17SHawking Zhang */ 2742*5e779b17SHawking Zhang 2743*5e779b17SHawking Zhang /*define for HEADER word*/ 2744*5e779b17SHawking Zhang /*define for op field*/ 2745*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 2746*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF 2747*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 2748*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) 2749*5e779b17SHawking Zhang 2750*5e779b17SHawking Zhang /*define for sub_op field*/ 2751*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 2752*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 2753*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 2754*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) 2755*5e779b17SHawking Zhang 2756*5e779b17SHawking Zhang /*define for detile field*/ 2757*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 2758*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 2759*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 2760*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) 2761*5e779b17SHawking Zhang 2762*5e779b17SHawking Zhang /*define for TILED_ADDR_LO word*/ 2763*5e779b17SHawking Zhang /*define for tiled_addr_31_0 field*/ 2764*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2765*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2766*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2767*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 2768*5e779b17SHawking Zhang 2769*5e779b17SHawking Zhang /*define for TILED_ADDR_HI word*/ 2770*5e779b17SHawking Zhang /*define for tiled_addr_63_32 field*/ 2771*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2772*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2773*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2774*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 2775*5e779b17SHawking Zhang 2776*5e779b17SHawking Zhang /*define for DW_3 word*/ 2777*5e779b17SHawking Zhang /*define for tiled_x field*/ 2778*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 2779*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF 2780*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 2781*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) 2782*5e779b17SHawking Zhang 2783*5e779b17SHawking Zhang /*define for tiled_y field*/ 2784*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 2785*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF 2786*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 2787*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) 2788*5e779b17SHawking Zhang 2789*5e779b17SHawking Zhang /*define for DW_4 word*/ 2790*5e779b17SHawking Zhang /*define for tiled_z field*/ 2791*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 2792*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF 2793*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 2794*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) 2795*5e779b17SHawking Zhang 2796*5e779b17SHawking Zhang /*define for width field*/ 2797*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 2798*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF 2799*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 2800*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) 2801*5e779b17SHawking Zhang 2802*5e779b17SHawking Zhang /*define for DW_5 word*/ 2803*5e779b17SHawking Zhang /*define for height field*/ 2804*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 2805*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF 2806*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 2807*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) 2808*5e779b17SHawking Zhang 2809*5e779b17SHawking Zhang /*define for depth field*/ 2810*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 2811*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF 2812*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 2813*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) 2814*5e779b17SHawking Zhang 2815*5e779b17SHawking Zhang /*define for DW_6 word*/ 2816*5e779b17SHawking Zhang /*define for element_size field*/ 2817*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 2818*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 2819*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 2820*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) 2821*5e779b17SHawking Zhang 2822*5e779b17SHawking Zhang /*define for array_mode field*/ 2823*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 2824*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F 2825*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 2826*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) 2827*5e779b17SHawking Zhang 2828*5e779b17SHawking Zhang /*define for mit_mode field*/ 2829*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 2830*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 2831*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 2832*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) 2833*5e779b17SHawking Zhang 2834*5e779b17SHawking Zhang /*define for tilesplit_size field*/ 2835*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 2836*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 2837*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 2838*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) 2839*5e779b17SHawking Zhang 2840*5e779b17SHawking Zhang /*define for bank_w field*/ 2841*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 2842*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 2843*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 2844*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) 2845*5e779b17SHawking Zhang 2846*5e779b17SHawking Zhang /*define for bank_h field*/ 2847*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 2848*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 2849*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 2850*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) 2851*5e779b17SHawking Zhang 2852*5e779b17SHawking Zhang /*define for num_bank field*/ 2853*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 2854*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 2855*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 2856*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) 2857*5e779b17SHawking Zhang 2858*5e779b17SHawking Zhang /*define for mat_aspt field*/ 2859*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 2860*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 2861*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 2862*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) 2863*5e779b17SHawking Zhang 2864*5e779b17SHawking Zhang /*define for pipe_config field*/ 2865*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 2866*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F 2867*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 2868*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) 2869*5e779b17SHawking Zhang 2870*5e779b17SHawking Zhang /*define for LINEAR_ADDR_LO word*/ 2871*5e779b17SHawking Zhang /*define for linear_addr_31_0 field*/ 2872*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2873*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2874*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2875*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2876*5e779b17SHawking Zhang 2877*5e779b17SHawking Zhang /*define for LINEAR_ADDR_HI word*/ 2878*5e779b17SHawking Zhang /*define for linear_addr_63_32 field*/ 2879*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2880*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2881*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2882*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2883*5e779b17SHawking Zhang 2884*5e779b17SHawking Zhang /*define for DW_9 word*/ 2885*5e779b17SHawking Zhang /*define for linear_x field*/ 2886*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 2887*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF 2888*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 2889*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) 2890*5e779b17SHawking Zhang 2891*5e779b17SHawking Zhang /*define for linear_y field*/ 2892*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 2893*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF 2894*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 2895*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) 2896*5e779b17SHawking Zhang 2897*5e779b17SHawking Zhang /*define for DW_10 word*/ 2898*5e779b17SHawking Zhang /*define for linear_z field*/ 2899*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 2900*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF 2901*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 2902*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) 2903*5e779b17SHawking Zhang 2904*5e779b17SHawking Zhang /*define for linear_pitch field*/ 2905*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 2906*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF 2907*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 2908*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) 2909*5e779b17SHawking Zhang 2910*5e779b17SHawking Zhang /*define for DW_11 word*/ 2911*5e779b17SHawking Zhang /*define for linear_slice_pitch field*/ 2912*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 2913*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2914*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 2915*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) 2916*5e779b17SHawking Zhang 2917*5e779b17SHawking Zhang /*define for DW_12 word*/ 2918*5e779b17SHawking Zhang /*define for rect_x field*/ 2919*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 2920*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF 2921*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 2922*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) 2923*5e779b17SHawking Zhang 2924*5e779b17SHawking Zhang /*define for rect_y field*/ 2925*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 2926*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF 2927*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 2928*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) 2929*5e779b17SHawking Zhang 2930*5e779b17SHawking Zhang /*define for DW_13 word*/ 2931*5e779b17SHawking Zhang /*define for rect_z field*/ 2932*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 2933*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF 2934*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 2935*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) 2936*5e779b17SHawking Zhang 2937*5e779b17SHawking Zhang /*define for linear_sw field*/ 2938*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 2939*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 2940*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 2941*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) 2942*5e779b17SHawking Zhang 2943*5e779b17SHawking Zhang /*define for tile_sw field*/ 2944*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 2945*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 2946*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 2947*5e779b17SHawking Zhang #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) 2948*5e779b17SHawking Zhang 2949*5e779b17SHawking Zhang 2950*5e779b17SHawking Zhang /* 2951*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COPY_STRUCT packet 2952*5e779b17SHawking Zhang */ 2953*5e779b17SHawking Zhang 2954*5e779b17SHawking Zhang /*define for HEADER word*/ 2955*5e779b17SHawking Zhang /*define for op field*/ 2956*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 2957*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 2958*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 2959*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 2960*5e779b17SHawking Zhang 2961*5e779b17SHawking Zhang /*define for sub_op field*/ 2962*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 2963*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 2964*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 2965*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 2966*5e779b17SHawking Zhang 2967*5e779b17SHawking Zhang /*define for tmz field*/ 2968*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 2969*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 2970*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 2971*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 2972*5e779b17SHawking Zhang 2973*5e779b17SHawking Zhang /*define for cpv field*/ 2974*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset 0 2975*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask 0x00000001 2976*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift 28 2977*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask) << SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift) 2978*5e779b17SHawking Zhang 2979*5e779b17SHawking Zhang /*define for detile field*/ 2980*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 2981*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 2982*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 2983*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 2984*5e779b17SHawking Zhang 2985*5e779b17SHawking Zhang /*define for SB_ADDR_LO word*/ 2986*5e779b17SHawking Zhang /*define for sb_addr_31_0 field*/ 2987*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 2988*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 2989*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 2990*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 2991*5e779b17SHawking Zhang 2992*5e779b17SHawking Zhang /*define for SB_ADDR_HI word*/ 2993*5e779b17SHawking Zhang /*define for sb_addr_63_32 field*/ 2994*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 2995*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 2996*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 2997*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 2998*5e779b17SHawking Zhang 2999*5e779b17SHawking Zhang /*define for START_INDEX word*/ 3000*5e779b17SHawking Zhang /*define for start_index field*/ 3001*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 3002*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 3003*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 3004*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 3005*5e779b17SHawking Zhang 3006*5e779b17SHawking Zhang /*define for COUNT word*/ 3007*5e779b17SHawking Zhang /*define for count field*/ 3008*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 3009*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 3010*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 3011*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 3012*5e779b17SHawking Zhang 3013*5e779b17SHawking Zhang /*define for DW_5 word*/ 3014*5e779b17SHawking Zhang /*define for stride field*/ 3015*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 3016*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 3017*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 3018*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 3019*5e779b17SHawking Zhang 3020*5e779b17SHawking Zhang /*define for linear_sw field*/ 3021*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 3022*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 3023*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 3024*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 3025*5e779b17SHawking Zhang 3026*5e779b17SHawking Zhang /*define for linear_cache_policy field*/ 3027*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset 5 3028*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask 0x00000007 3029*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift 18 3030*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift) 3031*5e779b17SHawking Zhang 3032*5e779b17SHawking Zhang /*define for struct_sw field*/ 3033*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 3034*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 3035*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 3036*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 3037*5e779b17SHawking Zhang 3038*5e779b17SHawking Zhang /*define for struct_cache_policy field*/ 3039*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset 5 3040*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask 0x00000007 3041*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift 26 3042*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift) 3043*5e779b17SHawking Zhang 3044*5e779b17SHawking Zhang /*define for LINEAR_ADDR_LO word*/ 3045*5e779b17SHawking Zhang /*define for linear_addr_31_0 field*/ 3046*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 3047*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 3048*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 3049*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 3050*5e779b17SHawking Zhang 3051*5e779b17SHawking Zhang /*define for LINEAR_ADDR_HI word*/ 3052*5e779b17SHawking Zhang /*define for linear_addr_63_32 field*/ 3053*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 3054*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 3055*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 3056*5e779b17SHawking Zhang #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 3057*5e779b17SHawking Zhang 3058*5e779b17SHawking Zhang 3059*5e779b17SHawking Zhang /* 3060*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_WRITE_UNTILED packet 3061*5e779b17SHawking Zhang */ 3062*5e779b17SHawking Zhang 3063*5e779b17SHawking Zhang /*define for HEADER word*/ 3064*5e779b17SHawking Zhang /*define for op field*/ 3065*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 3066*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 3067*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 3068*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 3069*5e779b17SHawking Zhang 3070*5e779b17SHawking Zhang /*define for sub_op field*/ 3071*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 3072*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 3073*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 3074*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 3075*5e779b17SHawking Zhang 3076*5e779b17SHawking Zhang /*define for encrypt field*/ 3077*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 3078*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 3079*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 3080*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 3081*5e779b17SHawking Zhang 3082*5e779b17SHawking Zhang /*define for tmz field*/ 3083*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 3084*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 3085*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 3086*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 3087*5e779b17SHawking Zhang 3088*5e779b17SHawking Zhang /*define for cpv field*/ 3089*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset 0 3090*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask 0x00000001 3091*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift 28 3092*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift) 3093*5e779b17SHawking Zhang 3094*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 3095*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 3096*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 3097*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3098*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 3099*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 3100*5e779b17SHawking Zhang 3101*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 3102*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 3103*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 3104*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3105*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 3106*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 3107*5e779b17SHawking Zhang 3108*5e779b17SHawking Zhang /*define for DW_3 word*/ 3109*5e779b17SHawking Zhang /*define for count field*/ 3110*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 3111*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 3112*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 3113*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 3114*5e779b17SHawking Zhang 3115*5e779b17SHawking Zhang /*define for sw field*/ 3116*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 3117*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 3118*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 3119*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 3120*5e779b17SHawking Zhang 3121*5e779b17SHawking Zhang /*define for cache_policy field*/ 3122*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset 3 3123*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask 0x00000007 3124*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift 26 3125*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift) 3126*5e779b17SHawking Zhang 3127*5e779b17SHawking Zhang /*define for DATA0 word*/ 3128*5e779b17SHawking Zhang /*define for data0 field*/ 3129*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 3130*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 3131*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 3132*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 3133*5e779b17SHawking Zhang 3134*5e779b17SHawking Zhang 3135*5e779b17SHawking Zhang /* 3136*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_WRITE_TILED packet 3137*5e779b17SHawking Zhang */ 3138*5e779b17SHawking Zhang 3139*5e779b17SHawking Zhang /*define for HEADER word*/ 3140*5e779b17SHawking Zhang /*define for op field*/ 3141*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 3142*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 3143*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 3144*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 3145*5e779b17SHawking Zhang 3146*5e779b17SHawking Zhang /*define for sub_op field*/ 3147*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 3148*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 3149*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 3150*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 3151*5e779b17SHawking Zhang 3152*5e779b17SHawking Zhang /*define for encrypt field*/ 3153*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 3154*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 3155*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 3156*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 3157*5e779b17SHawking Zhang 3158*5e779b17SHawking Zhang /*define for tmz field*/ 3159*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 3160*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 3161*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 3162*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 3163*5e779b17SHawking Zhang 3164*5e779b17SHawking Zhang /*define for cpv field*/ 3165*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_cpv_offset 0 3166*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_cpv_mask 0x00000001 3167*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_cpv_shift 28 3168*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_TILED_HEADER_cpv_shift) 3169*5e779b17SHawking Zhang 3170*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 3171*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 3172*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 3173*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3174*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 3175*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 3176*5e779b17SHawking Zhang 3177*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 3178*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 3179*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 3180*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3181*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 3182*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 3183*5e779b17SHawking Zhang 3184*5e779b17SHawking Zhang /*define for DW_3 word*/ 3185*5e779b17SHawking Zhang /*define for width field*/ 3186*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 3187*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 3188*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 3189*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 3190*5e779b17SHawking Zhang 3191*5e779b17SHawking Zhang /*define for DW_4 word*/ 3192*5e779b17SHawking Zhang /*define for height field*/ 3193*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 3194*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 3195*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 3196*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 3197*5e779b17SHawking Zhang 3198*5e779b17SHawking Zhang /*define for depth field*/ 3199*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 3200*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF 3201*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 3202*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 3203*5e779b17SHawking Zhang 3204*5e779b17SHawking Zhang /*define for DW_5 word*/ 3205*5e779b17SHawking Zhang /*define for element_size field*/ 3206*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 3207*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 3208*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 3209*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 3210*5e779b17SHawking Zhang 3211*5e779b17SHawking Zhang /*define for swizzle_mode field*/ 3212*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 3213*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 3214*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 3215*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 3216*5e779b17SHawking Zhang 3217*5e779b17SHawking Zhang /*define for dimension field*/ 3218*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 3219*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 3220*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 3221*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 3222*5e779b17SHawking Zhang 3223*5e779b17SHawking Zhang /*define for mip_max field*/ 3224*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 3225*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F 3226*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 3227*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) 3228*5e779b17SHawking Zhang 3229*5e779b17SHawking Zhang /*define for DW_6 word*/ 3230*5e779b17SHawking Zhang /*define for x field*/ 3231*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 3232*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 3233*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 3234*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 3235*5e779b17SHawking Zhang 3236*5e779b17SHawking Zhang /*define for y field*/ 3237*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 3238*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 3239*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 3240*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 3241*5e779b17SHawking Zhang 3242*5e779b17SHawking Zhang /*define for DW_7 word*/ 3243*5e779b17SHawking Zhang /*define for z field*/ 3244*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 3245*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF 3246*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 3247*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 3248*5e779b17SHawking Zhang 3249*5e779b17SHawking Zhang /*define for sw field*/ 3250*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 3251*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 3252*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 3253*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 3254*5e779b17SHawking Zhang 3255*5e779b17SHawking Zhang /*define for cache_policy field*/ 3256*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset 7 3257*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask 0x00000007 3258*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift 26 3259*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask) << SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift) 3260*5e779b17SHawking Zhang 3261*5e779b17SHawking Zhang /*define for COUNT word*/ 3262*5e779b17SHawking Zhang /*define for count field*/ 3263*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 3264*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 3265*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 3266*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 3267*5e779b17SHawking Zhang 3268*5e779b17SHawking Zhang /*define for DATA0 word*/ 3269*5e779b17SHawking Zhang /*define for data0 field*/ 3270*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 3271*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 3272*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 3273*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 3274*5e779b17SHawking Zhang 3275*5e779b17SHawking Zhang 3276*5e779b17SHawking Zhang /* 3277*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_WRITE_TILED_BC packet 3278*5e779b17SHawking Zhang */ 3279*5e779b17SHawking Zhang 3280*5e779b17SHawking Zhang /*define for HEADER word*/ 3281*5e779b17SHawking Zhang /*define for op field*/ 3282*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 3283*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF 3284*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 3285*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) 3286*5e779b17SHawking Zhang 3287*5e779b17SHawking Zhang /*define for sub_op field*/ 3288*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 3289*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF 3290*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 3291*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) 3292*5e779b17SHawking Zhang 3293*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 3294*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 3295*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 3296*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3297*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 3298*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) 3299*5e779b17SHawking Zhang 3300*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 3301*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 3302*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 3303*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3304*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 3305*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) 3306*5e779b17SHawking Zhang 3307*5e779b17SHawking Zhang /*define for DW_3 word*/ 3308*5e779b17SHawking Zhang /*define for width field*/ 3309*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 3310*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF 3311*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 3312*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) 3313*5e779b17SHawking Zhang 3314*5e779b17SHawking Zhang /*define for DW_4 word*/ 3315*5e779b17SHawking Zhang /*define for height field*/ 3316*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 3317*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF 3318*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 3319*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) 3320*5e779b17SHawking Zhang 3321*5e779b17SHawking Zhang /*define for depth field*/ 3322*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 3323*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF 3324*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 3325*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) 3326*5e779b17SHawking Zhang 3327*5e779b17SHawking Zhang /*define for DW_5 word*/ 3328*5e779b17SHawking Zhang /*define for element_size field*/ 3329*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 3330*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 3331*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 3332*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) 3333*5e779b17SHawking Zhang 3334*5e779b17SHawking Zhang /*define for array_mode field*/ 3335*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 3336*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F 3337*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 3338*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) 3339*5e779b17SHawking Zhang 3340*5e779b17SHawking Zhang /*define for mit_mode field*/ 3341*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 3342*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 3343*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 3344*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) 3345*5e779b17SHawking Zhang 3346*5e779b17SHawking Zhang /*define for tilesplit_size field*/ 3347*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 3348*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 3349*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 3350*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) 3351*5e779b17SHawking Zhang 3352*5e779b17SHawking Zhang /*define for bank_w field*/ 3353*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 3354*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 3355*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 3356*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) 3357*5e779b17SHawking Zhang 3358*5e779b17SHawking Zhang /*define for bank_h field*/ 3359*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 3360*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 3361*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 3362*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) 3363*5e779b17SHawking Zhang 3364*5e779b17SHawking Zhang /*define for num_bank field*/ 3365*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 3366*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 3367*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 3368*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) 3369*5e779b17SHawking Zhang 3370*5e779b17SHawking Zhang /*define for mat_aspt field*/ 3371*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 3372*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 3373*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 3374*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) 3375*5e779b17SHawking Zhang 3376*5e779b17SHawking Zhang /*define for pipe_config field*/ 3377*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 3378*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F 3379*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 3380*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) 3381*5e779b17SHawking Zhang 3382*5e779b17SHawking Zhang /*define for DW_6 word*/ 3383*5e779b17SHawking Zhang /*define for x field*/ 3384*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 3385*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF 3386*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 3387*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) 3388*5e779b17SHawking Zhang 3389*5e779b17SHawking Zhang /*define for y field*/ 3390*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 3391*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF 3392*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 3393*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) 3394*5e779b17SHawking Zhang 3395*5e779b17SHawking Zhang /*define for DW_7 word*/ 3396*5e779b17SHawking Zhang /*define for z field*/ 3397*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 3398*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF 3399*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 3400*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) 3401*5e779b17SHawking Zhang 3402*5e779b17SHawking Zhang /*define for sw field*/ 3403*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 3404*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 3405*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 3406*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) 3407*5e779b17SHawking Zhang 3408*5e779b17SHawking Zhang /*define for COUNT word*/ 3409*5e779b17SHawking Zhang /*define for count field*/ 3410*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 3411*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF 3412*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 3413*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) 3414*5e779b17SHawking Zhang 3415*5e779b17SHawking Zhang /*define for DATA0 word*/ 3416*5e779b17SHawking Zhang /*define for data0 field*/ 3417*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 3418*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF 3419*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 3420*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) 3421*5e779b17SHawking Zhang 3422*5e779b17SHawking Zhang 3423*5e779b17SHawking Zhang /* 3424*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_PTEPDE_COPY packet 3425*5e779b17SHawking Zhang */ 3426*5e779b17SHawking Zhang 3427*5e779b17SHawking Zhang /*define for HEADER word*/ 3428*5e779b17SHawking Zhang /*define for op field*/ 3429*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 3430*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 3431*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 3432*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 3433*5e779b17SHawking Zhang 3434*5e779b17SHawking Zhang /*define for sub_op field*/ 3435*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 3436*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 3437*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 3438*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 3439*5e779b17SHawking Zhang 3440*5e779b17SHawking Zhang /*define for tmz field*/ 3441*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 3442*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 3443*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 3444*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) 3445*5e779b17SHawking Zhang 3446*5e779b17SHawking Zhang /*define for cpv field*/ 3447*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset 0 3448*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask 0x00000001 3449*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift 28 3450*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift) 3451*5e779b17SHawking Zhang 3452*5e779b17SHawking Zhang /*define for ptepde_op field*/ 3453*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 3454*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 3455*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 3456*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 3457*5e779b17SHawking Zhang 3458*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 3459*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 3460*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 3461*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3462*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 3463*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 3464*5e779b17SHawking Zhang 3465*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 3466*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 3467*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 3468*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3469*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 3470*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 3471*5e779b17SHawking Zhang 3472*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 3473*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 3474*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 3475*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3476*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 3477*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 3478*5e779b17SHawking Zhang 3479*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 3480*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 3481*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 3482*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3483*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 3484*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 3485*5e779b17SHawking Zhang 3486*5e779b17SHawking Zhang /*define for MASK_DW0 word*/ 3487*5e779b17SHawking Zhang /*define for mask_dw0 field*/ 3488*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 3489*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3490*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 3491*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 3492*5e779b17SHawking Zhang 3493*5e779b17SHawking Zhang /*define for MASK_DW1 word*/ 3494*5e779b17SHawking Zhang /*define for mask_dw1 field*/ 3495*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 3496*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3497*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 3498*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 3499*5e779b17SHawking Zhang 3500*5e779b17SHawking Zhang /*define for COUNT word*/ 3501*5e779b17SHawking Zhang /*define for count field*/ 3502*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 3503*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 3504*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 3505*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 3506*5e779b17SHawking Zhang 3507*5e779b17SHawking Zhang /*define for dst_cache_policy field*/ 3508*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset 7 3509*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask 0x00000007 3510*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift 22 3511*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift) 3512*5e779b17SHawking Zhang 3513*5e779b17SHawking Zhang /*define for src_cache_policy field*/ 3514*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset 7 3515*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask 0x00000007 3516*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift 29 3517*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift) 3518*5e779b17SHawking Zhang 3519*5e779b17SHawking Zhang 3520*5e779b17SHawking Zhang /* 3521*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 3522*5e779b17SHawking Zhang */ 3523*5e779b17SHawking Zhang 3524*5e779b17SHawking Zhang /*define for HEADER word*/ 3525*5e779b17SHawking Zhang /*define for op field*/ 3526*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 3527*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 3528*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 3529*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 3530*5e779b17SHawking Zhang 3531*5e779b17SHawking Zhang /*define for sub_op field*/ 3532*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 3533*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 3534*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 3535*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 3536*5e779b17SHawking Zhang 3537*5e779b17SHawking Zhang /*define for pte_size field*/ 3538*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 3539*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 3540*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 3541*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 3542*5e779b17SHawking Zhang 3543*5e779b17SHawking Zhang /*define for direction field*/ 3544*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 3545*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 3546*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 3547*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 3548*5e779b17SHawking Zhang 3549*5e779b17SHawking Zhang /*define for ptepde_op field*/ 3550*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 3551*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 3552*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 3553*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 3554*5e779b17SHawking Zhang 3555*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 3556*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 3557*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 3558*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3559*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 3560*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 3561*5e779b17SHawking Zhang 3562*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 3563*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 3564*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 3565*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3566*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 3567*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 3568*5e779b17SHawking Zhang 3569*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 3570*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 3571*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 3572*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3573*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 3574*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 3575*5e779b17SHawking Zhang 3576*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 3577*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 3578*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 3579*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3580*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 3581*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 3582*5e779b17SHawking Zhang 3583*5e779b17SHawking Zhang /*define for MASK_BIT_FOR_DW word*/ 3584*5e779b17SHawking Zhang /*define for mask_first_xfer field*/ 3585*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 3586*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 3587*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 3588*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 3589*5e779b17SHawking Zhang 3590*5e779b17SHawking Zhang /*define for mask_last_xfer field*/ 3591*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 3592*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 3593*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 3594*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 3595*5e779b17SHawking Zhang 3596*5e779b17SHawking Zhang /*define for COUNT_IN_32B_XFER word*/ 3597*5e779b17SHawking Zhang /*define for count field*/ 3598*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 3599*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 3600*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 3601*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 3602*5e779b17SHawking Zhang 3603*5e779b17SHawking Zhang 3604*5e779b17SHawking Zhang /* 3605*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_PTEPDE_RMW packet 3606*5e779b17SHawking Zhang */ 3607*5e779b17SHawking Zhang 3608*5e779b17SHawking Zhang /*define for HEADER word*/ 3609*5e779b17SHawking Zhang /*define for op field*/ 3610*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 3611*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 3612*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 3613*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 3614*5e779b17SHawking Zhang 3615*5e779b17SHawking Zhang /*define for sub_op field*/ 3616*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 3617*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 3618*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 3619*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 3620*5e779b17SHawking Zhang 3621*5e779b17SHawking Zhang /*define for mtype field*/ 3622*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 3623*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 3624*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 3625*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) 3626*5e779b17SHawking Zhang 3627*5e779b17SHawking Zhang /*define for gcc field*/ 3628*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 3629*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 3630*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 3631*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 3632*5e779b17SHawking Zhang 3633*5e779b17SHawking Zhang /*define for sys field*/ 3634*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 3635*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 3636*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 3637*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 3638*5e779b17SHawking Zhang 3639*5e779b17SHawking Zhang /*define for snp field*/ 3640*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 3641*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 3642*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 3643*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 3644*5e779b17SHawking Zhang 3645*5e779b17SHawking Zhang /*define for gpa field*/ 3646*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 3647*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 3648*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 3649*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 3650*5e779b17SHawking Zhang 3651*5e779b17SHawking Zhang /*define for l2_policy field*/ 3652*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 3653*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 3654*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 3655*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) 3656*5e779b17SHawking Zhang 3657*5e779b17SHawking Zhang /*define for llc_policy field*/ 3658*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset 0 3659*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask 0x00000001 3660*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift 26 3661*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift) 3662*5e779b17SHawking Zhang 3663*5e779b17SHawking Zhang /*define for cpv field*/ 3664*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset 0 3665*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask 0x00000001 3666*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift 28 3667*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift) 3668*5e779b17SHawking Zhang 3669*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 3670*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 3671*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 3672*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3673*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 3674*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 3675*5e779b17SHawking Zhang 3676*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 3677*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 3678*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 3679*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3680*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 3681*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 3682*5e779b17SHawking Zhang 3683*5e779b17SHawking Zhang /*define for MASK_LO word*/ 3684*5e779b17SHawking Zhang /*define for mask_31_0 field*/ 3685*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 3686*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 3687*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 3688*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 3689*5e779b17SHawking Zhang 3690*5e779b17SHawking Zhang /*define for MASK_HI word*/ 3691*5e779b17SHawking Zhang /*define for mask_63_32 field*/ 3692*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 3693*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 3694*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 3695*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 3696*5e779b17SHawking Zhang 3697*5e779b17SHawking Zhang /*define for VALUE_LO word*/ 3698*5e779b17SHawking Zhang /*define for value_31_0 field*/ 3699*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 3700*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 3701*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 3702*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 3703*5e779b17SHawking Zhang 3704*5e779b17SHawking Zhang /*define for VALUE_HI word*/ 3705*5e779b17SHawking Zhang /*define for value_63_32 field*/ 3706*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 3707*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 3708*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 3709*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 3710*5e779b17SHawking Zhang 3711*5e779b17SHawking Zhang /*define for COUNT word*/ 3712*5e779b17SHawking Zhang /*define for num_of_pte field*/ 3713*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset 7 3714*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask 0xFFFFFFFF 3715*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift 0 3716*5e779b17SHawking Zhang #define SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x) (((x) & SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask) << SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift) 3717*5e779b17SHawking Zhang 3718*5e779b17SHawking Zhang 3719*5e779b17SHawking Zhang /* 3720*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_REGISTER_RMW packet 3721*5e779b17SHawking Zhang */ 3722*5e779b17SHawking Zhang 3723*5e779b17SHawking Zhang /*define for HEADER word*/ 3724*5e779b17SHawking Zhang /*define for op field*/ 3725*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_op_offset 0 3726*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_op_mask 0x000000FF 3727*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_op_shift 0 3728*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_op_shift) 3729*5e779b17SHawking Zhang 3730*5e779b17SHawking Zhang /*define for sub_op field*/ 3731*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset 0 3732*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask 0x000000FF 3733*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift 8 3734*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift) 3735*5e779b17SHawking Zhang 3736*5e779b17SHawking Zhang /*define for ADDR word*/ 3737*5e779b17SHawking Zhang /*define for addr field*/ 3738*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_addr_offset 1 3739*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_addr_mask 0x000FFFFF 3740*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_addr_shift 0 3741*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_addr_mask) << SDMA_PKT_REGISTER_RMW_ADDR_addr_shift) 3742*5e779b17SHawking Zhang 3743*5e779b17SHawking Zhang /*define for aperture_id field*/ 3744*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset 1 3745*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask 0x00000FFF 3746*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift 20 3747*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask) << SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift) 3748*5e779b17SHawking Zhang 3749*5e779b17SHawking Zhang /*define for MASK word*/ 3750*5e779b17SHawking Zhang /*define for mask field*/ 3751*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MASK_mask_offset 2 3752*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MASK_mask_mask 0xFFFFFFFF 3753*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MASK_mask_shift 0 3754*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MASK_MASK(x) (((x) & SDMA_PKT_REGISTER_RMW_MASK_mask_mask) << SDMA_PKT_REGISTER_RMW_MASK_mask_shift) 3755*5e779b17SHawking Zhang 3756*5e779b17SHawking Zhang /*define for VALUE word*/ 3757*5e779b17SHawking Zhang /*define for value field*/ 3758*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_VALUE_value_offset 3 3759*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_VALUE_value_mask 0xFFFFFFFF 3760*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_VALUE_value_shift 0 3761*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x) (((x) & SDMA_PKT_REGISTER_RMW_VALUE_value_mask) << SDMA_PKT_REGISTER_RMW_VALUE_value_shift) 3762*5e779b17SHawking Zhang 3763*5e779b17SHawking Zhang /*define for MISC word*/ 3764*5e779b17SHawking Zhang /*define for stride field*/ 3765*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_stride_offset 4 3766*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_stride_mask 0x000FFFFF 3767*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_stride_shift 0 3768*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_stride_mask) << SDMA_PKT_REGISTER_RMW_MISC_stride_shift) 3769*5e779b17SHawking Zhang 3770*5e779b17SHawking Zhang /*define for num_of_reg field*/ 3771*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset 4 3772*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask 0x00000FFF 3773*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift 20 3774*5e779b17SHawking Zhang #define SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask) << SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift) 3775*5e779b17SHawking Zhang 3776*5e779b17SHawking Zhang 3777*5e779b17SHawking Zhang /* 3778*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_WRITE_INCR packet 3779*5e779b17SHawking Zhang */ 3780*5e779b17SHawking Zhang 3781*5e779b17SHawking Zhang /*define for HEADER word*/ 3782*5e779b17SHawking Zhang /*define for op field*/ 3783*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 3784*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 3785*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 3786*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 3787*5e779b17SHawking Zhang 3788*5e779b17SHawking Zhang /*define for sub_op field*/ 3789*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 3790*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 3791*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 3792*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 3793*5e779b17SHawking Zhang 3794*5e779b17SHawking Zhang /*define for cache_policy field*/ 3795*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset 0 3796*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask 0x00000007 3797*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift 24 3798*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask) << SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift) 3799*5e779b17SHawking Zhang 3800*5e779b17SHawking Zhang /*define for cpv field*/ 3801*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_cpv_offset 0 3802*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_cpv_mask 0x00000001 3803*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_cpv_shift 28 3804*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cpv_mask) << SDMA_PKT_WRITE_INCR_HEADER_cpv_shift) 3805*5e779b17SHawking Zhang 3806*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 3807*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 3808*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 3809*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3810*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 3811*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 3812*5e779b17SHawking Zhang 3813*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 3814*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 3815*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 3816*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3817*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 3818*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 3819*5e779b17SHawking Zhang 3820*5e779b17SHawking Zhang /*define for MASK_DW0 word*/ 3821*5e779b17SHawking Zhang /*define for mask_dw0 field*/ 3822*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 3823*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3824*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 3825*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 3826*5e779b17SHawking Zhang 3827*5e779b17SHawking Zhang /*define for MASK_DW1 word*/ 3828*5e779b17SHawking Zhang /*define for mask_dw1 field*/ 3829*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 3830*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3831*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 3832*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 3833*5e779b17SHawking Zhang 3834*5e779b17SHawking Zhang /*define for INIT_DW0 word*/ 3835*5e779b17SHawking Zhang /*define for init_dw0 field*/ 3836*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 3837*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 3838*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 3839*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 3840*5e779b17SHawking Zhang 3841*5e779b17SHawking Zhang /*define for INIT_DW1 word*/ 3842*5e779b17SHawking Zhang /*define for init_dw1 field*/ 3843*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 3844*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 3845*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 3846*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 3847*5e779b17SHawking Zhang 3848*5e779b17SHawking Zhang /*define for INCR_DW0 word*/ 3849*5e779b17SHawking Zhang /*define for incr_dw0 field*/ 3850*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 3851*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 3852*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 3853*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 3854*5e779b17SHawking Zhang 3855*5e779b17SHawking Zhang /*define for INCR_DW1 word*/ 3856*5e779b17SHawking Zhang /*define for incr_dw1 field*/ 3857*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 3858*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 3859*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 3860*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 3861*5e779b17SHawking Zhang 3862*5e779b17SHawking Zhang /*define for COUNT word*/ 3863*5e779b17SHawking Zhang /*define for count field*/ 3864*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 3865*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 3866*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 3867*5e779b17SHawking Zhang #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 3868*5e779b17SHawking Zhang 3869*5e779b17SHawking Zhang 3870*5e779b17SHawking Zhang /* 3871*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_INDIRECT packet 3872*5e779b17SHawking Zhang */ 3873*5e779b17SHawking Zhang 3874*5e779b17SHawking Zhang /*define for HEADER word*/ 3875*5e779b17SHawking Zhang /*define for op field*/ 3876*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 3877*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 3878*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 3879*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 3880*5e779b17SHawking Zhang 3881*5e779b17SHawking Zhang /*define for sub_op field*/ 3882*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 3883*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 3884*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 3885*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 3886*5e779b17SHawking Zhang 3887*5e779b17SHawking Zhang /*define for vmid field*/ 3888*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 3889*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 3890*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 3891*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 3892*5e779b17SHawking Zhang 3893*5e779b17SHawking Zhang /*define for priv field*/ 3894*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 3895*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 3896*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 3897*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) 3898*5e779b17SHawking Zhang 3899*5e779b17SHawking Zhang /*define for BASE_LO word*/ 3900*5e779b17SHawking Zhang /*define for ib_base_31_0 field*/ 3901*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 3902*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 3903*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 3904*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 3905*5e779b17SHawking Zhang 3906*5e779b17SHawking Zhang /*define for BASE_HI word*/ 3907*5e779b17SHawking Zhang /*define for ib_base_63_32 field*/ 3908*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 3909*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 3910*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 3911*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 3912*5e779b17SHawking Zhang 3913*5e779b17SHawking Zhang /*define for IB_SIZE word*/ 3914*5e779b17SHawking Zhang /*define for ib_size field*/ 3915*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 3916*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 3917*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 3918*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 3919*5e779b17SHawking Zhang 3920*5e779b17SHawking Zhang /*define for CSA_ADDR_LO word*/ 3921*5e779b17SHawking Zhang /*define for csa_addr_31_0 field*/ 3922*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 3923*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 3924*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 3925*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 3926*5e779b17SHawking Zhang 3927*5e779b17SHawking Zhang /*define for CSA_ADDR_HI word*/ 3928*5e779b17SHawking Zhang /*define for csa_addr_63_32 field*/ 3929*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 3930*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 3931*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 3932*5e779b17SHawking Zhang #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 3933*5e779b17SHawking Zhang 3934*5e779b17SHawking Zhang 3935*5e779b17SHawking Zhang /* 3936*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_SEMAPHORE packet 3937*5e779b17SHawking Zhang */ 3938*5e779b17SHawking Zhang 3939*5e779b17SHawking Zhang /*define for HEADER word*/ 3940*5e779b17SHawking Zhang /*define for op field*/ 3941*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 3942*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 3943*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 3944*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 3945*5e779b17SHawking Zhang 3946*5e779b17SHawking Zhang /*define for sub_op field*/ 3947*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 3948*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 3949*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 3950*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 3951*5e779b17SHawking Zhang 3952*5e779b17SHawking Zhang /*define for write_one field*/ 3953*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 3954*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 3955*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 3956*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 3957*5e779b17SHawking Zhang 3958*5e779b17SHawking Zhang /*define for signal field*/ 3959*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 3960*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 3961*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 3962*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 3963*5e779b17SHawking Zhang 3964*5e779b17SHawking Zhang /*define for mailbox field*/ 3965*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 3966*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 3967*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 3968*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 3969*5e779b17SHawking Zhang 3970*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 3971*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 3972*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 3973*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3974*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 3975*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 3976*5e779b17SHawking Zhang 3977*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 3978*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 3979*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 3980*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3981*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 3982*5e779b17SHawking Zhang #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 3983*5e779b17SHawking Zhang 3984*5e779b17SHawking Zhang 3985*5e779b17SHawking Zhang /* 3986*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_MEM_INCR packet 3987*5e779b17SHawking Zhang */ 3988*5e779b17SHawking Zhang 3989*5e779b17SHawking Zhang /*define for HEADER word*/ 3990*5e779b17SHawking Zhang /*define for op field*/ 3991*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_op_offset 0 3992*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_op_mask 0x000000FF 3993*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_op_shift 0 3994*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_op_mask) << SDMA_PKT_MEM_INCR_HEADER_op_shift) 3995*5e779b17SHawking Zhang 3996*5e779b17SHawking Zhang /*define for sub_op field*/ 3997*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_sub_op_offset 0 3998*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_sub_op_mask 0x000000FF 3999*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_sub_op_shift 8 4000*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_sub_op_mask) << SDMA_PKT_MEM_INCR_HEADER_sub_op_shift) 4001*5e779b17SHawking Zhang 4002*5e779b17SHawking Zhang /*define for l2_policy field*/ 4003*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset 0 4004*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask 0x00000003 4005*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift 24 4006*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift) 4007*5e779b17SHawking Zhang 4008*5e779b17SHawking Zhang /*define for llc_policy field*/ 4009*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset 0 4010*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask 0x00000001 4011*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift 26 4012*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift) 4013*5e779b17SHawking Zhang 4014*5e779b17SHawking Zhang /*define for cpv field*/ 4015*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_cpv_offset 0 4016*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_cpv_mask 0x00000001 4017*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_cpv_shift 28 4018*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_cpv_mask) << SDMA_PKT_MEM_INCR_HEADER_cpv_shift) 4019*5e779b17SHawking Zhang 4020*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 4021*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4022*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset 1 4023*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4024*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift 0 4025*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask) << SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift) 4026*5e779b17SHawking Zhang 4027*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 4028*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4029*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset 2 4030*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4031*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift 0 4032*5e779b17SHawking Zhang #define SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask) << SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift) 4033*5e779b17SHawking Zhang 4034*5e779b17SHawking Zhang 4035*5e779b17SHawking Zhang /* 4036*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_VM_INVALIDATION packet 4037*5e779b17SHawking Zhang */ 4038*5e779b17SHawking Zhang 4039*5e779b17SHawking Zhang /*define for HEADER word*/ 4040*5e779b17SHawking Zhang /*define for op field*/ 4041*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0 4042*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF 4043*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0 4044*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) 4045*5e779b17SHawking Zhang 4046*5e779b17SHawking Zhang /*define for sub_op field*/ 4047*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0 4048*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF 4049*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8 4050*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) 4051*5e779b17SHawking Zhang 4052*5e779b17SHawking Zhang /*define for gfx_eng_id field*/ 4053*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0 4054*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask 0x0000001F 4055*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift 16 4056*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) 4057*5e779b17SHawking Zhang 4058*5e779b17SHawking Zhang /*define for mm_eng_id field*/ 4059*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0 4060*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask 0x0000001F 4061*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift 24 4062*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) 4063*5e779b17SHawking Zhang 4064*5e779b17SHawking Zhang /*define for INVALIDATEREQ word*/ 4065*5e779b17SHawking Zhang /*define for invalidatereq field*/ 4066*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1 4067*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF 4068*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0 4069*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) 4070*5e779b17SHawking Zhang 4071*5e779b17SHawking Zhang /*define for ADDRESSRANGELO word*/ 4072*5e779b17SHawking Zhang /*define for addressrangelo field*/ 4073*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2 4074*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF 4075*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0 4076*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) 4077*5e779b17SHawking Zhang 4078*5e779b17SHawking Zhang /*define for ADDRESSRANGEHI word*/ 4079*5e779b17SHawking Zhang /*define for invalidateack field*/ 4080*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3 4081*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF 4082*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0 4083*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) 4084*5e779b17SHawking Zhang 4085*5e779b17SHawking Zhang /*define for addressrangehi field*/ 4086*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3 4087*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F 4088*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16 4089*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) 4090*5e779b17SHawking Zhang 4091*5e779b17SHawking Zhang /*define for reserved field*/ 4092*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3 4093*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF 4094*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23 4095*5e779b17SHawking Zhang #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) 4096*5e779b17SHawking Zhang 4097*5e779b17SHawking Zhang 4098*5e779b17SHawking Zhang /* 4099*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_FENCE packet 4100*5e779b17SHawking Zhang */ 4101*5e779b17SHawking Zhang 4102*5e779b17SHawking Zhang /*define for HEADER word*/ 4103*5e779b17SHawking Zhang /*define for op field*/ 4104*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_op_offset 0 4105*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 4106*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_op_shift 0 4107*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 4108*5e779b17SHawking Zhang 4109*5e779b17SHawking Zhang /*define for sub_op field*/ 4110*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 4111*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 4112*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 4113*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 4114*5e779b17SHawking Zhang 4115*5e779b17SHawking Zhang /*define for mtype field*/ 4116*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_mtype_offset 0 4117*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 4118*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_mtype_shift 16 4119*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) 4120*5e779b17SHawking Zhang 4121*5e779b17SHawking Zhang /*define for gcc field*/ 4122*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_gcc_offset 0 4123*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 4124*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_gcc_shift 19 4125*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) 4126*5e779b17SHawking Zhang 4127*5e779b17SHawking Zhang /*define for sys field*/ 4128*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_sys_offset 0 4129*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 4130*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_sys_shift 20 4131*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) 4132*5e779b17SHawking Zhang 4133*5e779b17SHawking Zhang /*define for snp field*/ 4134*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_snp_offset 0 4135*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 4136*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_snp_shift 22 4137*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) 4138*5e779b17SHawking Zhang 4139*5e779b17SHawking Zhang /*define for gpa field*/ 4140*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_gpa_offset 0 4141*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 4142*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_gpa_shift 23 4143*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) 4144*5e779b17SHawking Zhang 4145*5e779b17SHawking Zhang /*define for l2_policy field*/ 4146*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 4147*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 4148*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 4149*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) 4150*5e779b17SHawking Zhang 4151*5e779b17SHawking Zhang /*define for llc_policy field*/ 4152*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_llc_policy_offset 0 4153*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_llc_policy_mask 0x00000001 4154*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_llc_policy_shift 26 4155*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_llc_policy_mask) << SDMA_PKT_FENCE_HEADER_llc_policy_shift) 4156*5e779b17SHawking Zhang 4157*5e779b17SHawking Zhang /*define for cpv field*/ 4158*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_cpv_offset 0 4159*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_cpv_mask 0x00000001 4160*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_cpv_shift 28 4161*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_HEADER_CPV(x) (((x) & SDMA_PKT_FENCE_HEADER_cpv_mask) << SDMA_PKT_FENCE_HEADER_cpv_shift) 4162*5e779b17SHawking Zhang 4163*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 4164*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4165*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 4166*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4167*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 4168*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 4169*5e779b17SHawking Zhang 4170*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 4171*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4172*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 4173*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4174*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 4175*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 4176*5e779b17SHawking Zhang 4177*5e779b17SHawking Zhang /*define for DATA word*/ 4178*5e779b17SHawking Zhang /*define for data field*/ 4179*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_DATA_data_offset 3 4180*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 4181*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_DATA_data_shift 0 4182*5e779b17SHawking Zhang #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 4183*5e779b17SHawking Zhang 4184*5e779b17SHawking Zhang 4185*5e779b17SHawking Zhang /* 4186*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_SRBM_WRITE packet 4187*5e779b17SHawking Zhang */ 4188*5e779b17SHawking Zhang 4189*5e779b17SHawking Zhang /*define for HEADER word*/ 4190*5e779b17SHawking Zhang /*define for op field*/ 4191*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 4192*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 4193*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 4194*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 4195*5e779b17SHawking Zhang 4196*5e779b17SHawking Zhang /*define for sub_op field*/ 4197*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 4198*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 4199*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 4200*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 4201*5e779b17SHawking Zhang 4202*5e779b17SHawking Zhang /*define for byte_en field*/ 4203*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 4204*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 4205*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 4206*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 4207*5e779b17SHawking Zhang 4208*5e779b17SHawking Zhang /*define for ADDR word*/ 4209*5e779b17SHawking Zhang /*define for addr field*/ 4210*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 4211*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 4212*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 4213*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 4214*5e779b17SHawking Zhang 4215*5e779b17SHawking Zhang /*define for apertureid field*/ 4216*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 4217*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF 4218*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 4219*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) 4220*5e779b17SHawking Zhang 4221*5e779b17SHawking Zhang /*define for DATA word*/ 4222*5e779b17SHawking Zhang /*define for data field*/ 4223*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 4224*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 4225*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 4226*5e779b17SHawking Zhang #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 4227*5e779b17SHawking Zhang 4228*5e779b17SHawking Zhang 4229*5e779b17SHawking Zhang /* 4230*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_PRE_EXE packet 4231*5e779b17SHawking Zhang */ 4232*5e779b17SHawking Zhang 4233*5e779b17SHawking Zhang /*define for HEADER word*/ 4234*5e779b17SHawking Zhang /*define for op field*/ 4235*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 4236*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 4237*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 4238*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 4239*5e779b17SHawking Zhang 4240*5e779b17SHawking Zhang /*define for sub_op field*/ 4241*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 4242*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 4243*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 4244*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 4245*5e779b17SHawking Zhang 4246*5e779b17SHawking Zhang /*define for dev_sel field*/ 4247*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 4248*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 4249*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 4250*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 4251*5e779b17SHawking Zhang 4252*5e779b17SHawking Zhang /*define for EXEC_COUNT word*/ 4253*5e779b17SHawking Zhang /*define for exec_count field*/ 4254*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 4255*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 4256*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 4257*5e779b17SHawking Zhang #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 4258*5e779b17SHawking Zhang 4259*5e779b17SHawking Zhang 4260*5e779b17SHawking Zhang /* 4261*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_COND_EXE packet 4262*5e779b17SHawking Zhang */ 4263*5e779b17SHawking Zhang 4264*5e779b17SHawking Zhang /*define for HEADER word*/ 4265*5e779b17SHawking Zhang /*define for op field*/ 4266*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 4267*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 4268*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 4269*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 4270*5e779b17SHawking Zhang 4271*5e779b17SHawking Zhang /*define for sub_op field*/ 4272*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 4273*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 4274*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 4275*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 4276*5e779b17SHawking Zhang 4277*5e779b17SHawking Zhang /*define for cache_policy field*/ 4278*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_cache_policy_offset 0 4279*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_cache_policy_mask 0x00000007 4280*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_cache_policy_shift 24 4281*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cache_policy_mask) << SDMA_PKT_COND_EXE_HEADER_cache_policy_shift) 4282*5e779b17SHawking Zhang 4283*5e779b17SHawking Zhang /*define for cpv field*/ 4284*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_cpv_offset 0 4285*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_cpv_mask 0x00000001 4286*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_cpv_shift 28 4287*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_HEADER_CPV(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cpv_mask) << SDMA_PKT_COND_EXE_HEADER_cpv_shift) 4288*5e779b17SHawking Zhang 4289*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 4290*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4291*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 4292*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4293*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 4294*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 4295*5e779b17SHawking Zhang 4296*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 4297*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4298*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 4299*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4300*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 4301*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 4302*5e779b17SHawking Zhang 4303*5e779b17SHawking Zhang /*define for REFERENCE word*/ 4304*5e779b17SHawking Zhang /*define for reference field*/ 4305*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 4306*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 4307*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 4308*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 4309*5e779b17SHawking Zhang 4310*5e779b17SHawking Zhang /*define for EXEC_COUNT word*/ 4311*5e779b17SHawking Zhang /*define for exec_count field*/ 4312*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 4313*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 4314*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 4315*5e779b17SHawking Zhang #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 4316*5e779b17SHawking Zhang 4317*5e779b17SHawking Zhang 4318*5e779b17SHawking Zhang /* 4319*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_CONSTANT_FILL packet 4320*5e779b17SHawking Zhang */ 4321*5e779b17SHawking Zhang 4322*5e779b17SHawking Zhang /*define for HEADER word*/ 4323*5e779b17SHawking Zhang /*define for op field*/ 4324*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 4325*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 4326*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 4327*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 4328*5e779b17SHawking Zhang 4329*5e779b17SHawking Zhang /*define for sub_op field*/ 4330*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 4331*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 4332*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 4333*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 4334*5e779b17SHawking Zhang 4335*5e779b17SHawking Zhang /*define for sw field*/ 4336*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 4337*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 4338*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 4339*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 4340*5e779b17SHawking Zhang 4341*5e779b17SHawking Zhang /*define for cache_policy field*/ 4342*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset 0 4343*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask 0x00000007 4344*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift 24 4345*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift) 4346*5e779b17SHawking Zhang 4347*5e779b17SHawking Zhang /*define for cpv field*/ 4348*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset 0 4349*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask 0x00000001 4350*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift 28 4351*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift) 4352*5e779b17SHawking Zhang 4353*5e779b17SHawking Zhang /*define for fillsize field*/ 4354*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 4355*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 4356*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 4357*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 4358*5e779b17SHawking Zhang 4359*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 4360*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 4361*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 4362*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4363*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 4364*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 4365*5e779b17SHawking Zhang 4366*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 4367*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 4368*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 4369*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4370*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 4371*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 4372*5e779b17SHawking Zhang 4373*5e779b17SHawking Zhang /*define for DATA word*/ 4374*5e779b17SHawking Zhang /*define for src_data_31_0 field*/ 4375*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 4376*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 4377*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 4378*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 4379*5e779b17SHawking Zhang 4380*5e779b17SHawking Zhang /*define for COUNT word*/ 4381*5e779b17SHawking Zhang /*define for count field*/ 4382*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 4383*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x3FFFFFFF 4384*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 4385*5e779b17SHawking Zhang #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 4386*5e779b17SHawking Zhang 4387*5e779b17SHawking Zhang 4388*5e779b17SHawking Zhang /* 4389*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 4390*5e779b17SHawking Zhang */ 4391*5e779b17SHawking Zhang 4392*5e779b17SHawking Zhang /*define for HEADER word*/ 4393*5e779b17SHawking Zhang /*define for op field*/ 4394*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 4395*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 4396*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 4397*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 4398*5e779b17SHawking Zhang 4399*5e779b17SHawking Zhang /*define for sub_op field*/ 4400*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 4401*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 4402*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 4403*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 4404*5e779b17SHawking Zhang 4405*5e779b17SHawking Zhang /*define for cache_policy field*/ 4406*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset 0 4407*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask 0x00000007 4408*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift 24 4409*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift) 4410*5e779b17SHawking Zhang 4411*5e779b17SHawking Zhang /*define for cpv field*/ 4412*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset 0 4413*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask 0x00000001 4414*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift 28 4415*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift) 4416*5e779b17SHawking Zhang 4417*5e779b17SHawking Zhang /*define for memlog_clr field*/ 4418*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 4419*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 4420*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 4421*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 4422*5e779b17SHawking Zhang 4423*5e779b17SHawking Zhang /*define for BYTE_STRIDE word*/ 4424*5e779b17SHawking Zhang /*define for byte_stride field*/ 4425*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 4426*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 4427*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 4428*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 4429*5e779b17SHawking Zhang 4430*5e779b17SHawking Zhang /*define for DMA_COUNT word*/ 4431*5e779b17SHawking Zhang /*define for dma_count field*/ 4432*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 4433*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 4434*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 4435*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 4436*5e779b17SHawking Zhang 4437*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 4438*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 4439*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 4440*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4441*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 4442*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 4443*5e779b17SHawking Zhang 4444*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 4445*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 4446*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 4447*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4448*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 4449*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 4450*5e779b17SHawking Zhang 4451*5e779b17SHawking Zhang /*define for BYTE_COUNT word*/ 4452*5e779b17SHawking Zhang /*define for count field*/ 4453*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 4454*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 4455*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 4456*5e779b17SHawking Zhang #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 4457*5e779b17SHawking Zhang 4458*5e779b17SHawking Zhang 4459*5e779b17SHawking Zhang /* 4460*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_POLL_REGMEM packet 4461*5e779b17SHawking Zhang */ 4462*5e779b17SHawking Zhang 4463*5e779b17SHawking Zhang /*define for HEADER word*/ 4464*5e779b17SHawking Zhang /*define for op field*/ 4465*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 4466*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 4467*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 4468*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 4469*5e779b17SHawking Zhang 4470*5e779b17SHawking Zhang /*define for sub_op field*/ 4471*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 4472*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 4473*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 4474*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 4475*5e779b17SHawking Zhang 4476*5e779b17SHawking Zhang /*define for cache_policy field*/ 4477*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset 0 4478*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask 0x00000007 4479*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift 20 4480*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift) 4481*5e779b17SHawking Zhang 4482*5e779b17SHawking Zhang /*define for cpv field*/ 4483*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset 0 4484*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask 0x00000001 4485*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift 24 4486*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift) 4487*5e779b17SHawking Zhang 4488*5e779b17SHawking Zhang /*define for hdp_flush field*/ 4489*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 4490*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 4491*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 4492*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 4493*5e779b17SHawking Zhang 4494*5e779b17SHawking Zhang /*define for func field*/ 4495*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 4496*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 4497*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 4498*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 4499*5e779b17SHawking Zhang 4500*5e779b17SHawking Zhang /*define for mem_poll field*/ 4501*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 4502*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 4503*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 4504*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 4505*5e779b17SHawking Zhang 4506*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 4507*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4508*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 4509*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4510*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 4511*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 4512*5e779b17SHawking Zhang 4513*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 4514*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4515*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 4516*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4517*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 4518*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 4519*5e779b17SHawking Zhang 4520*5e779b17SHawking Zhang /*define for VALUE word*/ 4521*5e779b17SHawking Zhang /*define for value field*/ 4522*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 4523*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 4524*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 4525*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 4526*5e779b17SHawking Zhang 4527*5e779b17SHawking Zhang /*define for MASK word*/ 4528*5e779b17SHawking Zhang /*define for mask field*/ 4529*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 4530*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 4531*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 4532*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 4533*5e779b17SHawking Zhang 4534*5e779b17SHawking Zhang /*define for DW5 word*/ 4535*5e779b17SHawking Zhang /*define for interval field*/ 4536*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 4537*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 4538*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 4539*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 4540*5e779b17SHawking Zhang 4541*5e779b17SHawking Zhang /*define for retry_count field*/ 4542*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 4543*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 4544*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 4545*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 4546*5e779b17SHawking Zhang 4547*5e779b17SHawking Zhang 4548*5e779b17SHawking Zhang /* 4549*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 4550*5e779b17SHawking Zhang */ 4551*5e779b17SHawking Zhang 4552*5e779b17SHawking Zhang /*define for HEADER word*/ 4553*5e779b17SHawking Zhang /*define for op field*/ 4554*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 4555*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 4556*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 4557*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 4558*5e779b17SHawking Zhang 4559*5e779b17SHawking Zhang /*define for sub_op field*/ 4560*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 4561*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 4562*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 4563*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 4564*5e779b17SHawking Zhang 4565*5e779b17SHawking Zhang /*define for cache_policy field*/ 4566*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset 0 4567*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 4568*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift 24 4569*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift) 4570*5e779b17SHawking Zhang 4571*5e779b17SHawking Zhang /*define for cpv field*/ 4572*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset 0 4573*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask 0x00000001 4574*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift 28 4575*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift) 4576*5e779b17SHawking Zhang 4577*5e779b17SHawking Zhang /*define for SRC_ADDR word*/ 4578*5e779b17SHawking Zhang /*define for addr_31_2 field*/ 4579*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 4580*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 4581*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 4582*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 4583*5e779b17SHawking Zhang 4584*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 4585*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4586*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 4587*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4588*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 4589*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 4590*5e779b17SHawking Zhang 4591*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 4592*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4593*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 4594*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4595*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 4596*5e779b17SHawking Zhang #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 4597*5e779b17SHawking Zhang 4598*5e779b17SHawking Zhang 4599*5e779b17SHawking Zhang /* 4600*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 4601*5e779b17SHawking Zhang */ 4602*5e779b17SHawking Zhang 4603*5e779b17SHawking Zhang /*define for HEADER word*/ 4604*5e779b17SHawking Zhang /*define for op field*/ 4605*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 4606*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 4607*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 4608*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 4609*5e779b17SHawking Zhang 4610*5e779b17SHawking Zhang /*define for sub_op field*/ 4611*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 4612*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 4613*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 4614*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 4615*5e779b17SHawking Zhang 4616*5e779b17SHawking Zhang /*define for ea field*/ 4617*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 4618*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 4619*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 4620*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 4621*5e779b17SHawking Zhang 4622*5e779b17SHawking Zhang /*define for cache_policy field*/ 4623*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset 0 4624*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 4625*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift 24 4626*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift) 4627*5e779b17SHawking Zhang 4628*5e779b17SHawking Zhang /*define for cpv field*/ 4629*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset 0 4630*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask 0x00000001 4631*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift 28 4632*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift) 4633*5e779b17SHawking Zhang 4634*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 4635*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4636*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 4637*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4638*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 4639*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 4640*5e779b17SHawking Zhang 4641*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 4642*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4643*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 4644*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4645*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 4646*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 4647*5e779b17SHawking Zhang 4648*5e779b17SHawking Zhang /*define for START_PAGE word*/ 4649*5e779b17SHawking Zhang /*define for addr_31_4 field*/ 4650*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 4651*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 4652*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 4653*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 4654*5e779b17SHawking Zhang 4655*5e779b17SHawking Zhang /*define for PAGE_NUM word*/ 4656*5e779b17SHawking Zhang /*define for page_num_31_0 field*/ 4657*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 4658*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 4659*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 4660*5e779b17SHawking Zhang #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 4661*5e779b17SHawking Zhang 4662*5e779b17SHawking Zhang 4663*5e779b17SHawking Zhang /* 4664*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 4665*5e779b17SHawking Zhang */ 4666*5e779b17SHawking Zhang 4667*5e779b17SHawking Zhang /*define for HEADER word*/ 4668*5e779b17SHawking Zhang /*define for op field*/ 4669*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 4670*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 4671*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 4672*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 4673*5e779b17SHawking Zhang 4674*5e779b17SHawking Zhang /*define for sub_op field*/ 4675*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 4676*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 4677*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 4678*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 4679*5e779b17SHawking Zhang 4680*5e779b17SHawking Zhang /*define for cache_policy field*/ 4681*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset 0 4682*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask 0x00000007 4683*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift 24 4684*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift) 4685*5e779b17SHawking Zhang 4686*5e779b17SHawking Zhang /*define for cpv field*/ 4687*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset 0 4688*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask 0x00000001 4689*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift 28 4690*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift) 4691*5e779b17SHawking Zhang 4692*5e779b17SHawking Zhang /*define for mode field*/ 4693*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 4694*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 4695*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 4696*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 4697*5e779b17SHawking Zhang 4698*5e779b17SHawking Zhang /*define for PATTERN word*/ 4699*5e779b17SHawking Zhang /*define for pattern field*/ 4700*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 4701*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 4702*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 4703*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 4704*5e779b17SHawking Zhang 4705*5e779b17SHawking Zhang /*define for CMP0_ADDR_START_LO word*/ 4706*5e779b17SHawking Zhang /*define for cmp0_start_31_0 field*/ 4707*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 4708*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 4709*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 4710*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 4711*5e779b17SHawking Zhang 4712*5e779b17SHawking Zhang /*define for CMP0_ADDR_START_HI word*/ 4713*5e779b17SHawking Zhang /*define for cmp0_start_63_32 field*/ 4714*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 4715*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 4716*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 4717*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 4718*5e779b17SHawking Zhang 4719*5e779b17SHawking Zhang /*define for CMP0_ADDR_END_LO word*/ 4720*5e779b17SHawking Zhang /*define for cmp0_end_31_0 field*/ 4721*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset 4 4722*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask 0xFFFFFFFF 4723*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift 0 4724*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift) 4725*5e779b17SHawking Zhang 4726*5e779b17SHawking Zhang /*define for CMP0_ADDR_END_HI word*/ 4727*5e779b17SHawking Zhang /*define for cmp0_end_63_32 field*/ 4728*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset 5 4729*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask 0xFFFFFFFF 4730*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift 0 4731*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift) 4732*5e779b17SHawking Zhang 4733*5e779b17SHawking Zhang /*define for CMP1_ADDR_START_LO word*/ 4734*5e779b17SHawking Zhang /*define for cmp1_start_31_0 field*/ 4735*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 4736*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 4737*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 4738*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 4739*5e779b17SHawking Zhang 4740*5e779b17SHawking Zhang /*define for CMP1_ADDR_START_HI word*/ 4741*5e779b17SHawking Zhang /*define for cmp1_start_63_32 field*/ 4742*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 4743*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 4744*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 4745*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 4746*5e779b17SHawking Zhang 4747*5e779b17SHawking Zhang /*define for CMP1_ADDR_END_LO word*/ 4748*5e779b17SHawking Zhang /*define for cmp1_end_31_0 field*/ 4749*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 4750*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 4751*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 4752*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 4753*5e779b17SHawking Zhang 4754*5e779b17SHawking Zhang /*define for CMP1_ADDR_END_HI word*/ 4755*5e779b17SHawking Zhang /*define for cmp1_end_63_32 field*/ 4756*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 4757*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 4758*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 4759*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 4760*5e779b17SHawking Zhang 4761*5e779b17SHawking Zhang /*define for REC_ADDR_LO word*/ 4762*5e779b17SHawking Zhang /*define for rec_31_0 field*/ 4763*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 4764*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 4765*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 4766*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 4767*5e779b17SHawking Zhang 4768*5e779b17SHawking Zhang /*define for REC_ADDR_HI word*/ 4769*5e779b17SHawking Zhang /*define for rec_63_32 field*/ 4770*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 4771*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 4772*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 4773*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 4774*5e779b17SHawking Zhang 4775*5e779b17SHawking Zhang /*define for RESERVED word*/ 4776*5e779b17SHawking Zhang /*define for reserved field*/ 4777*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 4778*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 4779*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 4780*5e779b17SHawking Zhang #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 4781*5e779b17SHawking Zhang 4782*5e779b17SHawking Zhang 4783*5e779b17SHawking Zhang /* 4784*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_ATOMIC packet 4785*5e779b17SHawking Zhang */ 4786*5e779b17SHawking Zhang 4787*5e779b17SHawking Zhang /*define for HEADER word*/ 4788*5e779b17SHawking Zhang /*define for op field*/ 4789*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 4790*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 4791*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 4792*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 4793*5e779b17SHawking Zhang 4794*5e779b17SHawking Zhang /*define for loop field*/ 4795*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 4796*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 4797*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 4798*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 4799*5e779b17SHawking Zhang 4800*5e779b17SHawking Zhang /*define for tmz field*/ 4801*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 4802*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 4803*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 4804*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 4805*5e779b17SHawking Zhang 4806*5e779b17SHawking Zhang /*define for cache_policy field*/ 4807*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_cache_policy_offset 0 4808*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_cache_policy_mask 0x00000007 4809*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_cache_policy_shift 20 4810*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cache_policy_mask) << SDMA_PKT_ATOMIC_HEADER_cache_policy_shift) 4811*5e779b17SHawking Zhang 4812*5e779b17SHawking Zhang /*define for cpv field*/ 4813*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_cpv_offset 0 4814*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_cpv_mask 0x00000001 4815*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_cpv_shift 24 4816*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_CPV(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cpv_mask) << SDMA_PKT_ATOMIC_HEADER_cpv_shift) 4817*5e779b17SHawking Zhang 4818*5e779b17SHawking Zhang /*define for atomic_op field*/ 4819*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 4820*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 4821*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 4822*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 4823*5e779b17SHawking Zhang 4824*5e779b17SHawking Zhang /*define for ADDR_LO word*/ 4825*5e779b17SHawking Zhang /*define for addr_31_0 field*/ 4826*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 4827*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4828*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 4829*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 4830*5e779b17SHawking Zhang 4831*5e779b17SHawking Zhang /*define for ADDR_HI word*/ 4832*5e779b17SHawking Zhang /*define for addr_63_32 field*/ 4833*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 4834*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4835*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 4836*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 4837*5e779b17SHawking Zhang 4838*5e779b17SHawking Zhang /*define for SRC_DATA_LO word*/ 4839*5e779b17SHawking Zhang /*define for src_data_31_0 field*/ 4840*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 4841*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 4842*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 4843*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 4844*5e779b17SHawking Zhang 4845*5e779b17SHawking Zhang /*define for SRC_DATA_HI word*/ 4846*5e779b17SHawking Zhang /*define for src_data_63_32 field*/ 4847*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 4848*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 4849*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 4850*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 4851*5e779b17SHawking Zhang 4852*5e779b17SHawking Zhang /*define for CMP_DATA_LO word*/ 4853*5e779b17SHawking Zhang /*define for cmp_data_31_0 field*/ 4854*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 4855*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 4856*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 4857*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 4858*5e779b17SHawking Zhang 4859*5e779b17SHawking Zhang /*define for CMP_DATA_HI word*/ 4860*5e779b17SHawking Zhang /*define for cmp_data_63_32 field*/ 4861*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 4862*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 4863*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 4864*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 4865*5e779b17SHawking Zhang 4866*5e779b17SHawking Zhang /*define for LOOP_INTERVAL word*/ 4867*5e779b17SHawking Zhang /*define for loop_interval field*/ 4868*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 4869*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 4870*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 4871*5e779b17SHawking Zhang #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 4872*5e779b17SHawking Zhang 4873*5e779b17SHawking Zhang 4874*5e779b17SHawking Zhang /* 4875*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 4876*5e779b17SHawking Zhang */ 4877*5e779b17SHawking Zhang 4878*5e779b17SHawking Zhang /*define for HEADER word*/ 4879*5e779b17SHawking Zhang /*define for op field*/ 4880*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 4881*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 4882*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 4883*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 4884*5e779b17SHawking Zhang 4885*5e779b17SHawking Zhang /*define for sub_op field*/ 4886*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 4887*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 4888*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 4889*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 4890*5e779b17SHawking Zhang 4891*5e779b17SHawking Zhang /*define for INIT_DATA_LO word*/ 4892*5e779b17SHawking Zhang /*define for init_data_31_0 field*/ 4893*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 4894*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 4895*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 4896*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 4897*5e779b17SHawking Zhang 4898*5e779b17SHawking Zhang /*define for INIT_DATA_HI word*/ 4899*5e779b17SHawking Zhang /*define for init_data_63_32 field*/ 4900*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 4901*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 4902*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 4903*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 4904*5e779b17SHawking Zhang 4905*5e779b17SHawking Zhang 4906*5e779b17SHawking Zhang /* 4907*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 4908*5e779b17SHawking Zhang */ 4909*5e779b17SHawking Zhang 4910*5e779b17SHawking Zhang /*define for HEADER word*/ 4911*5e779b17SHawking Zhang /*define for op field*/ 4912*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 4913*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 4914*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 4915*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 4916*5e779b17SHawking Zhang 4917*5e779b17SHawking Zhang /*define for sub_op field*/ 4918*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 4919*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 4920*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 4921*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 4922*5e779b17SHawking Zhang 4923*5e779b17SHawking Zhang /*define for l2_policy field*/ 4924*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset 0 4925*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask 0x00000003 4926*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift 24 4927*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift) 4928*5e779b17SHawking Zhang 4929*5e779b17SHawking Zhang /*define for llc_policy field*/ 4930*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset 0 4931*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask 0x00000001 4932*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift 26 4933*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift) 4934*5e779b17SHawking Zhang 4935*5e779b17SHawking Zhang /*define for cpv field*/ 4936*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset 0 4937*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask 0x00000001 4938*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift 28 4939*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift) 4940*5e779b17SHawking Zhang 4941*5e779b17SHawking Zhang /*define for WRITE_ADDR_LO word*/ 4942*5e779b17SHawking Zhang /*define for write_addr_31_3 field*/ 4943*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 4944*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4945*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 4946*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 4947*5e779b17SHawking Zhang 4948*5e779b17SHawking Zhang /*define for WRITE_ADDR_HI word*/ 4949*5e779b17SHawking Zhang /*define for write_addr_63_32 field*/ 4950*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 4951*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 4952*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 4953*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 4954*5e779b17SHawking Zhang 4955*5e779b17SHawking Zhang 4956*5e779b17SHawking Zhang /* 4957*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 4958*5e779b17SHawking Zhang */ 4959*5e779b17SHawking Zhang 4960*5e779b17SHawking Zhang /*define for HEADER word*/ 4961*5e779b17SHawking Zhang /*define for op field*/ 4962*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 4963*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 4964*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 4965*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 4966*5e779b17SHawking Zhang 4967*5e779b17SHawking Zhang /*define for sub_op field*/ 4968*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 4969*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 4970*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 4971*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 4972*5e779b17SHawking Zhang 4973*5e779b17SHawking Zhang /*define for l2_policy field*/ 4974*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset 0 4975*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask 0x00000003 4976*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift 24 4977*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift) 4978*5e779b17SHawking Zhang 4979*5e779b17SHawking Zhang /*define for llc_policy field*/ 4980*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset 0 4981*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask 0x00000001 4982*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift 26 4983*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift) 4984*5e779b17SHawking Zhang 4985*5e779b17SHawking Zhang /*define for cpv field*/ 4986*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset 0 4987*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask 0x00000001 4988*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift 28 4989*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift) 4990*5e779b17SHawking Zhang 4991*5e779b17SHawking Zhang /*define for WRITE_ADDR_LO word*/ 4992*5e779b17SHawking Zhang /*define for write_addr_31_3 field*/ 4993*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 4994*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4995*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 4996*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 4997*5e779b17SHawking Zhang 4998*5e779b17SHawking Zhang /*define for WRITE_ADDR_HI word*/ 4999*5e779b17SHawking Zhang /*define for write_addr_63_32 field*/ 5000*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 5001*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 5002*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 5003*5e779b17SHawking Zhang #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 5004*5e779b17SHawking Zhang 5005*5e779b17SHawking Zhang 5006*5e779b17SHawking Zhang /* 5007*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_TRAP packet 5008*5e779b17SHawking Zhang */ 5009*5e779b17SHawking Zhang 5010*5e779b17SHawking Zhang /*define for HEADER word*/ 5011*5e779b17SHawking Zhang /*define for op field*/ 5012*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_op_offset 0 5013*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 5014*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_op_shift 0 5015*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 5016*5e779b17SHawking Zhang 5017*5e779b17SHawking Zhang /*define for sub_op field*/ 5018*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 5019*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 5020*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 5021*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 5022*5e779b17SHawking Zhang 5023*5e779b17SHawking Zhang /*define for INT_CONTEXT word*/ 5024*5e779b17SHawking Zhang /*define for int_context field*/ 5025*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 5026*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 5027*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 5028*5e779b17SHawking Zhang #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 5029*5e779b17SHawking Zhang 5030*5e779b17SHawking Zhang 5031*5e779b17SHawking Zhang /* 5032*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_DUMMY_TRAP packet 5033*5e779b17SHawking Zhang */ 5034*5e779b17SHawking Zhang 5035*5e779b17SHawking Zhang /*define for HEADER word*/ 5036*5e779b17SHawking Zhang /*define for op field*/ 5037*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 5038*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 5039*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 5040*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 5041*5e779b17SHawking Zhang 5042*5e779b17SHawking Zhang /*define for sub_op field*/ 5043*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 5044*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 5045*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 5046*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 5047*5e779b17SHawking Zhang 5048*5e779b17SHawking Zhang /*define for INT_CONTEXT word*/ 5049*5e779b17SHawking Zhang /*define for int_context field*/ 5050*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 5051*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 5052*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 5053*5e779b17SHawking Zhang #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 5054*5e779b17SHawking Zhang 5055*5e779b17SHawking Zhang 5056*5e779b17SHawking Zhang /* 5057*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_GPUVM_INV packet 5058*5e779b17SHawking Zhang */ 5059*5e779b17SHawking Zhang 5060*5e779b17SHawking Zhang /*define for HEADER word*/ 5061*5e779b17SHawking Zhang /*define for op field*/ 5062*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 5063*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF 5064*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 5065*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) 5066*5e779b17SHawking Zhang 5067*5e779b17SHawking Zhang /*define for sub_op field*/ 5068*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 5069*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF 5070*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 5071*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) 5072*5e779b17SHawking Zhang 5073*5e779b17SHawking Zhang /*define for PAYLOAD1 word*/ 5074*5e779b17SHawking Zhang /*define for per_vmid_inv_req field*/ 5075*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 5076*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF 5077*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 5078*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) 5079*5e779b17SHawking Zhang 5080*5e779b17SHawking Zhang /*define for flush_type field*/ 5081*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 5082*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 5083*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 5084*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) 5085*5e779b17SHawking Zhang 5086*5e779b17SHawking Zhang /*define for l2_ptes field*/ 5087*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 5088*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 5089*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 5090*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) 5091*5e779b17SHawking Zhang 5092*5e779b17SHawking Zhang /*define for l2_pde0 field*/ 5093*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 5094*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 5095*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 5096*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) 5097*5e779b17SHawking Zhang 5098*5e779b17SHawking Zhang /*define for l2_pde1 field*/ 5099*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 5100*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 5101*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 5102*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) 5103*5e779b17SHawking Zhang 5104*5e779b17SHawking Zhang /*define for l2_pde2 field*/ 5105*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 5106*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 5107*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 5108*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) 5109*5e779b17SHawking Zhang 5110*5e779b17SHawking Zhang /*define for l1_ptes field*/ 5111*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 5112*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 5113*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 5114*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) 5115*5e779b17SHawking Zhang 5116*5e779b17SHawking Zhang /*define for clr_protection_fault_status_addr field*/ 5117*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 5118*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 5119*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 5120*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) 5121*5e779b17SHawking Zhang 5122*5e779b17SHawking Zhang /*define for log_request field*/ 5123*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 5124*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 5125*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 5126*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) 5127*5e779b17SHawking Zhang 5128*5e779b17SHawking Zhang /*define for four_kilobytes field*/ 5129*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 5130*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 5131*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 5132*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) 5133*5e779b17SHawking Zhang 5134*5e779b17SHawking Zhang /*define for PAYLOAD2 word*/ 5135*5e779b17SHawking Zhang /*define for s field*/ 5136*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 5137*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 5138*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 5139*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) 5140*5e779b17SHawking Zhang 5141*5e779b17SHawking Zhang /*define for page_va_42_12 field*/ 5142*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 5143*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF 5144*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 5145*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) 5146*5e779b17SHawking Zhang 5147*5e779b17SHawking Zhang /*define for PAYLOAD3 word*/ 5148*5e779b17SHawking Zhang /*define for page_va_47_43 field*/ 5149*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 5150*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F 5151*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 5152*5e779b17SHawking Zhang #define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) 5153*5e779b17SHawking Zhang 5154*5e779b17SHawking Zhang 5155*5e779b17SHawking Zhang /* 5156*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_GCR_REQ packet 5157*5e779b17SHawking Zhang */ 5158*5e779b17SHawking Zhang 5159*5e779b17SHawking Zhang /*define for HEADER word*/ 5160*5e779b17SHawking Zhang /*define for op field*/ 5161*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 5162*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF 5163*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 5164*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) 5165*5e779b17SHawking Zhang 5166*5e779b17SHawking Zhang /*define for sub_op field*/ 5167*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 5168*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF 5169*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 5170*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) 5171*5e779b17SHawking Zhang 5172*5e779b17SHawking Zhang /*define for PAYLOAD1 word*/ 5173*5e779b17SHawking Zhang /*define for base_va_31_7 field*/ 5174*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 5175*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF 5176*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 5177*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) 5178*5e779b17SHawking Zhang 5179*5e779b17SHawking Zhang /*define for PAYLOAD2 word*/ 5180*5e779b17SHawking Zhang /*define for base_va_47_32 field*/ 5181*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 5182*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF 5183*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 5184*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) 5185*5e779b17SHawking Zhang 5186*5e779b17SHawking Zhang /*define for gcr_control_15_0 field*/ 5187*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 5188*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF 5189*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 5190*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) 5191*5e779b17SHawking Zhang 5192*5e779b17SHawking Zhang /*define for PAYLOAD3 word*/ 5193*5e779b17SHawking Zhang /*define for gcr_control_18_16 field*/ 5194*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 5195*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 5196*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 5197*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) 5198*5e779b17SHawking Zhang 5199*5e779b17SHawking Zhang /*define for limit_va_31_7 field*/ 5200*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 5201*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF 5202*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 5203*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) 5204*5e779b17SHawking Zhang 5205*5e779b17SHawking Zhang /*define for PAYLOAD4 word*/ 5206*5e779b17SHawking Zhang /*define for limit_va_47_32 field*/ 5207*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 5208*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF 5209*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 5210*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) 5211*5e779b17SHawking Zhang 5212*5e779b17SHawking Zhang /*define for vmid field*/ 5213*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 5214*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F 5215*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 5216*5e779b17SHawking Zhang #define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) 5217*5e779b17SHawking Zhang 5218*5e779b17SHawking Zhang 5219*5e779b17SHawking Zhang /* 5220*5e779b17SHawking Zhang ** Definitions for SDMA_PKT_NOP packet 5221*5e779b17SHawking Zhang */ 5222*5e779b17SHawking Zhang 5223*5e779b17SHawking Zhang /*define for HEADER word*/ 5224*5e779b17SHawking Zhang /*define for op field*/ 5225*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_op_offset 0 5226*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 5227*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_op_shift 0 5228*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 5229*5e779b17SHawking Zhang 5230*5e779b17SHawking Zhang /*define for sub_op field*/ 5231*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 5232*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 5233*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 5234*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 5235*5e779b17SHawking Zhang 5236*5e779b17SHawking Zhang /*define for count field*/ 5237*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_count_offset 0 5238*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 5239*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_count_shift 16 5240*5e779b17SHawking Zhang #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 5241*5e779b17SHawking Zhang 5242*5e779b17SHawking Zhang /*define for DATA0 word*/ 5243*5e779b17SHawking Zhang /*define for data0 field*/ 5244*5e779b17SHawking Zhang #define SDMA_PKT_NOP_DATA0_data0_offset 1 5245*5e779b17SHawking Zhang #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 5246*5e779b17SHawking Zhang #define SDMA_PKT_NOP_DATA0_data0_shift 0 5247*5e779b17SHawking Zhang #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 5248*5e779b17SHawking Zhang 5249*5e779b17SHawking Zhang 5250*5e779b17SHawking Zhang /* 5251*5e779b17SHawking Zhang ** Definitions for SDMA_AQL_PKT_HEADER packet 5252*5e779b17SHawking Zhang */ 5253*5e779b17SHawking Zhang 5254*5e779b17SHawking Zhang /*define for HEADER word*/ 5255*5e779b17SHawking Zhang /*define for format field*/ 5256*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 5257*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 5258*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 5259*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 5260*5e779b17SHawking Zhang 5261*5e779b17SHawking Zhang /*define for barrier field*/ 5262*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 5263*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 5264*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 5265*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 5266*5e779b17SHawking Zhang 5267*5e779b17SHawking Zhang /*define for acquire_fence_scope field*/ 5268*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 5269*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 5270*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 5271*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 5272*5e779b17SHawking Zhang 5273*5e779b17SHawking Zhang /*define for release_fence_scope field*/ 5274*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 5275*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 5276*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 5277*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 5278*5e779b17SHawking Zhang 5279*5e779b17SHawking Zhang /*define for reserved field*/ 5280*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 5281*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 5282*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 5283*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 5284*5e779b17SHawking Zhang 5285*5e779b17SHawking Zhang /*define for op field*/ 5286*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 5287*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 5288*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 5289*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 5290*5e779b17SHawking Zhang 5291*5e779b17SHawking Zhang /*define for subop field*/ 5292*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 5293*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 5294*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 5295*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 5296*5e779b17SHawking Zhang 5297*5e779b17SHawking Zhang /*define for cpv field*/ 5298*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_cpv_offset 0 5299*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_cpv_mask 0x00000001 5300*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_cpv_shift 28 5301*5e779b17SHawking Zhang #define SDMA_AQL_PKT_HEADER_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_cpv_mask) << SDMA_AQL_PKT_HEADER_HEADER_cpv_shift) 5302*5e779b17SHawking Zhang 5303*5e779b17SHawking Zhang 5304*5e779b17SHawking Zhang /* 5305*5e779b17SHawking Zhang ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 5306*5e779b17SHawking Zhang */ 5307*5e779b17SHawking Zhang 5308*5e779b17SHawking Zhang /*define for HEADER word*/ 5309*5e779b17SHawking Zhang /*define for format field*/ 5310*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 5311*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 5312*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 5313*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 5314*5e779b17SHawking Zhang 5315*5e779b17SHawking Zhang /*define for barrier field*/ 5316*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 5317*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 5318*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 5319*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 5320*5e779b17SHawking Zhang 5321*5e779b17SHawking Zhang /*define for acquire_fence_scope field*/ 5322*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 5323*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 5324*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 5325*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 5326*5e779b17SHawking Zhang 5327*5e779b17SHawking Zhang /*define for release_fence_scope field*/ 5328*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 5329*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 5330*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 5331*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 5332*5e779b17SHawking Zhang 5333*5e779b17SHawking Zhang /*define for reserved field*/ 5334*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 5335*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 5336*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 5337*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 5338*5e779b17SHawking Zhang 5339*5e779b17SHawking Zhang /*define for op field*/ 5340*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 5341*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 5342*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 5343*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 5344*5e779b17SHawking Zhang 5345*5e779b17SHawking Zhang /*define for subop field*/ 5346*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 5347*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 5348*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 5349*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 5350*5e779b17SHawking Zhang 5351*5e779b17SHawking Zhang /*define for cpv field*/ 5352*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset 0 5353*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 5354*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift 28 5355*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift) 5356*5e779b17SHawking Zhang 5357*5e779b17SHawking Zhang /*define for RESERVED_DW1 word*/ 5358*5e779b17SHawking Zhang /*define for reserved_dw1 field*/ 5359*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 5360*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 5361*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 5362*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 5363*5e779b17SHawking Zhang 5364*5e779b17SHawking Zhang /*define for RETURN_ADDR_LO word*/ 5365*5e779b17SHawking Zhang /*define for return_addr_31_0 field*/ 5366*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 5367*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 5368*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 5369*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 5370*5e779b17SHawking Zhang 5371*5e779b17SHawking Zhang /*define for RETURN_ADDR_HI word*/ 5372*5e779b17SHawking Zhang /*define for return_addr_63_32 field*/ 5373*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 5374*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 5375*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 5376*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 5377*5e779b17SHawking Zhang 5378*5e779b17SHawking Zhang /*define for COUNT word*/ 5379*5e779b17SHawking Zhang /*define for count field*/ 5380*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 5381*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 5382*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 5383*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 5384*5e779b17SHawking Zhang 5385*5e779b17SHawking Zhang /*define for PARAMETER word*/ 5386*5e779b17SHawking Zhang /*define for dst_sw field*/ 5387*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 5388*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 5389*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 5390*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 5391*5e779b17SHawking Zhang 5392*5e779b17SHawking Zhang /*define for dst_cache_policy field*/ 5393*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 5 5394*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 5395*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 5396*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) 5397*5e779b17SHawking Zhang 5398*5e779b17SHawking Zhang /*define for src_sw field*/ 5399*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 5400*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 5401*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 5402*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 5403*5e779b17SHawking Zhang 5404*5e779b17SHawking Zhang /*define for src_cache_policy field*/ 5405*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 5 5406*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 5407*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 5408*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) 5409*5e779b17SHawking Zhang 5410*5e779b17SHawking Zhang /*define for SRC_ADDR_LO word*/ 5411*5e779b17SHawking Zhang /*define for src_addr_31_0 field*/ 5412*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 5413*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 5414*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 5415*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 5416*5e779b17SHawking Zhang 5417*5e779b17SHawking Zhang /*define for SRC_ADDR_HI word*/ 5418*5e779b17SHawking Zhang /*define for src_addr_63_32 field*/ 5419*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 5420*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 5421*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 5422*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 5423*5e779b17SHawking Zhang 5424*5e779b17SHawking Zhang /*define for DST_ADDR_LO word*/ 5425*5e779b17SHawking Zhang /*define for dst_addr_31_0 field*/ 5426*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 5427*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 5428*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 5429*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 5430*5e779b17SHawking Zhang 5431*5e779b17SHawking Zhang /*define for DST_ADDR_HI word*/ 5432*5e779b17SHawking Zhang /*define for dst_addr_63_32 field*/ 5433*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 5434*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 5435*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 5436*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 5437*5e779b17SHawking Zhang 5438*5e779b17SHawking Zhang /*define for RESERVED_DW10 word*/ 5439*5e779b17SHawking Zhang /*define for reserved_dw10 field*/ 5440*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 5441*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 5442*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 5443*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 5444*5e779b17SHawking Zhang 5445*5e779b17SHawking Zhang /*define for RESERVED_DW11 word*/ 5446*5e779b17SHawking Zhang /*define for reserved_dw11 field*/ 5447*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 5448*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 5449*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 5450*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 5451*5e779b17SHawking Zhang 5452*5e779b17SHawking Zhang /*define for RESERVED_DW12 word*/ 5453*5e779b17SHawking Zhang /*define for reserved_dw12 field*/ 5454*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 5455*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 5456*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 5457*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 5458*5e779b17SHawking Zhang 5459*5e779b17SHawking Zhang /*define for RESERVED_DW13 word*/ 5460*5e779b17SHawking Zhang /*define for reserved_dw13 field*/ 5461*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 5462*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 5463*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 5464*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 5465*5e779b17SHawking Zhang 5466*5e779b17SHawking Zhang /*define for COMPLETION_SIGNAL_LO word*/ 5467*5e779b17SHawking Zhang /*define for completion_signal_31_0 field*/ 5468*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 5469*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 5470*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 5471*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 5472*5e779b17SHawking Zhang 5473*5e779b17SHawking Zhang /*define for COMPLETION_SIGNAL_HI word*/ 5474*5e779b17SHawking Zhang /*define for completion_signal_63_32 field*/ 5475*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 5476*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 5477*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 5478*5e779b17SHawking Zhang #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 5479*5e779b17SHawking Zhang 5480*5e779b17SHawking Zhang 5481*5e779b17SHawking Zhang /* 5482*5e779b17SHawking Zhang ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 5483*5e779b17SHawking Zhang */ 5484*5e779b17SHawking Zhang 5485*5e779b17SHawking Zhang /*define for HEADER word*/ 5486*5e779b17SHawking Zhang /*define for format field*/ 5487*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 5488*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 5489*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 5490*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 5491*5e779b17SHawking Zhang 5492*5e779b17SHawking Zhang /*define for barrier field*/ 5493*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 5494*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 5495*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 5496*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 5497*5e779b17SHawking Zhang 5498*5e779b17SHawking Zhang /*define for acquire_fence_scope field*/ 5499*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 5500*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 5501*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 5502*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 5503*5e779b17SHawking Zhang 5504*5e779b17SHawking Zhang /*define for release_fence_scope field*/ 5505*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 5506*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 5507*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 5508*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 5509*5e779b17SHawking Zhang 5510*5e779b17SHawking Zhang /*define for reserved field*/ 5511*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 5512*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 5513*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 5514*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 5515*5e779b17SHawking Zhang 5516*5e779b17SHawking Zhang /*define for op field*/ 5517*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 5518*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 5519*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 5520*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 5521*5e779b17SHawking Zhang 5522*5e779b17SHawking Zhang /*define for subop field*/ 5523*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 5524*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 5525*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 5526*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 5527*5e779b17SHawking Zhang 5528*5e779b17SHawking Zhang /*define for cpv field*/ 5529*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset 0 5530*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask 0x00000001 5531*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift 28 5532*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift) 5533*5e779b17SHawking Zhang 5534*5e779b17SHawking Zhang /*define for RESERVED_DW1 word*/ 5535*5e779b17SHawking Zhang /*define for reserved_dw1 field*/ 5536*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 5537*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 5538*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 5539*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 5540*5e779b17SHawking Zhang 5541*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_0_LO word*/ 5542*5e779b17SHawking Zhang /*define for dependent_addr_0_31_0 field*/ 5543*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 5544*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 5545*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 5546*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 5547*5e779b17SHawking Zhang 5548*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_0_HI word*/ 5549*5e779b17SHawking Zhang /*define for dependent_addr_0_63_32 field*/ 5550*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 5551*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 5552*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 5553*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 5554*5e779b17SHawking Zhang 5555*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_1_LO word*/ 5556*5e779b17SHawking Zhang /*define for dependent_addr_1_31_0 field*/ 5557*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 5558*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 5559*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 5560*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 5561*5e779b17SHawking Zhang 5562*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_1_HI word*/ 5563*5e779b17SHawking Zhang /*define for dependent_addr_1_63_32 field*/ 5564*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 5565*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 5566*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 5567*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 5568*5e779b17SHawking Zhang 5569*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_2_LO word*/ 5570*5e779b17SHawking Zhang /*define for dependent_addr_2_31_0 field*/ 5571*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 5572*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 5573*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 5574*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 5575*5e779b17SHawking Zhang 5576*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_2_HI word*/ 5577*5e779b17SHawking Zhang /*define for dependent_addr_2_63_32 field*/ 5578*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 5579*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 5580*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 5581*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 5582*5e779b17SHawking Zhang 5583*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_3_LO word*/ 5584*5e779b17SHawking Zhang /*define for dependent_addr_3_31_0 field*/ 5585*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 5586*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 5587*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 5588*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 5589*5e779b17SHawking Zhang 5590*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_3_HI word*/ 5591*5e779b17SHawking Zhang /*define for dependent_addr_3_63_32 field*/ 5592*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 5593*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 5594*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 5595*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 5596*5e779b17SHawking Zhang 5597*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_4_LO word*/ 5598*5e779b17SHawking Zhang /*define for dependent_addr_4_31_0 field*/ 5599*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 5600*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 5601*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 5602*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 5603*5e779b17SHawking Zhang 5604*5e779b17SHawking Zhang /*define for DEPENDENT_ADDR_4_HI word*/ 5605*5e779b17SHawking Zhang /*define for dependent_addr_4_63_32 field*/ 5606*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 5607*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 5608*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 5609*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 5610*5e779b17SHawking Zhang 5611*5e779b17SHawking Zhang /*define for CACHE_POLICY word*/ 5612*5e779b17SHawking Zhang /*define for cache_policy0 field*/ 5613*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset 12 5614*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask 0x00000007 5615*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift 0 5616*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift) 5617*5e779b17SHawking Zhang 5618*5e779b17SHawking Zhang /*define for cache_policy1 field*/ 5619*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset 12 5620*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask 0x00000007 5621*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift 5 5622*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift) 5623*5e779b17SHawking Zhang 5624*5e779b17SHawking Zhang /*define for cache_policy2 field*/ 5625*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset 12 5626*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask 0x00000007 5627*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift 10 5628*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift) 5629*5e779b17SHawking Zhang 5630*5e779b17SHawking Zhang /*define for cache_policy3 field*/ 5631*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset 12 5632*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask 0x00000007 5633*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift 15 5634*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift) 5635*5e779b17SHawking Zhang 5636*5e779b17SHawking Zhang /*define for cache_policy4 field*/ 5637*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset 12 5638*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask 0x00000007 5639*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift 20 5640*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift) 5641*5e779b17SHawking Zhang 5642*5e779b17SHawking Zhang /*define for RESERVED_DW13 word*/ 5643*5e779b17SHawking Zhang /*define for reserved_dw13 field*/ 5644*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 5645*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 5646*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 5647*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 5648*5e779b17SHawking Zhang 5649*5e779b17SHawking Zhang /*define for COMPLETION_SIGNAL_LO word*/ 5650*5e779b17SHawking Zhang /*define for completion_signal_31_0 field*/ 5651*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 5652*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 5653*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 5654*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 5655*5e779b17SHawking Zhang 5656*5e779b17SHawking Zhang /*define for COMPLETION_SIGNAL_HI word*/ 5657*5e779b17SHawking Zhang /*define for completion_signal_63_32 field*/ 5658*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 5659*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 5660*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 5661*5e779b17SHawking Zhang #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 5662*5e779b17SHawking Zhang 5663*5e779b17SHawking Zhang 5664*5e779b17SHawking Zhang #endif /* __SDMA_V6_0_0_PKT_OPEN_H_ */ 5665