Lines Matching +full:0 +full:x0007ffff
24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
50 0
70 writel(0x003f0000, &noc_fw_ocram_base->region0); in socfpga_init_security_policies()
71 writel(0x1, &noc_fw_ocram_base->enable); in socfpga_init_security_policies()
74 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); in socfpga_init_security_policies()
75 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS); in socfpga_init_security_policies()
78 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST); in socfpga_init_security_policies()
81 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); in socfpga_init_security_policies()
82 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); in socfpga_init_security_policies()
84 writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); in socfpga_init_security_policies()
89 /* Configure the L2 controller to make SDRAM start at 0 */ in socfpga_sdram_remap_zero()
90 writel(0x1, &pl310->pl310_addr_filter_start); in socfpga_sdram_remap_zero()
97 socfpga_fpga_add(&altera_fpga[0]); in arch_early_init_r()
99 return 0; in arch_early_init_r()
114 return 0; in print_cpuinfo()