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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr600_mt47h32m16_37e_166_cl4_sync.c12 0x03030301,
13 0x03030303,
14 0x01000000,
15 0x00000101,
16 0x00000001,
17 0x01000000,
18 0x00010001,
19 0x00000100,
20 0x00010001,
21 0x00000003,
[all …]
H A Dspr600_mt47h128m8_3_266_cl5_async.c12 0x00000001,
13 0x00000000,
14 0x01000000,
15 0x00000101,
16 0x00000001,
17 0x01000000,
18 0x00010001,
19 0x00000100,
20 0x00010001,
21 0x00000003,
[all …]
H A Dspr600_mt47h64m16_3_333_cl5_psync.c13 0x00000001,
14 0x00000000,
16 0x02020201,
17 0x02020202,
19 0x01000000,
20 0x00000101,
21 0x00000101,
22 0x01000000,
23 0x00010001,
24 0x00000100,
[all …]
H A Dspr600_mt47h32m16_333_cl5_psync.c13 0x00000001,
14 0x00000000,
16 0x02020201,
17 0x02020202,
19 0x01000000,
20 0x00000101,
21 0x00000101,
22 0x01000000,
23 0x00010001,
24 0x00000100,
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgt215.c38 const u32 soff = ior->id * 0x800; in gt215_sor_hda_eld()
41 for (i = 0; i < size; i++) in gt215_sor_hda_eld()
42 nvkm_wr32(device, 0x61c440 + soff, (i << 8) | data[i]); in gt215_sor_hda_eld()
43 for (; i < 0x60; i++) in gt215_sor_hda_eld()
44 nvkm_wr32(device, 0x61c440 + soff, (i << 8)); in gt215_sor_hda_eld()
45 nvkm_mask(device, 0x61c448 + soff, 0x80000002, 0x80000002); in gt215_sor_hda_eld()
52 u32 data = 0x80000000; in gt215_sor_hda_hpd()
53 u32 mask = 0x80000001; in gt215_sor_hda_hpd()
55 data |= 0x00000001; in gt215_sor_hda_hpd()
57 mask |= 0x00000002; in gt215_sor_hda_hpd()
[all …]
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h103 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
104 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
109 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
110 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
111 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
112 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
113 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
114 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
115 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
116 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
[all …]
/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
31 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
40 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
72 #define MSGDMA_DESC_TX_STRIDE (0x00010001)
73 #define MSGDMA_DESC_RX_STRIDE (0x00010001)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
92 #define MSGDMA_CSR_STAT_BUSY BIT(0)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
[all …]
/openbmc/u-boot/drivers/net/
H A Daltera_tse.h17 #define ALT_SGDMA 0
34 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
122 #define MSGDMA_DESC_TX_STRIDE 0x00010001
123 #define MSGDMA_DESC_RX_STRIDE 0x00010001
130 u32 resp_fill_level; /* bit 15:0 */
136 #define MSGDMA_CSR_STAT_BUSY BIT(0)
138 #define MSGDMA_CSR_STAT_MASK 0x3FF
150 #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
181 u32 reserved1[0x29];
187 u32 reserved2[0x44];
[all …]
/openbmc/linux/sound/soc/amd/rpl/
H A Drpl_acp6x.h10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP6x_PHY_BASE_ADDRESS 0x1240000
13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
15 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
17 #define ACP_POWERED_ON 0
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r2_addu_ph.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010001; in main()
12 result = 0x01000100; in main()
14 ("addu.ph %0, %1, %2\n\t" in main()
20 rs = 0xFFFF1111; in main()
21 rt = 0x00020001; in main()
22 result = 0x00011112; in main()
24 ("addu.ph %0, %2, %3\n\t" in main()
30 assert(((dsp >> 20) & 0x01) == 1); in main()
32 return 0; in main()
H A Dtest_dsp_r1_addu_qb.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010001; in main()
12 result = 0x00000000; in main()
14 ("addu.qb %0, %2, %3\n\t" in main()
20 assert(((dsp >> 20) & 0x01) == 1); in main()
22 rs = 0xFFFF1111; in main()
23 rt = 0x00020001; in main()
24 result = 0xFF011112; in main()
26 ("addu.qb %0, %2, %3\n\t" in main()
32 assert(((dsp >> 20) & 0x01) == 1); in main()
[all …]
/openbmc/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
/openbmc/qemu/hw/audio/
H A Dhda-codec-common.h28 #define QEMU_HDA_ID_OUTPUT ((QEMU_HDA_ID_VENDOR << 16) | 0x12)
29 #define QEMU_HDA_ID_DUPLEX ((QEMU_HDA_ID_VENDOR << 16) | 0x22)
30 #define QEMU_HDA_ID_MICRO ((QEMU_HDA_ID_VENDOR << 16) | 0x32)
37 #define QEMU_HDA_ID_OUTPUT ((QEMU_HDA_ID_VENDOR << 16) | 0x11)
38 #define QEMU_HDA_ID_DUPLEX ((QEMU_HDA_ID_VENDOR << 16) | 0x21)
39 #define QEMU_HDA_ID_MICRO ((QEMU_HDA_ID_VENDOR << 16) | 0x31)
146 .val = 0x00100101,
149 .val = 0x00010001,
163 .val = 0x00020002,
178 .val = 0,
[all …]
/openbmc/u-boot/board/udoo/
H A Dudoo_spl.c29 * 0x30 == 40 Ohm
30 * 0x28 == 48 Ohm
32 #define IMX6DQ_DRIVE_STRENGTH 0x30
33 #define IMX6SDL_DRIVE_STRENGTH 0x28
44 .dram_sdba2 = 0x00000000,
67 .grp_ddr_type = 0x000c0000,
68 .grp_ddrmode_ctl = 0x00020000,
69 .grp_ddrpke = 0x00000000,
72 .grp_ddrmode = 0x00020000,
92 .dram_sdba2 = 0x00000000,
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/openbmc/linux/sound/soc/amd/renoir/
H A Drn_acp3x.h11 #define ACP_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_REG_START 0x1240000
13 #define ACP_REG_END 0x1250200
15 #define ACP_DEVICE_ID 0x15E2
16 #define ACP_POWER_ON 0x00
17 #define ACP_POWER_ON_IN_PROGRESS 0x01
18 #define ACP_POWER_OFF 0x02
19 #define ACP_POWER_OFF_IN_PROGRESS 0x03
20 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
22 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
17 0x1d191519
18 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-2GB-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
18 0x1d191519
19 0x14040808
[all …]
/openbmc/linux/sound/soc/amd/yc/
H A Dacp6x.h10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP6x_PHY_BASE_ADDRESS 0x1240000
12 #define ACP6x_REG_START 0x1240000
13 #define ACP6x_REG_END 0x1250200
17 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
19 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
21 #define ACP_POWERED_ON 0
26 #define ACP_ERROR_MASK 0x20000000
27 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
28 #define PDM_DMA_STAT 0x10
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]

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