Lines Matching +full:0 +full:x00010001

17 #define ALT_SGDMA	0
34 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK		BIT(0)
122 #define MSGDMA_DESC_TX_STRIDE		0x00010001
123 #define MSGDMA_DESC_RX_STRIDE		0x00010001
130 	u32 resp_fill_level;	/* bit 15:0 */
136 #define MSGDMA_CSR_STAT_BUSY			BIT(0)
138 #define MSGDMA_CSR_STAT_MASK			0x3FF
150 #define ALTERA_TSE_CMD_TX_ENA_MSK		BIT(0)
181 	u32 reserved1[0x29];
187 	u32 reserved2[0x44];
189 	/*Registers 0 to 31 within PHY device 0/1 */
190 	u32 mdio_phy0[0x20];
191 	u32 mdio_phy1[0x20];
203 	u32 reserved3[0x38];