Lines Matching +full:0 +full:x00010001
75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
298 0, 0,
300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
302 0, 0,
304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
306 0, 0,
308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
310 0, 0,
312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
314 0, 0,
316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
318 0, 0,
320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
322 0, 0,
324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
326 0, 0,
328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
330 0, 0,
332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
334 0, 0,
336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
338 0, 0,
340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
342 0, 0,
344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
346 0, 0,
348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
350 0, 0,
352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
354 0, 0,
356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
358 0, 0,
360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
362 0, 0,
364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
366 0, 0,
368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
370 0, 0,
372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
374 0, 0,
376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
378 0, 0,
380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
382 0, 0,
384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
386 0, 0,
388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
390 0, 0,
398 case 0: in sdma_v4_0_get_reg_offset()
399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
417 return 0; in sdma_v4_0_get_reg_offset()
423 case 0: in sdma_v4_0_seq_to_irq_id()
449 return 0; in sdma_v4_0_irq_id_to_seq()
472 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_golden_registers()
473 case IP_VERSION(4, 0, 0): in sdma_v4_0_init_golden_registers()
481 case IP_VERSION(4, 0, 1): in sdma_v4_0_init_golden_registers()
489 case IP_VERSION(4, 2, 0): in sdma_v4_0_init_golden_registers()
505 case IP_VERSION(4, 4, 0): in sdma_v4_0_init_golden_registers()
510 case IP_VERSION(4, 1, 0): in sdma_v4_0_init_golden_registers()
542 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_setup_ulv()
543 case IP_VERSION(4, 0, 0): in sdma_v4_0_setup_ulv()
544 if (adev->pdev->device == 0x6860) in sdma_v4_0_setup_ulv()
547 case IP_VERSION(4, 2, 0): in sdma_v4_0_setup_ulv()
548 if (adev->pdev->device == 0x66a1) in sdma_v4_0_setup_ulv()
555 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_setup_ulv()
559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); in sdma_v4_0_setup_ulv()
571 * Returns 0 on success, error on failure.
580 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
581 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || in sdma_v4_0_init_microcode()
582 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { in sdma_v4_0_init_microcode()
585 ret = amdgpu_sdma_init_microcode(adev, 0, true); in sdma_v4_0_init_microcode()
611 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); in sdma_v4_0_ring_get_rptr()
630 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_0_ring_get_wptr()
635 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", in sdma_v4_0_ring_get_wptr()
658 "wptr_offs == 0x%08x " in sdma_v4_0_ring_set_wptr()
659 "lower_32_bits(ring->wptr << 2) == 0x%08x " in sdma_v4_0_ring_set_wptr()
660 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", in sdma_v4_0_ring_set_wptr()
666 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", in sdma_v4_0_ring_set_wptr()
671 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " in sdma_v4_0_ring_set_wptr()
672 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", in sdma_v4_0_ring_set_wptr()
740 for (i = 0; i < count; i++) in sdma_v4_0_ring_insert_nop()
741 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_0_ring_insert_nop()
769 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); in sdma_v4_0_ring_emit_ib()
771 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
774 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
775 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
800 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | in sdma_v4_0_wait_reg_mem()
814 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush()
819 sdma_v4_0_wait_reg_mem(ring, 0, 1, in sdma_v4_0_ring_emit_hdp_flush()
844 BUG_ON(addr & 0x3); in sdma_v4_0_ring_emit_fence()
854 BUG_ON(addr & 0x3); in sdma_v4_0_ring_emit_fence()
862 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); in sdma_v4_0_ring_emit_fence()
880 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_gfx_enable()
882 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0); in sdma_v4_0_gfx_enable()
885 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0); in sdma_v4_0_gfx_enable()
916 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_page_stop()
919 RB_ENABLE, 0); in sdma_v4_0_page_stop()
923 IB_ENABLE, 0); in sdma_v4_0_page_stop()
938 u32 f32_cntl, phase_quantum = 0; in sdma_v4_0_ctx_switch_enable()
943 unsigned unit = 0; in sdma_v4_0_ctx_switch_enable()
965 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_ctx_switch_enable()
968 AUTO_CTXSW_ENABLE, enable ? 1 : 0); in sdma_v4_0_ctx_switch_enable()
981 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && in sdma_v4_0_ctx_switch_enable()
985 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); in sdma_v4_0_ctx_switch_enable()
1010 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_enable()
1012 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
1041 * Returns 0 for success, error for failure.
1056 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); in sdma_v4_0_gfx_resume()
1057 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); in sdma_v4_0_gfx_resume()
1058 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); in sdma_v4_0_gfx_resume()
1059 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); in sdma_v4_0_gfx_resume()
1063 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); in sdma_v4_0_gfx_resume()
1065 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v4_0_gfx_resume()
1073 ring->wptr = 0; in sdma_v4_0_gfx_resume()
1091 /* set minor_ptr_update to 0 after wptr programed */ in sdma_v4_0_gfx_resume()
1092 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); in sdma_v4_0_gfx_resume()
1103 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); in sdma_v4_0_gfx_resume()
1126 * Returns 0 for success, error for failure.
1141 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); in sdma_v4_0_page_resume()
1142 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); in sdma_v4_0_page_resume()
1143 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); in sdma_v4_0_page_resume()
1144 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); in sdma_v4_0_page_resume()
1148 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); in sdma_v4_0_page_resume()
1150 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v4_0_page_resume()
1158 ring->wptr = 0; in sdma_v4_0_page_resume()
1177 /* set minor_ptr_update to 0 after wptr programed */ in sdma_v4_0_page_resume()
1178 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); in sdma_v4_0_page_resume()
1189 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); in sdma_v4_0_page_resume()
1212 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
1216 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
1219 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
1222 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
1231 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1234 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
1237 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_init_power_gating()
1240 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_init_power_gating()
1243 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1250 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
1258 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_pg()
1259 case IP_VERSION(4, 1, 0): in sdma_v4_0_init_pg()
1276 * Returns 0 for success, error for failure.
1282 return 0; in sdma_v4_0_rlc_resume()
1291 * Returns 0 for success, -EINVAL if the ucode is not available.
1303 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_load_microcode()
1315 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); in sdma_v4_0_load_microcode()
1317 for (j = 0; j < fw_size; j++) in sdma_v4_0_load_microcode()
1325 return 0; in sdma_v4_0_load_microcode()
1334 * Returns 0 for success, error for failure.
1339 int i, r = 0; in sdma_v4_0_start()
1359 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_start()
1362 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); in sdma_v4_0_start()
1375 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v4_0_start()
1389 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_start()
1421 * Returns 0 for success, error for failure.
1437 tmp = 0xCAFEDEAD; in sdma_v4_0_ring_test_ring()
1448 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v4_0_ring_test_ring()
1449 amdgpu_ring_write(ring, 0xDEADBEEF); in sdma_v4_0_ring_test_ring()
1452 for (i = 0; i < adev->usec_timeout; i++) { in sdma_v4_0_ring_test_ring()
1454 if (tmp == 0xDEADBEEF) in sdma_v4_0_ring_test_ring()
1474 * Returns 0 on success, error on failure.
1483 u32 tmp = 0; in sdma_v4_0_ring_test_ib()
1491 tmp = 0xCAFEDEAD; in sdma_v4_0_ring_test_ib()
1493 memset(&ib, 0, sizeof(ib)); in sdma_v4_0_ring_test_ib()
1499 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v4_0_ring_test_ib()
1503 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v4_0_ring_test_ib()
1504 ib.ptr[4] = 0xDEADBEEF; in sdma_v4_0_ring_test_ib()
1515 if (r == 0) { in sdma_v4_0_ring_test_ib()
1518 } else if (r < 0) { in sdma_v4_0_ring_test_ib()
1522 if (tmp == 0xDEADBEEF) in sdma_v4_0_ring_test_ib()
1523 r = 0; in sdma_v4_0_ring_test_ib()
1555 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v4_0_vm_copy_pte()
1585 for (; ndw > 0; ndw -= 2) { in sdma_v4_0_vm_write_pte()
1618 ib->ptr[ib->length_dw++] = 0; in sdma_v4_0_vm_set_pte_pde()
1635 for (i = 0; i < pad_count; i++) in sdma_v4_0_ring_pad_ib()
1636 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_0_ring_pad_ib()
1659 sdma_v4_0_wait_reg_mem(ring, 1, 0, in sdma_v4_0_ring_emit_pipeline_sync()
1660 addr & 0xfffffffc, in sdma_v4_0_ring_emit_pipeline_sync()
1661 upper_32_bits(addr) & 0xffffffff, in sdma_v4_0_ring_emit_pipeline_sync()
1662 seq, 0xffffffff, 4); in sdma_v4_0_ring_emit_pipeline_sync()
1686 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); in sdma_v4_0_ring_emit_wreg()
1694 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); in sdma_v4_0_ring_emit_reg_wait()
1699 uint fw_version = adev->sdma.instance[0].fw_version; in sdma_v4_0_fw_support_paging_queue()
1701 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_fw_support_paging_queue()
1702 case IP_VERSION(4, 0, 0): in sdma_v4_0_fw_support_paging_queue()
1704 case IP_VERSION(4, 0, 1): in sdma_v4_0_fw_support_paging_queue()
1707 case IP_VERSION(4, 2, 0): in sdma_v4_0_fw_support_paging_queue()
1726 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && in sdma_v4_0_early_init()
1738 return 0; in sdma_v4_0_early_init()
1757 return 0; in sdma_v4_0_late_init()
1767 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_sw_init()
1776 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_sw_init()
1785 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_sw_init()
1811 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_sw_init()
1826 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) in sdma_v4_0_sw_init()
1827 ring->vm_hub = AMDGPU_MMHUB1(0); in sdma_v4_0_sw_init()
1829 ring->vm_hub = AMDGPU_MMHUB0(0); in sdma_v4_0_sw_init()
1844 * with 0x400 (4096 dwords) offset on second doorbell page in sdma_v4_0_sw_init()
1846 if (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(4, 0, 0) && in sdma_v4_0_sw_init()
1847 adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(4, 2, 0)) { in sdma_v4_0_sw_init()
1850 ring->doorbell_index += 0x400; in sdma_v4_0_sw_init()
1859 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) in sdma_v4_0_sw_init()
1860 ring->vm_hub = AMDGPU_MMHUB1(0); in sdma_v4_0_sw_init()
1862 ring->vm_hub = AMDGPU_MMHUB0(0); in sdma_v4_0_sw_init()
1887 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_sw_fini()
1893 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || in sdma_v4_0_sw_fini()
1894 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) in sdma_v4_0_sw_fini()
1899 return 0; in sdma_v4_0_sw_fini()
1923 return 0; in sdma_v4_0_hw_fini()
1927 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_hw_fini()
1939 return 0; in sdma_v4_0_hw_fini()
1949 return 0; in sdma_v4_0_suspend()
1964 return 0; in sdma_v4_0_resume()
1975 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_is_idle()
1991 for (i = 0; i < adev->usec_timeout; i++) { in sdma_v4_0_wait_for_idle()
1992 for (j = 0; j < adev->sdma.num_instances; j++) { in sdma_v4_0_wait_for_idle()
1998 return 0; in sdma_v4_0_wait_for_idle()
2008 return 0; in sdma_v4_0_soft_reset()
2020 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_trap_irq_state()
2023 return 0; in sdma_v4_0_set_trap_irq_state()
2034 if (instance < 0) in sdma_v4_0_process_trap_irq()
2038 case 0: in sdma_v4_0_process_trap_irq()
2042 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) in sdma_v4_0_process_trap_irq()
2049 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) in sdma_v4_0_process_trap_irq()
2053 return 0; in sdma_v4_0_process_trap_irq()
2070 if (instance < 0) in sdma_v4_0_process_ras_data_cb()
2088 if (instance < 0) in sdma_v4_0_process_illegal_inst_irq()
2089 return 0; in sdma_v4_0_process_illegal_inst_irq()
2092 case 0: in sdma_v4_0_process_illegal_inst_irq()
2096 return 0; in sdma_v4_0_process_illegal_inst_irq()
2108 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_ecc_irq_state()
2111 return 0; in sdma_v4_0_set_ecc_irq_state()
2122 if (instance < 0 || instance >= adev->sdma.num_instances) { in sdma_v4_0_print_iv_entry()
2127 addr = (u64)entry->src_data[0] << 12; in sdma_v4_0_print_iv_entry()
2128 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in sdma_v4_0_print_iv_entry()
2130 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); in sdma_v4_0_print_iv_entry()
2134 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " in sdma_v4_0_print_iv_entry()
2139 return 0; in sdma_v4_0_print_iv_entry()
2148 return 0; in sdma_v4_0_process_vm_hole_irq()
2155 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); in sdma_v4_0_process_doorbell_invalid_irq()
2157 return 0; in sdma_v4_0_process_doorbell_invalid_irq()
2167 return 0; in sdma_v4_0_process_pool_timeout_irq()
2177 return 0; in sdma_v4_0_process_srbm_write_irq()
2188 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_update_medium_grain_clock_gating()
2202 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_update_medium_grain_clock_gating()
2227 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_update_medium_grain_light_sleep()
2229 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); in sdma_v4_0_update_medium_grain_light_sleep()
2232 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); in sdma_v4_0_update_medium_grain_light_sleep()
2235 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_update_medium_grain_light_sleep()
2236 /* 0-override:disable sdma mem light sleep */ in sdma_v4_0_update_medium_grain_light_sleep()
2237 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); in sdma_v4_0_update_medium_grain_light_sleep()
2240 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); in sdma_v4_0_update_medium_grain_light_sleep()
2251 return 0; in sdma_v4_0_set_clockgating_state()
2257 return 0; in sdma_v4_0_set_clockgating_state()
2265 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_set_powergating_state()
2266 case IP_VERSION(4, 1, 0): in sdma_v4_0_set_powergating_state()
2276 return 0; in sdma_v4_0_set_powergating_state()
2285 *flags = 0; in sdma_v4_0_get_clockgating_state()
2288 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
2293 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_0_get_clockgating_state()
2318 .align_mask = 0xff,
2350 .align_mask = 0xff,
2384 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_set_ring_funcs()
2471 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); in sdma_v4_0_emit_copy_buffer()
2473 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v4_0_emit_copy_buffer()
2503 .copy_max_bytes = 0x400000,
2507 .fill_max_bytes = 0x400000,
2516 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; in sdma_v4_0_set_buffer_funcs()
2518 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v4_0_set_buffer_funcs()
2535 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_set_vm_pte_funcs()
2553 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { in sdma_v4_0_get_ras_error_count()
2573 uint32_t sec_count = 0; in sdma_v4_0_query_ras_error_count_by_instance()
2574 uint32_t reg_value = 0; in sdma_v4_0_query_ras_error_count_by_instance()
2581 /* err_data->ce_count should be initialized to 0 in sdma_v4_0_query_ras_error_count_by_instance()
2585 * set ue count to 0 */ in sdma_v4_0_query_ras_error_count_by_instance()
2586 err_data->ue_count = 0; in sdma_v4_0_query_ras_error_count_by_instance()
2588 return 0; in sdma_v4_0_query_ras_error_count_by_instance()
2593 int i = 0; in sdma_v4_0_query_ras_error_count()
2595 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_query_ras_error_count()
2609 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v4_0_reset_ras_error_count()
2628 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_set_ras_funcs()
2629 case IP_VERSION(4, 2, 0): in sdma_v4_0_set_ras_funcs()
2633 case IP_VERSION(4, 4, 0): in sdma_v4_0_set_ras_funcs()
2645 .minor = 0,
2646 .rev = 0,