Lines Matching +full:0 +full:x00010001

29  *   0x30 == 40 Ohm
30  *   0x28 == 48 Ohm
32 #define IMX6DQ_DRIVE_STRENGTH		0x30
33 #define IMX6SDL_DRIVE_STRENGTH	0x28
44 	.dram_sdba2 = 0x00000000,
67 	.grp_ddr_type = 0x000c0000,
68 	.grp_ddrmode_ctl = 0x00020000,
69 	.grp_ddrpke = 0x00000000,
72 	.grp_ddrmode = 0x00020000,
92 	.dram_sdba2 = 0x00000000,
115 	.grp_ddr_type = 0x000c0000,
116 	.grp_ddrmode_ctl = 0x00020000,
117 	.grp_ddrpke = 0x00000000,
120 	.grp_ddrmode = 0x00020000,
144 	.SRT = 0,
148 	.p0_mpwldectrl0 = 0x00350035,
149 	.p0_mpwldectrl1 = 0x001F001F,
150 	.p1_mpwldectrl0 = 0x00010001,
151 	.p1_mpwldectrl1 = 0x00010001,
152 	.p0_mpdgctrl0 = 0x43510360,
153 	.p0_mpdgctrl1 = 0x0342033F,
154 	.p1_mpdgctrl0 = 0x033F033F,
155 	.p1_mpdgctrl1 = 0x03290266,
156 	.p0_mprddlctl = 0x4B3E4141,
157 	.p1_mprddlctl = 0x47413B4A,
158 	.p0_mpwrdlctl = 0x42404843,
159 	.p1_mpwrdlctl = 0x4C3F4C45,
163 	.p0_mpwldectrl0 = 0x002F0038,
164 	.p0_mpwldectrl1 = 0x001F001F,
165 	.p1_mpwldectrl0 = 0x001F001F,
166 	.p1_mpwldectrl1 = 0x001F001F,
167 	.p0_mpdgctrl0 = 0x425C0251,
168 	.p0_mpdgctrl1 = 0x021B021E,
169 	.p1_mpdgctrl0 = 0x021B021E,
170 	.p1_mpdgctrl1 = 0x01730200,
171 	.p0_mprddlctl = 0x45474C45,
172 	.p1_mprddlctl = 0x44464744,
173 	.p0_mpwrdlctl = 0x3F3F3336,
174 	.p1_mpwrdlctl = 0x32383630,
180 	.cs1_mirror = 0,
190 	.walat = 0,
192 	.rst_to_cke = 0x23,
193 	.sde_to_rst = 0x10,
203 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
204 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
205 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
206 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
207 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
208 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
209 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()